Two-Dimensional Field-Effect Transistors with a Reconfigurable Floating Gate for Logic-in-Memory

Recently, machine learning applications, such as artificial intelligence, neuromorphic computing, and autonomous vehicles, are attracting extensive attention. However, the von Neumann architecture consisting of the separated parts of data processing and data storage has weaknesses in real-time processing and consumes large power. Therefore, there has been a need for energy-efficient electronic hardware without data transport between logic and memory units. In this regard, two-dimensional (2D) materials are considered promising candidates for logic-in-memory. Owing to the atomic thickness and electrostatic controllability, the conductance of 2D field-effect transistors (FETs) can be precisely modulated so that they can be used for reconfigurable logic circuits. However, the logic-in-memory in previous works still shows a large power loss because the used 2D memory devices have only n-type transport. Therefore, it has been required to develop a CMOS-based circuit consisting of p-type and n-type memory devices, which have a low static power consumption and high noise margin. Here, we demonstrate 2D FETs with a reconfigurable floating gate based on the van der Waals heterostructure. By using WSe₂ as an ambipolar channel, the WSe₂ FETs exhibit not only reconfigurable memory operation of n- and p-type polarity but also multiple conductance states. The inverters and circuits based on the WSe₂ FETs show multi-functionality in logic operation with low power consumption. Our work highlights the great potential of atomically thin semiconductors for next-generation low-power electronics.