Content Addressable Memories and Transformable Logic Circuits Based on Ferroelectric Reconfigurable Transistors for In-Memory Computing

As a promising alternative to the Von Neumann architecture, in-memory computing holds the promise of delivering high computing capacity while consuming low power. In this paper, we show that the ferroelectric reconfigurable transistor can serve as a versatile logic-in-memory unit, which can perform logic operations and data storage concurrently. When functioning as memory, a ferroelectric reconfigurable transistor can implement content addressable memory (CAM) with 1-transistor-per-bit density. With the switchable polarity of the ferroelectric reconfigurable transistor, XOR/XNOR-like matching operation in CAM is realized in a single transistor, which can offer a significant improvement in area and energy efficiency compared to conventional CAMs. NAND- and NOR-arrays of CAMs are also demonstrated, which enable multi-bit matching in a single reading operation. In addition, the NOR array of CAM cells effectively measures the Hamming distance between the input query and stored entries. When functioning as a logic element, a ferroelectric reconfigurable transistor can be switched between n- and p-type modes. Utilizing the switchable polarity of these ferroelectric Schottky barrier transistors, we demonstrate reconfigurable logic gates with NAND/NOR dual functions, whose input-output mapping can be transformed in real time without changing the layout and the configuration is non-volatile.<br/><br/><b>Reference</b>: Z. Zhao, J. Kang, A. Tunga, H. Ryu, A. Shukla, S. Rakheja, and W. Zhu, “Content Addressable Memories and Transformable Logic Circuits Based on Ferroelectric Reconfigurable Transistors for In-Memory Computing”, arXiv:2307.03660, (2023)<br/> <br/><b>Acknowledgement</b>: The authors would like to thank the support from Semiconductor Research Corporation (SRC) under grant SRC 2021-LM-3042.