Interface Engineering toward Future Low-Energy and Scalable Ferroelectric Memory

Differing from most nonvolatile memory (NVM) solutions, such as RRAM, PCRAM, STT-MRAM, SOT-MRAM, etc, the switching of a ferroelectric (FE) memory is driven by the electric field rather than the electric current. Its low operating current allows extremely low switching energy and also a compact cell size by reducing the dimension of the access transistor. The promising FE properties of thin Hafnium-Zirconium oxide (HZO) by atomic layer deposition suggest the possibility of achieving a low operating voltage, which is also critical for embedded memory in the logic process. However, some open questions remain for FE memory that might require fundamental material and physical understanding and innovative solutions. First, the thickness and area scalability of FE capacitors that satisfy the strict requirements at the advanced logic nodes remain to be explored. Second, the endurance of FE capacitors is limited by the fatigue-breakdown dilemma. Without robust endurance, the application space of FE memories with the destructive-read feature is limited. Third, the destructive-read feature is also not desirable for performing energy-efficient in-memory computing. One of the nondestructive-read FE memories is the ferroelectric tunnel junction (FTJ). However, the low on-off current ratio and the low read current of FTJ remain problematic. We analyze these challenges from both theoretical and experimental perspectives. We found that the interfaces between FE and metal electrodes play a major critical role in improving these issues. These understandings would facilitate the development of future low-energy and scalable ferroelectric memory.