GeOx-Ge Quantum Dot Assembly for Multistate Spatial Wavefunction Switched (SWS) Field Effect Transistors

<b>Abstract:</b><br/>This paper presents a novel twin-drain Ge quantum dot (QD) spatial wavefunction switched (SWS) field-effect transistor (FET) which demonstrates multistate within a single device. [1-3]. An array of individually cladded quantum dots forms a quantum dot superlattice (QDSL) which exhibits discrete mini-energy bands that have very narrow density of states (DOS) separated by 0.3-0.4 eV. The QDSL serves as: (i) single/multiple transport channel, (ii) quantum dot gate on tunnel oxide, (iii) multiple drain SWS FET. The nanodevices create multiple intermediate logic states in addition to ON and OFF states [4]. The gate voltage determines the threshold for each of the intermediate states. The threshold voltage depends on size of the QD (core and cladding region thickness), gate dielectric thickness and constant. Jain et. al., experimentally demonstrated Si and Ge QD based three- and four-state state FET devices [4-6].<br/>Prior work [1] demonstrated carrier wavefunction switching from lower quantum dot channel to upper quantum dot channel in a multistate SWSFET using SiOx-cladded Si QDs. Ge QDs exhibiting more energy mini-bands will provide additional multiple states and hence versatile multibit processing. We describe processing of a twin-drain SWSFET having four layers of GeOx-cladded Ge QDs self-assembled in the channel region. The upper two QD layers act as the transport channel from source <i>S</i> to drain <i>D₁</i> and the lower two QD layers act as the transport channel from source, <i>S</i> to drain, <i>D₂</i>. The gate voltage, <i>V_G</i>, determines the spatial location of the charges in the upper or lower quantum-wells/-dots in the channel region. This property of the device allows it to encode logic levels at each threshold level of the device for the multivalued logic operation. The location of electrons in lower, upper, both and none encodes the logic states (01), (10), (11) and (00), respectively, which provides a 4-state/2-bit FET operation. In this method, a colloidal solution of cladded Ge QDs is prepared [7] and self-assembled at room temperature. The device sample with Ge dots is annealed at 350 C. The size of the Ge QDs is ~3-4nm with ~0.5 nm GeOx cladding. The experimental characteristics shows multiple state in the FET devices at room temperature.<br/>The low temperature Ge QD preparation and demonstration of multistate within the single device at room temperature operation achieve reduced device count. Further, these novel FETs can be integrated with QD-NVRAMS with CMOS compatible processing. This integration serves as a hardware platform for distributed computing and artificial intelligence applications.<br/><b>References:</b><br/>1. F. Jain, M. Lingalugari, B. Saman, P.-Y. Chan, P. Gogna, E.-S. Hasaneen1, J. Chandy, and E. Heller, “Multi-State Sub-9 nm QDC-SWS FETs for Compact Memory Circuits,” 46 th IEEE SISC, Dec 2-5, 2015.<br/>2. F. Jain, R. Gudlavalleti, R. Mays, B. Saman, J. Chandy, and E. Heller, Integrating QD-NVRAMs and QDC-SWS FET based logic for multi-bit computing, IJHSES, 31, pp.2240020-1, 2022.<br/>3. M. Lingalugari, P.-Y. Chan, E.K. Heller, J. Chandy, and F.C. Jain, “Quantum Dot Floating Gate Nonvolatile Random Access Memory Using Quantum Dot Channel for Faster Erasing”, Electronic Lett., 54, 36, 2018.<br/>4. F. C. Jain, E. Heller, S. Karmakar and J. Chandy, "Device and circuit modeling using novel 3-state quantum dot gate FETs," <i>2007 ISDRS</i>, 2007, pp. 1-2.<br/>5. R. H. Gudlavalleti, P.-Y Chan, R. Mays, E. Heller, F. Jain, “A Novel Peripheral Circuit for SWSFET based Multivalued Static Random Access Memory”, <i>Int. J. of High Speed Electron. Syst.</i>, vol. 29, vo. 01n04, pp. 2040010, 2020.<br/>6. F. Jain, B. Saman, R. Gudlavalleti, R. Mays, J. Chandy and E. Heller, Low-threshold II–VI lattice-matched SWSFETs for multivalued low-power logic, J. Electron. Mater., 50, 2618–2629, 2021.<br/>7. F. Papadimitrakopoulos, T. Phely-Bobin, P. Wisniecki, “Self-assembled nanosilicon/ siloxane composite films,” <i>Chem. Mater.</i>, 11, (3), pp. 522–525, 1999.