Yasuo Cho1,Hiroyuki Nagasawa2,Masao Sakuraba1,Shigeo Sato1
Tohoku University1,CUSIC Inc.2
Yasuo Cho1,Hiroyuki Nagasawa2,Masao Sakuraba1,Shigeo Sato1
Tohoku University1,CUSIC Inc.2
The layer structure of 3C-SiC(111) stacked on 4H-SiC(0001) is expected to be effective in reducing the specific on-resistance (<i>R</i><sub>on</sub>) of power MOSFETs operating at high voltages. This is because the channel is formed in the 3C-SiC layer, which shows low interface density of sate (<i>D</i><sub>it</sub>) at interface with SiO<sub>2</sub>, and the depletion region extends toward the 4H-SiC layer with high breakdown electric field.<br/>Recently, the simultaneous lateral epitaxy (SLE) method, in which 3C-SiC and 4H-SiC are grown transversely at the same time, has been proposed as a technique for fabricating this structure and has attracted much attention[1].<br/>However, there was no specific study that experimentally evaluated <i>D</i><sub>it</sub> at the MOS (SiO<sub>2 </sub>/SiC) interface on the SiC layer grown by SLE and verified the effect of 3C-SiC (111)/4H-SiC (0001) structure with simultaneously formed SiO<sub>2 </sub>oxide film on the MOSFET performance.<br/>On the other hand, we have studied the evaluation of the SiO<sub>2</sub>/SiC interface using scanning nonlinear dielectric constant microscopy (SNDM) and reported that the relative standard deviation (RSD), which is the signal fluctuation (standard deviation) in the SNDM image (d<i>C</i>/d<i>V</i> image) normalized by its mean value, can be used to evaluate <i>D</i><sub>it</sub> [2] and that the local deep level transient spectroscopy (DLTS) method using the time-resolved SNDM (tr-SNDM) method can quantitatively evaluate the two-dimensional distribution of <i>D</i><sub>it</sub> itself [3].<br/>In this paper, by using these two techniques, we characterize MOS interfaces on epitaxially stacked 3C-SiC(111)/4H-SiC(0001) grown by SLE.<br/><br/>References:<br/>[1] H. Nagasawa, European Patent No. EP 4 135 047 A1 (27 April 2021).<br/>[2] Norimichi Chinone, Alpana Nayak, Ryoji Kosugi, Yasunori Tanaka, Shinsuke Harada,<br/>Hajime Okumura, and Yasuo Cho, “Evaluation of silicon- and carbon-face SiO<sub>2</sub>/SiC MOS interface quality based on scanning nonlinear dielectric microscopy”, Appl. Phys. Lett. Vol.111, 061602 (2017).<br/>[3] Yuji Yamagishi, and Yasuo Cho, “Nanosecond microscopy of capacitance at SiO<sub>2</sub>/4H-SiC interfaces by time-resolved scanning nonlinear dielectric microscopy”, Appl. Phys. Lett. Vol.111, 163103 (2017).