High-Performance Oxide Thin-Film Transistors based on Indium with Nano-Iaminate Structure using Plasma-Enhanced Atomic Layer Deposition

Since the discovery of amorphous indium-gallium-zinc oxide (a-IGZO) by the Hosono group in 2004, oxide semiconductors have been intensively studied. a-IGZO, with desirable electrical characteristics such as moderate mobility (~10 cm²/Vs), very low leakage current (&lt;10^-12 A), and reasonable bias stability, gained significant attention in the display industry as a backplane technology due to its low processing temperature (~400°C) and relatively low manufacturing cost. Consequently, a-IGZO became the standard backplane technology for active-matrix organic light-emitting diode (AMOLED) television displays. However, a-IGZO faced challenges in high-end mobile AMOLED displays requiring short switching times due to the high pixel density (ppi). As a result, low-temperature polysilicon (LTPS), which offers high mobility (&gt;80 cm²/Vs) and excellent bias stability, has been predominantly used as the backplane technology for mobile AMOLED displays. Currently, high-end mobile AMOLED displays employ LTPS and oxide (LTPO) technologies for the backplane, consisting of LTPS and IGZO TFTs for driving and switching transistors, respectively. The hybrid concept of LTPO technology can provide high resolution, fast frame rates, and low power consumption simultaneously. However, the challenging manufacturing process of LTPO technology remains a drawback, resulting in high manufacturing costs and low yield rates. Developing oxide TFTs with high mobility and reliability to compete with LTPS TFTs is a demanding engineering task.<br/>In this study, a single diode with a 2 nm confinement layer (CL) thickness of either indium-gallium-oxide (In_0.84Ga_0.16O) or indium-zinc-oxide (In_0.75Zn_0.25O) and a barrier layer (BL) of gallium oxide (Ga₂O₃) was designed to achieve excellent electrical performance in thin-film transistors (TFTs). The formation of multiple channels within the oxide nano-laminate (NL) structure was proven to occur near the CL/BL hetero-interface in the form of a quasi-2D electron gas (q2DEG), where free charge carriers accumulate, leading to superior carrier mobility. The q2DEG near the oxide interface, designed for Fermi level (EF) engineering, was utilized to implement the NL structure in oxide semiconductors by adopting different oxide materials. The engineered q2DEG structure ensures excellent stability by reducing the trap density of the oxide NL compared to single-layer oxide TFTs. The optimized device with In_0.75Zn_0.25O/Ga₂O₃ NL TFT exhibited remarkable electrical performance: a mobility (μFE) of 77.1 ± 0.67 cm²/Vs, a threshold voltage (V_TH) of 0.70 ± 0.25 V, a steep subthreshold swing (SS) of 100 ± 10 mV/decade, an I_ON/OFF ratio of 8.9 × 10⁹, a low operating voltage range of ≤ 2 V, and excellent stability (ΔV_TH of +0.27, -0.55, and +0.04 V for positive bias temperature stress, negative bias illumination stress, and constant current stress, respectively). The improved electrical performance, based on in-depth analysis, is attributed to the existence of q2DEG formed near the carefully designed CL/BL hetero-interface. TCAD simulations were performed theoretically to validate the formation of multiple channels in the oxide NL structure, with the formation of q2DEG near the CL/BL hetero-interface. These results clearly demonstrate that introducing heterojunction or NL structure concepts into this ALD-induced oxide semiconductor system is a highly effective strategy to enhance carrier transport characteristics and improve the bias stability in TFTs.