Effect of Copper Doping on Zinc Oxide and the Potential for Nanowire Devices

While silicon continues to dominate the semiconductor landscape, other materials have shown significant promise in conventional field-effect transistor (FET) devices as well as in optoelectronics and flexible electronics regime, zinc oxide (ZnO) being one of them. The doping of ZnO to generate carriers and consequently, designing devices of interest are active areas of research with several materials touted as possible dopants. In particular, much effort has gone into finding a reliable acceptor doping scheme as it has proven to be complicated to develop p-doped ZnO preventing the widespread use of it in certain applications. The goal of this study is to find the effects of copper (Cu) substitutional doping on ZnO using quantum mechanical computational models namely density functional theory (DFT) in conjunction with semi-empirical tight-binding extended Hückel method and non-equilibrium Green’s function (NEGF). DFT is used for material property determination whereas the semi-empirical model is used for device simulations which provides some key advantages over DFT in the context of this study including a reasonable simulation time for a system with a large number of atoms as is the case with most electronic devices.<br/><br/>Analyses of how selectively supplanting zinc (Zn) with copper (Cu) impacts the electronic properties of the resultant structure and if the alterations can be leveraged to construct nanowire FET devices are performed. The density of states and carrier concentration calculations reveal that Cu doping of ZnO leads to p-type characteristics in the semiconductor. A massive increase in hole concentration to the order of 10¹⁸ cm⁻³takes place after the addition of copper. The resultant structure is then used to build junctionless nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs). The choice of the junctionless variant of the MOSFET is driven by its robust performance in the short-channel domain and fabrication simplicity. The nanoscale device exhibits excellent figures of merit including an on-current (I_on) of more than 500 μA/μm and an on-current to off-current ratio (I_on/I_off ) of greater than 5 × 10⁶ for certain configurations. In addition, several parameters like source/drain underlap length and work function of the gate material among others are varied, and guidelines are presented on optimization concerning I_on/I_off, I_on, and subthreshold swing (SS). The effects of different dielectric materials on the device performance are also studied. It is found that the use of high-κ dielectrics like hafnium oxide (HfO₂) can significantly improve the performance of the device. Furthermore, the merits and challenges of the modeling approach are discussed.