Improved Charge Trapping of Synaptic Flash Memory by TiO₂ Reinforcer

I. Introduction<br/>As AI computing has come a long way in the last decade, synaptic devices in artificial neural networks (ANNs) are recently drawing more attention due to the role of connection between neurons. Among synaptic devices, flash memory has been thoroughly investigated because of high density of data storage and low-voltage operation. However, even conventional flash memory like SiO₂/Si₃N₄/Al₂O₃ (SONOS) device still has a serious issue of nonlinear responses limiting the ability to deal with complicated input patterns. In order to improve the linearity, synaptic devices should have a large window of conductance to afford various input signals. In the present study we suggest new solution to subdue the nonlinearity by enhancing charge trapping.<br/><br/>II. Main Body<br/>2.1 Experimental<br/>The present synaptic devices were fabricated on Si(100) wafers using ETRI’s CMOS fab. Based on thermal oxide of 500 nm, deposition of polysilicon atop and ion implantation were performed in a row to make channel and source/drain. Dielectric complex including tunneling and blocking oxide was formed as SiO₂(3 nm)/Si₃N₄(3 nm)/TiO₂(2 nm)/Si₃N₄(3 nm)/Al₂O₃(9 nm) using plasma enhanced atomic layer deposition at 300°C. The incorporation of TiO₂, an additional charge-trapping layer in the middle of Si₃N, is the main feature of the solution suggested. Finally, we adopted TiN and aluminum as gate and electrode materials, respectively.<br/>Transfer properties of the implemented devices were measured using parameter analyzer for single and multiple pulse condition while keeping both programming (PRM) and erasing (ERS) voltages fixed. Input signal was a square-type pulse with duration of 2 sec in single pulse. On the other hand, we investigated conductance change under multiple pulses to simulate real ANNs by applying 10⁶ pulses with both duration and interval of 10 msec<br/><br/>2.2 Results and Discussion<br/>We extracted from measured transfer curves conductance change between PRM and ERS states of TiN/Al₂O₃/Si₃N₄/SiO₂/poly-Si (TANOS) and TiN/Al₂O₃/Si₃N₄/TiO₂/Si₃N₄/SiO₂/poly-Si (TAXOS) devices. Both devices show much lower PRM and ERS voltage (9 V) than conventional SONOS device (~ 20 V). Furthermore both devices show largest conductance span near the gate voltage of 1 V, which is small enough to reduce the burden of power issue.<br/>The difference of conductance △G between PRM and ERS states are compared both for TANOS vs. TAXOS and single vs. multiple pulse condition, respectively. As a result, the conductance span of TAXOS is superior to TANOS both for single (△G_s = 3.6x10⁴ S vs. 1.7x10² S) and multiple pulse condition (△G_m = 1.5x10⁴ S vs. 2.6x10³ S). The conductance span of TAXOS is one to two orders of magnitude higher than that of TANOS. The increased DG can keep more input signals contained in TAXOS device improving the linearity aforementioned. Furthermore, the wide tunability of conductance enables TAXOS synapse to catch even smaller change of input signals facilitating more accurate learning in ANNs.<br/>This improvement of conductance span in TAXOS is attributed to TiO₂ layer. TiO₂ has large dielectric constants of tens to hundreds depending on crystalline structure, thereby it can be regarded as a reinforcer of charge-trapping. Although we have not yet fully understood the trapping mechanism, its electron-deficient stoichiometry may be able to enhance the charge trapping capacity.<br/><br/>III. Conclusions<br/>We suggested new synaptic flash device of TAXOS that enhances charge-trapping capacity due to TiO₂ layer. TAXOS shows larger conductance span (tens to hundreds times) between PRM and ERS states than TANOS, which would be able to improve linearity in synaptic response. Through this study we noted that very high-k electron-deficient TiO₂ plays a role of reinforcer in charge-trapping operation despite a necessity to explore theoretical mechanism yet.