Self-Assembly of Dense, Aligned, Semiconducting Carbon Nanotube Arrays for High Performance Transistors

Carbon nanotubes conduct more electricity per width than silicon and more rapidly switch between on and off states with less voltage, making them ideal for next-generation fast, low-energy logic and high-speed, linear RF devices. However, despite carbon nanotubes’ promise, no one has yet been able create a process for employing nanotubes in high-performance electronics commercially. Since their discovery more than 25 years ago, nanotubes’ commercialization has been delayed by manufacturing challenges in purifying, aligning, and uniformly assembling them with precision over large areas. For nanotubes to be most useful, they must be purified by their electronic type (semiconducting versus metallic) and then lined up in the same direction in a dense layer with the thickness of a single nanotube, so that electricity can rapidly and efficiently travel through them.<br/><br/>This talk will present recent discoveries on (1) purifying and aligning semiconducting nanotubes into massively parallel arrays and (2) the research and development of semiconducting carbon nanotubes for logic and radio frequency devices. We have pioneered nanotube array fabrication technologies that enable the (a) partial alignment of nanotubes (±30^o) via shear (demonstrated 100 mm wafer-scale); (b) finer alignment (±6^o) at liquid-liquid interfaces (demonstrated 100 mm size-scale); and, (c) the selected-area deposition of nanotube arrays (±7^o) in lithographically-defined patterns combining topographical and chemical features (demonstrated 25 mm size-scale). Most recently, we have discovered a powerful new mechanism for driving the self-assembly of nanotubes into aligned arrays, by coaxing them to form two-dimensional liquid-crystals. We have uncovered that when nanotubes are segregated to liquid-liquid interfaces, mesogenic interactions cause them to self-align (within +/-5.7 degrees so far) and self-assemble into dense arrays (&gt; 100 per micron) like those needed for microelectronics. The assembled nanotubes are easily integrated on silicon substrates at room-temperature and integrated into high-performance devices. Work on the development of novel multifunctional polymer wrappers and the removal of these wrappers will also be presented.<br/><br/>APL (2014); ACS Nano (2014); Langmuir (2014); Science Advances (2016); Langmuir (2017); Adv Elect Materials (2019); Science Advances (2021); Nanoscale Advances (2021); JAP (2022); Submitted (2023). Highlights by Bloomberg News https://youtu.be/VsUF_CBJq50 (2022); US Patents 11,631,814; 10,873,026; 10,074,819; 9,938,149; 9,786,853; 9,728,734; 9,673,399; 9,425,405; 9,368,723; 9,327,979.