Anchoring to Prevent Bundling in Dense CNT Array Device Process

Carbon nanotubes (CNTs) are highly promising candidates for replacing silicon (Si) in digital devices due to their remarkable characteristics, including a 1-nm thin body, high mobility/velocity, and low capacitance. To achieve high-performance devices, there is a demand for high-density aligned CNT arrays with a pitch size of 2~4 nm. Significant progress has been made recently in CNT array assembly through the dimension-limited self-alignment method, along with the use of small molecule additives to suppress CNT bundling.<br/>However, the various processing steps involved in fabricating CNT field-effect transistors (CNTFETs) introduce extrinsic defects, such as lateral aggregation and vertical stacking, into the as-prepared CNT arrays. The presence of such CNT bundles can severely impact the ability of the transistor gate to effectively control the flow of charge carriers in the CNT channel, leading to considerable device-to-device variability.<br/>In response to these challenges, this study proposes the incorporation of dielectric anchors to prevent CNT bundling. Through the use of Atomic Force Microscopy (AFM) and Transmission Electron Microscopy (TEM), we investigate the CNT bundling conditions after essential processing steps, including post-evaporation, post-Atomic Layer Deposition (ALD), post-resist spin-coating, post-developing with the anchor layer, and without the anchor layer.<br/>By implementing the anchoring-first approach, we demonstrate reduced subthreshold slope variation (SS) and higher drain current (Ion) in CNTFETs. These findings present a promising process flow to construct high-performance CNTFETs, thereby advancing CNTFET fabrication towards practical applications in digital devices. The elimination of CNT bundling and improved device characteristics achieved through this study are crucial steps towards the realization of high-performance CNT-based electronics.