Multi-Level Generation Mechanism in Basic Floating Gate Memory Structure

Recently, researches on high-density memory have been focused to develop AI implementation or high-performance memory. Accordingly, interest in multi-level memory began to surge. In the early days, these researches were conducted using the characteristics that change with the current level by controlling the range of the gate voltage for multi-level implementation. And recently, they have been conducted for improving the performance of existing devices using modification of device structure or additional processes such as light source or plasma. However, compared to the areas where these applied studies are actively conducted, basic research is insufficient. Therefore, we investigated the multi-level generation mechanism in the floating gate memory of the basic structure and conducted a study to control and predict the number of multi-level using this. We fabricated floating gate memory devices using two-dimensional materials. MoS₂ was used for the channel, hBN for the tunneling insulating layer, and graphene for the floating gate. SiO₂/Si substrates were used as the gate insulating layer and the gate electrode under two-dimensional materials. We took advantage of the characteristic that the current level changes from the reading voltage by controlling the range of the gate voltage mentioned above, and the characteristic that the slope of the transfer curve of the transistor changes according to the thickness of the insulating layer in that the floating gate memory is similar to the transistor structure. As a result of the experiment, multi-level was implemented in a floating gate memory device having a basic structure, and the number of multi-level was controlled by tuning the thickness of hBN.