Van der Waals Stacked Synapse Transistor Based on Efficient Charge-(de)trap Flash Memory

The development of two-dimensional (2D) materials based synaptic devices has been of considerable interest owing to their highly gate-tunable charge transport and efficient charge transfer across van der Waals (vdW) stacks. In this study, we demonstrate a vdW synapse transistor, exclusively built with 2D materials by <i>i</i>) controllably oxidizing the surface of environmentally sensitive HfS₂ to form the HfO_x/HfS₂ floating gate stack and then <i>ii</i>) assembling with other stable channel materials, few-layer MoS₂. For the flash memory device, electrons were injected through tunneling oxide HfO_x, which is uniform and ultrathin native oxide, and trapped in floating gate HfS₂. As a result, we can precisely modulate trapped charge density by controlling the gate voltage level and the device characteristics show large memory window (&gt; 100 V), high on/off ratio (&gt; 10⁶) and good retention performance. Furthermore, HfO_x/HfS₂ floating gate can be additively stacked to enhance the linearity of conductance update as a synaptic emulator. Our work will provide a facile device configuration for efficient neuromorphic computing as well as synaptic transistor.