High Performance P-Type Metal Oxide Field-Effect Transistors for Large-Area Monolithic Three-Dimensional Integration

Over the past few decades, Si-based field-effect transistor (FET) technology has steadily advanced, enabling tremendous advancement in device performance and the realization of sub-10 nm dimensions. However, it has reached the physical limit to continuously downscaling the size of the devices. Monolithic three-dimensional (M3D) integration has emerged as a promising technology because it allows more devices to be connected vertically in the same area for greater integration. Also, the M3D integration of several devices such as memory or drive array on top of complementary metal oxide semiconductors (CMOS) logic circuit facilitates the improvement of speed and power consumption. To implement the fully M3D integration of FETs on the top of the CMOS devices, the low-temperature process under 400 °C is essential because a high temperature negatively affects the performance of underlying CMOS logic circuits. Considering low-temperature processability, large-scale uniformity, transparency and excellent electrical properties, metal oxide semiconductors are one of the best candidate materials for M3D integration.<br/>Unlike the successful development and commercialization of n-type metal oxide FETs, the progress in p-type metal oxide FETs has so far not been impressive. Therefore, it is challenging to develop the p-type metal oxide semiconductors that are capable of realizing high-performance FETs. Tin monoxide (SnO) is one of the most promising p-type metal-oxide semiconductors because of its small effective mass and large direct bandgap, providing excellent hole conductivity. Also, recently, ultrathin tellurium dioxide (TeO₂) is emerging as promising p-type semiconductor with high mobility.<br/>Here, we report on the sputtered p-type metal oxide FETs and circuits with high device performances. First, the high performance p-type SnO FETs with high field-effect mobility (<i>μ</i>_h) over 3.8 cm²/Vs, large on/off ratio over 10⁵ and low subthreshold swing of 800mV/dec are demonstrated at an annealing temperature of 250 °C. By optimizing the device manufacturing process, we have realized a large-area p-type SnO FET with high uniformity on a 6-inch wafer. Second, sputtered p-type TeO₂ FETs with excellent <i>μ</i>_h of 8 cm²/Vs at 150 °C are reported. We systematically investigate the structural, optical, and electrical properties of SnO and TeO₂ films using X-ray photoelectron spectroscopy, UV-Vis spectroscopy, X-ray diffraction, transmission electron microscopy and atomic force microscopy analyses, respectively. Finally, vertically integrating p-type FETs with n-type ones are demonstrated for M3D applications.