Directly Photo-Patternable High-k Polymer Gate Dielectrics for Oxide Thin-Film Transistors

Recently, the increasing demand for high-end displays has led to the development of flexible displays using non-traditional flexible substrates rather than traditional rigid substrate. Currently, thin-film transistors (TFTs) for flexible devices mainly use inorganic dielectrics such as SiO2, and Al2O3. These inorganic gate dielectric have critical issues to applicate in flexible devices because of their high temperature process, high-cost production, and limited flexibility. Therefore, the mass production yield inevitably decreases, leading to increase in price of devices. From this point of view, polymer dielectrics have attracted considerable attention as a gate insulator for flexible transistors because of their mechanical nature.<br/>Generally, organic dielectrics are fabricated with solution process, such as spin coating. Spin coating process can be easy and cheap method, however, the quality of films is not as good as the one with vacuum process because of the residual impurities and thermal damage to the substrate during post-coating bake. Poly(chloro para-xylylene) (Parylene) can be fabricated via pyrolysis-CVD process at room temperature, which lead to unique characteristics of pinhole-free nature. Also, electrical properties of parylene films are enough to utilize as dielectric layer of TFTs. However, dielectric properties of parylene are quite low compare to conventional inorganic dielectrics such as SiO2, and Al2O3.<br/>To define the dielectric layer with pattern, photolithography and etching process is required. There are some reports about photopatternable organic and hybrid (organic-inorganic) dielectric layer. However, they require post treatment such as thermal annealing in order to obtain proper properties or etching process to remove residual. These process can affect other component in thin-film transistors, especially semiconductors.<br/>In this work, custom-synthesized poly(para-xylylene) (parylene) based polymers were evaluated as alternative gate dielectric layer for TFTs. Here, oxide semiconductors were adopted for active layer to demonstrate high performance TFTs. Unlike most polymers fabricated by the solution process, fabrication process for parylene is based on a CVD system, which can provide a thin, conformal and pinhole-free film, leading to compatible interface to oxide materials. In addition, deposition temperature is around room temperature and no additional high-temperature annealing is required, so it does not affect to plastic substrate with low glass transition temperature for flexible or stretchable applications. Parylene synthesized by our material design exhibits dielectric constant of more than 6, which is more than twice higher than that of the three commercialized types of parylene (parylene-C, Parylene-D, Parylene-AF4) without degradation of leakage current (&lt;10-9 A/cm2). Also, custom-synthesized parylene can be directly patterned by UV treatment without additional post treatment.