Catherine Labelle1
Intel Corporation1
Etches for advanced semiconductor technologies are asked to deliver many things: critical dimension (CD) targeting, depth targeting, profile targeting, selectivity between various materials, etc., and then reproduce that result across-wafer, wafer-to-wafer, lot-to-lot, and chamber-to-chamber. As technology innovation has progressed, the length scale at which these parameters are required has shifted from microns to nanometers, and now to angstrom-level. In some memory technologies, variations in CD can influence the volume of the cell and therefore the performance of the cell. In some other technologies, the challenge is to control the profile over a high aspect ratio, which can be complicated further if there is more than one film involved. So, if a device is sensitive to CD and profile variations and the length scale of sensitivity is now in the angstrom regime, etch characterization parameters need to evolve to incorporate detecting changes at that scale. For instance, in addition to CD uniformity (CDU), which is typically measured across a wafer, *local* CDU (LCDU) needs to be understood since it is no longer in the noise of the overall CDU from a device perspective. Line/space edge/width roughness (LER/LWR/SER/SWR) also needs be considered as a function of the desired CD and space. The etch processes themselves need to be thought through from this perspective since different mechanisms drive local vs. across-wafer behaviors. Standard controls such as optical emission spectroscopy (OES) endpoints may also need to be re-thought since cyclic processes such as Atomic Layer Etch (ALE) can eliminate traditional endpoint signals. This talk will explore some of the challenges of operating in an angstrom-level regime and the evolution of thinking needed in designing etch processes needing to deliver in this regime. Data will also be shown for several cases where these challenges are being met.