Novel Nanospike Array Electrodes for Enhanced-Performance 50 NM-Channel MoS₂ Thin-Film Transistors

There has been a great deal of research interest in scaling down the channel lengths in MoS₂ thin-film transistors (TFTs). However, when the channel length reaches the nanometer scale, transistors start experiencing short channel effects, including low on/off ratio, degraded subthreshold swing, and drain-induced barrier lowering (DIBL), etc. This abstract introduces an alternative to overcome short channel effects for transistors with channel lengths below 100 nm. Conventionally, MoS₂ TFTs have been fabricated with flat edge source and drain electrodes. By changing the shape of the source/drain electrodes into nanospike-like structure, transistors can overcome short channel effects and regain gate control. Furthermore, patterning the source and drain contacts into nanospike array electrodes can improve the on-current of the transistors as well. 50 nm-channel length MoS₂ TFTs with nanospike array electrodes were fabricated along with the conventional flat edge electrodes for direct comparison.<br/>The 17 nm thick source/drain electrodes (Cr/Au) were patterned on 90 nm of SiO₂ coated silicon substrates using electron beam lithography (EBL). Mechanically exfoliated 5 nm few-layer MoS₂ and 20 nm thick hBN were transferred onto the preformed contacts. A 100 nm thick Au top gate was patterned with EBL and thermally evaporated. The nanospike tips are 200 nm wide equilateral triangles with a 1 μm long rectangular base extending orthogonally from conventional flat electrodes. The channel length, defined as the distance between the tips of the source and drain spikes, is approximately 50 nm. The total channel width is 3.4 mm with 5 pairs of nanospikes spaced evenly from each other.<br/>Nanospike electrodes provide a unique bias-dependent charge flow pattern, which is responsible for the improved performance. Enhanced electric field results in increased charge injection from the tips of the nanospike electrodes and improves channel length scaling to sub-50 nm while maintaining excellent current modulation. The spacing between each pair of nanospikes also plays an important role. Larger spacing accentuates the formation of individual charged nanoribbons between source and drain, and the increased channel width from having larger spacing also helps improve the on-current as well. The transfer characteristics of nanospike TFTs demonstrate an on/off ratio of ~10⁷ while this ratio is typically 10² or less for devices with flat edge electrodes. Increased drain current (35 μA/μm vs. 25 μA/μm) and reduced contact resistance (40 kΩ μm vs. 52 kΩ μm) are also observed for the nanospike devices.<br/>The 50 nm MoS₂ TFTs was connected in series with a 15 kΩ resistor to assess the characteristics of an inverter. With a supply voltage of 2 V, the circuit is on with an output voltage of 2 V at negative input voltages and an output voltage of near 0 at positive input voltages. The circuit gain was calculated to be approximately 3.75. The intrinsic gain (g_mr_o) of the device reaches 300 in the subthreshold regime, which is much higher than the intrinsic gain that can be achieved by silicon under subthreshold condition. The high intrinsic gain is a result of reduced DIBL and improved sub-threshold swing due to charged nanoribbon formation and enhanced gate control. This opens up the possibility for high performance subthreshold circuits with low power dissipation for applications such as neuromorphic computing and energy efficient logic. In summary, the use of nanospike array source/drain electrodes shows a step towards scalable, multi-functional, and high-performance MoS₂ TFTs.