Effect of Plasma Etching on the Transport Properties and Electrical Stability in Transition-Metal Dichalcogenide Field-Effect Transistors

The application of two-dimensional (2-D) layered transition metal dichalcogenide (TMDC) for high-performance large-area memory applications requires establishing long-term electrical stability through an understanding of the carrier transport and the effect of the materials processing on the device behavior. A novel approach for creating arrays of thin-film and few-layer molybdenum disulfide (MoS₂)-based field-effect transistors was achieved through a mechanical exfoliation and a dry etching process. The current-voltage (I-V) and electrical stability characteristics showed that the etching process can effectively remove intrinsic bulk defects within the TMDC layers and create few-layer device structures. The as-transferred thin-film transistor (TFT) structures, having thicknesses of ~ 90 nm, were found to have a trap density of approximately 3×10¹⁰ cm^-2 per monolayer. This defect density was observed to decrease when the layers were removed using a SF₆/O₂ plasma etching process, resulting in a positive threshold voltage shift in the transistor operation. The process was effective in removing bulk defects in the MoS₂ layers causing a positive threshold voltage shift of +40V with a final threshold voltage of -12V for a 3 nm thick layer. Conversely, the measured transport properties and electrical stability was found to degrade when the thickness of the MoS₂ layer was < 15 nm. This observed degradation was due to the etched backchannel layer moving closer to the active channel region as the TMDC layer was thinned. The transport properties of the transistor were affected by surface states along the backchannel contributing to carrier scattering as the thickness of the semiconductor approached the accumulation layer in the transistor. The same surface states acted as trap centers in the semiconductor degrading the electrical stability of the devices. This effect was becoming more pronounced as the proximity of the TFT backchannel surface approached the active channel region during etching. Finally, the effect of passivation layers on the etched backchannel will be presented for an array of TDMC devices for large-area memory applications.