MRS Meetings and Events

 

NM06.15.08 2022 MRS Fall Meeting

Threshold Voltage and On-Off Current Ratio Tuning of MoS2 Transistor

When and Where

Dec 6, 2022
10:10pm - 10:15pm

NM06-virtual

Presenter

Co-Author(s)

Fatemeh Khorramshahi1

VTT Technical Research Center of Finland1

Abstract

Fatemeh Khorramshahi1

VTT Technical Research Center of Finland1
Immunity to short channel effects and abrupt switching along with transparency and flexibility have made 2D molybdenum disulfide (MoS<sub>2</sub>) transistors compelling to be used in digital logic circuits. However, difficulties in obtaining a positive threshold voltage (V<sub>th</sub>) have hindered its application as in digital logics, an incorrect V<sub>th</sub> can lead to large short-circuit power consumption during switching. Similarly, a poor ON/OFF current ratio (I<sub>on</sub>/I<sub>off</sub>) can cause impractically low output swings and high leakage.<br/>In this work, we employed the strategy of tuning the work function of gate metal using an ALD-grown metal plus thinning the gate oxide dielectric in order to reduce the trap states to shift the threshold voltage towards the positive direction and increase I<sub>on</sub>/I<sub>off</sub>. To achieve that, two series of transistors were fabricated using a bottom gate structure on silicon substrates. The transistor's channel lengths varied from 1.5 um to 40 um and the channel widths varied from 10 um to 160 um. In one series of transistors, niobium was deposited as the gate metal and 35 nm aluminum oxide (Al<sub>2</sub>O<sub>3</sub>) was used as the gate dielectric. In the second series of transistors, titanium nitride (TiN) and 12 nm Al<sub>2</sub>O<sub>3</sub> were used as the gate metal and the gate dielectric respectively. A CVD-grown multilayer MoS2 was wet transferred to the structure and used as the gate channel.<br/>The electrical characteristics of the transistors were measured in the ambient environment and under dark conditions. A virtual source (VS) model was used to fit a curve on the measured data. The extracted transistors parameters from the fitted curves for the two series of transistors were compared. It was observed that the device performance enhanced significantly when TiN and thinner Al<sub>2</sub>O<sub>3</sub> were deposited as the gate metal and the gate dielectric. While as-fabricated devices with Nb and 35 nm Al<sub>2</sub>O<sub>3</sub> showed a negative threshold voltage of ~ -3 V, the device threshold voltage shifted toward the negative direction over time and by keeping the sample in the ambient environment. The I<sub>on</sub>/I<sub>off</sub> of these devices did not exceed 10<sup>4</sup>.<br/>The transistors using TiN gate metal and 12 nm Al<sub>2</sub>O<sub>3</sub> with the W/L ratio of 160/10 showed the ON-OFF current ratio of 10<sup>6</sup> with the ON current of 11.4 uA at V<sub>ds</sub> of 1 V and V<sub>gs</sub> of 5 V and the threshold voltage of 1.1 V. The average threshold voltage of the transistors fabricated using TiN gate metal and thin Al<sub>2</sub>O<sub>3</sub> dielectric layer for different W/L ratios was 1.3 V. We were able to adjust the threshold voltage to the positive values and tune the on-off current ratio across 10<sup>4</sup> to 10<sup>6</sup>. This study shows a comparably simple strategy for the fabrication of MoS<sub>2</sub> transistor for low power consumption logic circuits for industrial applications.

Symposium Organizers

Nicholas Glavin, Air Force Research Laboratory
Aida Ebrahimi, The Pennsylvania State University
SungWoo Nam, University of California, Irvine
Won Il Park, Hanyang University

Symposium Support

Bronze
MilliporeSigma

Publishing Alliance

MRS publishes with Springer Nature