Novel Patterning Solutions For Scaling Interconnects Beyond 2030

<br/>In addition to improved transistors, interconnects, and advanced packaging, scaling is a major factor in the improvement of semiconductor product performance. Scaling improves product performance by enabling lower capacitance and lower power systems, by enabling more functionality per logic block through use of additional transistors and by enabling either more cores or memory capacity per chip. Scaling is enabled by innovations in patterning, power delivery and transistor architecture. Stacked transistor architecture is expected to follow gate-all-around architecture for continued improvement in performance and density. Such an architecture could reduce the cell size by approximately 50% due to cell height reduction. However, to efficiently route an aggressively scaled cell with stacked transistors, the metal and interconnect pitch must be scaled to levels that are difficult to achieve with conventional patterning techniques. Variation control is the key challenge to pitch scaling as the edge placement margin of error is small and the large number of features required for modern circuits implies stochastics sampling in the greater than 7 sigma regime. Solutions are needed to address each component of variation, such as line roughness and size variation, via size variation, line-end pullback and overlay. One example of a powerful complementary lithography technique with superior variability control is directed self-assembly (DSA). DSA offers a fundamental advantage over conventional lithography since the line and space CDs are chemically encoded into each molecule with unprecedented accuracy. We will report on recent progress made for a process flow based on DSA that rectifies complex, multi-pitch and multi-CD EUV patterns with low integrated defects, robust electrical yield, and compatibility with standard design rules.