A Method for Extracting 2D Semiconductor Mobility in Transistors with Gate-Voltage-Dependent Contact Resistance

When and Where

Apr 25, 2024
10:45am - 11:00am

Room 344, Level 3, Summit

Presenter

Robert Bennett

Lauren Hoang

Connor Cremers

Andrew Mannix

Eric Pop

Co-Author(s)

Robert Bennett¹,Lauren Hoang¹,Connor Cremers¹,Andrew Mannix^1,2,Eric Pop¹

Stanford University¹,Stanford Institute for Materials and Energy Sciences²

Abstract

Robert Bennett¹,Lauren Hoang¹,Connor Cremers¹,Andrew Mannix^1,2,Eric Pop¹

Stanford University¹,Stanford Institute for Materials and Energy Sciences²

Emerging two-dimensional (2D) semiconductors are frequently characterized in terms of their electron and hole mobilities, which quantitatively describe the speed at which these carriers move through a material under an applied electric field. These mobilities are commonly extracted by fabricating and measuring field-effect transistors (FETs) and applying one of several techniques to estimate the 2D semiconductor’s electron or hole mobility. Back-gated FETs are often used for these extractions because they can be fabricated in fewer steps and in higher yields compared to top- or dual-gated geometries. However, back-gated FETs experience contact gating: the electric field from the gate electrode acts on the transistor’s source and drain, causing the contact resistance to decrease as the magnitude of the gate voltage increases [1–5]. Although contact gating increases the drive current that a 2D FET can achieve by minimizing contact resistance in the on-state [1, 3, 6], contact gating also modifies the shape of a transistor’s transfer characteristics (i.e., ID vs. VGS characteristics, where ID is the drain current and VGS is the gate-to-source voltage). Consequently, conventional mobility extraction techniques can overestimate the mobilities of emerging semiconductors in back-gated FETs by up to an order of magnitude [2–4]. Thus, it was suggested that mobility in back-gated FETs should be estimated only at high |VGS| (>> |VT|, the threshold voltage) to ensure that the channel resistance, rather than contact gating, dominates the FET transfer characteristics [2, 4]. Alternatively, mobility can be accurately extracted from FETs with more complicated geometries and fabrication procedures that allow for the effects of contact gating to be eliminated (such as FETs that incorporate additional terminals to probe the channel [7]). Although these approaches may be viable in some situations, the former method can be unsuitable for transistors that experience early dielectric breakdown, whereas the latter approach can introduce additional experimental complexity during fabrication. In this work, we propose a method of extracting a semiconductor’s carrier mobility that is compatible with back-gated FETs but that does not require the FET to operate in a channel-dominated regime. This method is inspired by the conventional transfer length method (TLM) approach but makes use of a transistor’s ID vs. VDS characteristics (where VDS is the drain-to-source voltage), rather than its ID vs. VGS characteristics, allowing us to properly account for contact gating in back-gated FETs without having to use complicated geometries to directly probe the channel. We validate this proposed method using current-voltage characteristics simulated by technology computer-aided design (TCAD). We find that this proposed method offers accurate mobility extraction (< 10% error) in regimes where conventional methods (including the linear extrapolation method, Y-function method, and TLM approach) overestimate mobility by > 50%. Furthermore, we demonstrate that this proposed method is robust to random variation in material quality, and we experimentally validate this method by demonstrating that experimentally-measured current-voltage characteristics of back-gated monolayer tungsten disulfide (WS2) FETs fit the method well. Overall, we anticipate that the method we propose in this work will allow for the mobilities of emerging semiconductors to be more quickly and easily extracted without requiring sophisticated transistor geometries or complicated fabrication procedures. References: [1] Z. Cheng et al., Nat. Electronics, 5, 416 – 423 (2022) [2] E. Bittle et al., Nat. Comm., 7, 10908 (2016) [3] J. Nasr et al., Adv. Mater., 31, 1806020 (2018) [4] I. McCulloch et al., Science, 352, 1521 – 1522 (2016) [5] W. Liu et al., ACS Nano, 9, 7904 – 7912 (2015) [6] G. Arutchelvan et al., Nanoscale, 9, 10869 – 10879 (2017) [7] C. Pang et al., Small, 17, 2100940 (2021)