Integration of Logic and Memory Functionalities Enabled by Asymmetric Dual-Gate Structure

Conventional van Neumann computing architecture suffers from the massive time and energy waste due to theseparation of memory and processing units. Logic-in-memory architecture has emerged as an aggressive approach toimprove the computing efficiency, which demands for the higher integration of circuits. However, silicon-based system is facing the challenge of short channel effect, approaching to the limitation of Moore’s law. Thus, two-dimensionallayered semiconductors are emerged as candidates for realizing down-scaled semiconducting devices. Thanks to theiratom-scale thickness, the absence of dangling bonds and enhanced external field control, dual-gated FET is a practical configuration for more complicated applications. The top gate can be in sole control of the channel or utilized in reconfigurable modulation with a back gate. The top gate can also enhance the crucial parameters of transistors such as carrier mobility, on/off ratio and subthreshold swing value due to the capacitance coupling. Both independent and dependent gate control give rise to the probability in extending logic and memory functionalities of a single device unit.<br/>In this work, we fabricate a two-dimensional field-effect transistor (FET) with an asymmetric dual-gated structure, where the top gate comprises the channel, which fulfils the logic and memory operations, typically in opposition to the common approach. The dual-gated FET(DGFET) is based on vertically stacked MoS₂−hBN−In₂Se₃ van der Waalsheterostructure. First, the DGFET can be functioned as a logic gate. The channel material MoS₂ with atomically thin body is sensitive to the electrostatic field, thus dual-surfaced channel and drain/source barriers are modulated by the top and back gates, respectively. The current level in the output presents a logic AND gate performance, giving rise toincrease the circuit density. Second, the DGFET can be operated as a non-volatile memory device. Our as-fabricateddevice exhibits a large memory window (up to 50 V), a high on/off ratio (≈ 10⁵ ) and a long data retention (&gt;80% data storage after 10 years). Also, the DGFET demonstrates the multibit storage state controlled by varying gate voltagepulses. The mechanism of the carrier trapping in the top gate is reported, the asymmetric gate design causes the capacitance coupling between top gate and bottom gate. The writing and erasing processes are original from the combination of capacitance coupling and charge tunneling. Besides, with photogate assisted, logic OR gate can be achieved in the DGFET due to the photo switchable property. The high value of photocurrent provides the feasibility to implement multilevel photo-erasing, and device shows 10 distinct states under different illumination powers and durations.