Dual Gate Electrochemical and Transistors and Inverters based on WO3 for Improved Transconductance and Dynamic Response

Electrolyte-gated transistors (EGTs) and electrochemical transistors (ECTs) have received special attention over the last decade due to their advantages, deriving from using electrolytes as gate dielectrics. These include low operating voltages, printability and solution processability, low contact resistances, and the possibility of fabricating new device architectures. High driving currents due to electric double layer (EDL) capacitance (C DL ) in EDL transistors (EDLTs) or 3D-channel formation in ECTs, complement the list and open routes for their application in biosensors, electrochemical logic gates, wearable electronics, or low-power consumption and flexible devices..<br/>This work shows a novel architecture of ECTs based on the electrochromic material WO3. Introducing a fourth electrode behind the channel (Back-electrode -BE) stabilized drain current, as electrons can be channeled into the active layer for electrochemical reactions. Additionally, control over the ion movement in the channel and the electrolyte and, consequently over the occurring redox reactions is possible. As a consequence thereof, it was found that Von can be controllable through the applied voltage at the BE (VBE ) and that VOn can be shifted from any negative VG up to 0 V and possibly beyond. The devices can be ‘programmed’ to work in normally-off (enhancement) or normally-on (depletion) mode. On-Off ratios of 10⁵ and transconductances of 0.35 mS were achieved. Dynamic characterization with an asymmetric square (VG between -6 and 4 V) wave potential demonstrated On-Off ratios of 4 orders of magnitude for frequencies up to 1 Hz. Data suggests that the cut-off frequency lies way beyond that value. It was demonstrated that with precise control over VOn, electrochemical logic inverters with two identical devices are feasible, presenting very high and controllable gains. The possibility of keeping load and driver transistors respectively at normally-on and normally-off makes transistor sizing redundant. Further, with this transistor architecture, problems like small logic swings or small noise margins, usually related to enhancement-load inverters, can be counteracted.