Large Area Phase Selection in Silicene by Interface Engineering

The synthesis of two-dimensional (2D) silicene by direct growth on Ag(111) substrate is usually qualified by the formation of multiple phases and domains, posing severe constraints on the spatial charge conduction towards a technological transfer of silicene to electronic transport devices. Here we engineer the silicene/silver interface by two different schemes, namely through decoration with Sn atoms, forming an 2D Ag₂Sn surface alloy (surface decoration scheme), or through an epitaxially grown silicene-stanene heterostructure with stanene buffering the substrate (heterostructure scheme) [1]. Based on in situ low energy electron diffraction (LEED) we observe that phase selection is obtained via the two interface engineering schemes. In details, a 4×4 and √3×√3 single silicene phase are selectively stabilized in the surface decoration and heterostructure scheme, respectively. The two selected phases in both case separately, are well-distinguished by characteristic phase-sensitive Raman spectra taken after top encapsulation of silicene with a sequentially grown nanoscale Al₂O₃, and upon probing the surface by positional LEED and Raman scanning, they prove to be extended all over the whole growth area, namely on the cm² scale. Interface engineering by surface decoration also stabilizes the ordered growth of a √3×√3 phase in the multilayer range, featuring a single rotational domain instead of the multiple domain formation upon direct growth. Theoretical<i> ab initio</i> models are used to investigate low-buckled silicene phases (4×4 and a competing √13×√13 one) and various √3×√3 structures, supporting the experimental findings [2]. Interface engineering with the heterostructure scheme is also functional to design an all-around encapsulation of silicene, entailing the top and the bottom face of silicene [3]. This processing step is structurally preparatory to extract the silicene from its native Ag substrate with no occurring environmental degradation (e.g. oxidation). Stabilization of Ag-free silicene is explained in terms of the sacrificial role played by the bottom stanene layer. Based on close Raman spectroscopy monitoring, we are able to certify the endurance of the silicene in the monthly scale.<br/>Interface engineering of silicene as reported in Ref. [2] provides new and promising technology routes to manipulate the silicene structure by controlled phase selection and single-crystal silicene growth on a wafer-scale, and enables us to develop an encapsulation scheme for the silicene preservation when its native Ag substrate is stripped off so as to create the condition for a full exploitation of silicene in durable operational devices like transistors and piezoristors [4].<br/>[1] D. S. Dhungana et al., Adv. Funct. Mater. (2021) 31, 2102797.<br/>[2] S. Achilli et al., Nanoscale (2023) 15, 11005.<br/>[3] D. S. Dhungana, et al., Nanoscale Horiz. (2023), doi: 10.1039/D3NH00309D.<br/>[4] L. Tao, et al., Nature Nanotech. (2015) 10, 227; C. Martella et al., Adv. Mater. (2023), doi: 10.1002/adma.202211419.