Large-Scale Integrated Vector-Matrix Multiplication Processor Based on Monolayer MoS₂

In recent years, data-driven algorithms took the spotlight promising new and efficient ways for processing and extracting meaningful information from ever-growing amounts of generated data. Although the von-Neuman architecture was the backbone of the data revolution, the separation of the memory and processing units makes the current processors spend a significant amount of energy moving data compared to the energy spent in computing [1]. This motivated the research in emerging computer architectures which could provide energy benefits while performing data-driven algorithms, such as artificial neural networks or signal and image processing. Among the different proposals, in-memory computing has been systematically shown to be beneficial for the previously mentioned applications [2]. Despite the intense research efforts put into the types of memory devices used in this architecture, no technology has been able to satisfy all the requirements [3]. The lack of a universal memory platform for performing computation has led to the investigation using two-dimensional materials as a promising material system for this emerging architecture [4]. In this light, here, we fabricated a 32x32 vector-matrix multiplier with 1024 floating-gate field-effect transistors (FGFET) that use atomically thin MoS₂as the semiconducting channel material. This large-scale integration device is developed in a wafer-scale fabrication process, achieving high yield and low device-to-device variation. Due to the low device variability, an open-loop programming scheme can be employed while obtaining multi-level memory behavior. Finally, our in-memory processor is used to demonstrate discrete signal processing based on vector-matrix multiplications. Our findings lay the foundations for creating complex in-memory processors that can harvest all the advantages of 2D materials.<br/> <br/>[1] G. Kestor, R. Gioiosa, D. J. Kerbyson, and A. Hoisie, “Quantifying the energy cost of data movement in scientific applications,” in 2013 IEEE International Symposium on Workload Characterization (IISWC), Sep. 2013, pp. 56–65. doi: 10.1109/IISWC.2013.6704670.<br/>[2] S. Yu, “Neuro-inspired computing with emerging nonvolatile memorys,” Proceedings of the IEEE, vol. 106, no. 2, pp. 260–285, Feb. 2018, doi: 10.1109/JPROC.2018.2790840.<br/>[3] H.-S. P. Wong and S. Salahuddin, “Memory leads the way to better computing,” Nature Nanotech, vol. 10, no. 3, Art. no. 3, Mar. 2015, doi: 10.1038/nnano.2015.29.<br/>[4] G. Migliato Marega et al., “Low-Power Artificial Neural Network Perceptron Based on Monolayer MoS2,” ACS Nano, vol. 16, no. 3, pp. 3684–3694, Mar. 2022, doi: 10.1021/acsnano.1c07065.