Nabil Labchir1,Saber Hammami2,Kilian Baril3,Maya Wehbe3,Sébastien Labau1,Camille Petit-Etienne1,Blandine Alloing3,Matthew Charles2,Jesus Zuniga Perez3,Cécile Gourgon1
LTM/CEA1,CEA Leti2,CRHEA_CNRS3
Nabil Labchir1,Saber Hammami2,Kilian Baril3,Maya Wehbe3,Sébastien Labau1,Camille Petit-Etienne1,Blandine Alloing3,Matthew Charles2,Jesus Zuniga Perez3,Cécile Gourgon1
LTM/CEA1,CEA Leti2,CRHEA_CNRS3
At present, GaN-based µLED optoelectronic devices are progressing beyond solid-state lighting, inspiring a fascinating new category of applications. Indeed, the µdisplay sector has reached a highly dynamic expansion phase. Unlike conventional displays, µdisplays require image magnification to be seen by the human eye. However, they must be able to display an image of similar quality to that of standard in terms of definition, i.e. number of pixels. To display as many pixels on a smaller surface, we need to reduce the pixel pitch, i.e. the distance between two pixels, from a few hundred micrometers to only a few micrometers. At present, controlling the internal crystal quality of the GaN substrate permits the development of smaller, more efficient µLEDs. However, the µLED lifetime is highly dependent on the density of dislocations inside GaN which behave as non-emissive zones on the µLED surface. In this context, nanoimprint lithography (NIL) will be deployed to nanotexture silicon-on-insulator (SOI) substrates in order to achieve a high density of GaN growth sites. The regrowth on these SiO<sub>2</sub>-based sites enhances the GaN quality and therefore the µLEDs performance. The innovation in our strategy is based on the nanopatterning of deposited GaN/AlN layers on 3 cm<sup>2 </sup>SOI surface for fabricating 200 nm nanopillar arrays with zero defect and that possess SiO<sub>2</sub> at the bottom, using both NIL and plasma etching techniques. Here, I have developed a process without lift-off that is compatible with industrial transfer by using metal hard mask etching. In this process, I have controlled pillar arrays with 150 nm in diameter at the bottom, and I have carefully optimized the plasma etching of materials at all the different steps, especially at the NIL and hard mask sections. For transferring our zero-defect protocol to large-scale production, we are working on extending our strategy to fabricate µLEDs on 200-300 mm wafers. This research will provide a breakthrough for the future optoelectronics industry of displays.