Extremely Scaled Hetero-Junction Channel TFT for Advanced Electronics

In this work, we investigate different combinations of Tin-doped Indium Oxide (ITO) and Indium Gallium Zinc Oxide (IGZO) as ultrathin (channel thickness less than 5 nm) channel layer for high performance short channel thin-film transistor (TFTs). The TFTs have been fabricated at low-temperature (<350°C) combining sputter deposition (channel layer) and atomic layer deposition (gate insulator HfO₂), making our fabrication approach compatible with low-thermal budget Cu interconnects for back-end-of-line. Our approach results in significant improvement in TFT performance above our earlier published record results for ~ 30 nm IGZO (channel) and ~ 10 nm HfO₂ (gate insulator). In this study, various ultrathin combinations have been explored, specifically ITO/IGZO heterostructure and superlattice. We have achieved a highest field-effect mobility of ~ 100 cm²V^-1s^-1 for ultra-thin ITO/IGZO channel with thickness of 4 nm. The introduction of a thin-layer ITO significantly suppresses the hysteresis in the device due to compensation of the interfacial/bulk traps. Moreover, the use of ultrathin combination compensates for the expected negative shift in V_th resulting in a V_th ~ 0V. Short channel immunity is observed with significantly low off-state current (<100 fA/µm), low subthreshold swing (SS) of <100 mV/decade and high ON/OFF ratio >10⁸, for 50 nm channel length devices. We also see a significant decrease in SS for the super lattice device. Furthermore, we have also studied ultrathin films of ITO and IGZO in isolation. We have successfully fabricated TFTs with ~ 2 nm ITO films as channel layer with a decent on/off ratio of 10⁶. There is a noticeable degradation in the ON state current as the thickness of IGZO is scaled below 6 nm. For the pure ITO situation, as the thickness is increased, we identify an increase in the ON state current but the Vth become progressively negative with poor SS. However, when we combined them as heterostructure and superlattice, the performance of our ultra-thin hybrid channel layer is comparable to emerging two-dimensional materials and superior to that of existing metal oxides. Moreover, unlike Si, there is no significant degradation in long channel transistor performance as the active layer thickness changes from 33 nm to 4 nm. Our approach combines the high carrier concentration in thin ITO and controlled electron flow through IGZO due to energy barrier formation at interface of these layers, resulting in improved device performance. This unique layered structure offers prospects for future sub 5 nm regime devices for BEOL compatible, advanced CMOS application.