Defect-Enhanced Recovery Processes for Heterogeneous Integration of Ge on Si

Epitaxial growth of germanium on silicon (Ge-on-Si) for heterogeneous integration of photonic devices poses a challenge due to the lattice misfit of Ge and Si, leading to defects such as threading and misfit dislocations. Ge is typically grown on Si via a two-step growth process with an initial low temperature buffer layer to suppress islanding followed by a high temperature layer (&gt;600°C) to obtain higher growth rates and better crystal quality. Additional post-processing at high temperatures via cyclic annealing is a well-established process utilized to reduce threading dislocation density and improve device performance. We have grown Ge on Si and Si-on-Insulator (SOI) substrates at low temperatures via Ultra High Vacuum Chemical Vapor Deposition (UHVCVD) and annealed at temperatures varying between 425°C-800°C to explore point defect and dislocation interactions in this temperature range.<br/>We have conducted Hall effect measurements to demonstrate that as-grown Ge exhibits p-type electrical conductivity with carrier concentration around 1016 cm-3, despite having no intentional dopant in the growth process. Electrical type conductivity conversion from p-type to n-type is observed consistently above 500°C annealing temperature for 500nm thick Ge and 600°C annealing temperature for 1000nm thick Ge. The defect recovery mechanism behind this type conversion exhibits first order rate kinetics with an activation energy of 1.7 eV in the 425°C-500°C annealing range. Transmission Electron Microscopy (TEM) conducted on the annealed samples demonstrates the following characteristic behavior: i) in the 500°C-600°C range, screw dislocation density is reduced, signaling point defect annihilation since temperatures are too low for the high temperature dislocation glide mechanism that results in dislocation density reduction, ii) in the 730°C-800°C range, the well-documented threading dislocation density (TDD) reduction to ~5x106 cm-2 is observed. Due to the low temperature (500°C-600°C) range where we observe screw dislocation reduction, we conclude that point defect-mediated climb is the mechanism behind screw dislocation reduction. Upon annealing, it is likely that supersaturated acceptor-like point defects diffuse and annihilate, relieving the p-type compensation and resulting in n-type conductivity. <br/>We have also conducted X-ray diffraction and found that as-grown Ge and Ge annealed at 600°C exhibit very low strain(0.1%), while Ge annealed at 730°C matches the strain of Ge layers grown at 730°C, 0.17%. Strain builds up in Ge on Si layers during cooling due to the difference in thermal expansion coefficients of Ge and Si. The strain we have observed is lower than the strain modeled from the difference in thermal expansion coefficient alone, consistent with previous observations of calculated vs experimental strain due to relaxation. However, there is no further build up in strain even when Ge is annealed at 600°C which is likely due to low dislocation velocity and thus lack of plastic deformation at this temperature. Previous reports of type conversion upon annealing have been at higher temperatures that attribute type conversion to plastic deformation during relaxation which induces clusters of point defects that result in p-type compensation. <br/>We have explored defect-enhanced recovery processes for heterogeneous integration of Ge on Si. We have observed that electrical conductivity type conversion occurs consistently in Ge layers at lower annealing temperatures than previously reported due to point defect-mediated climb of screw dislocations. Better understanding of defect recovery mechanisms can be utilized to further improve integrated Ge-on-Si photonics device performance.