Deep Learning Techniques for Integrated Circuit Die Performance Prediction

A deep learning ensemble model has been developed combining in-process defect inspection data and process control monitoring data to predict die performance. This model can be used to reduce die level testing and its high associated cost.<br/>Integrated circuit (IC) manufacturing produces a vast amount of data. Here we focus on in-process surface defects and process control monitoring (PCM) data that are usually readily available in good quality. Defects, such as scratches, particles, voids, notches, etc. can indicate device failure provided they are located at certain places, exceeding a particular threshold size. PCM parameters have already proven their applicability for forecasting various parameters, such as yield detractors detection, final test outcome prediction, yield estimation, and prediction. Thus, Machine Learning (ML) techniques, especially Deep Learning (DL) is a logical approach to approximate IC performance at the die level. In case when a large representative dataset is accessible, DL techniques, such as Neural Networks (NN) are known to be robust against the noise and are able to generalize well.<br/>In the present work, we first explored the possibility to use deep learning techniques to predict failed dice based on the defect data from the in-process inspection tools. Additionally, we explored ensemble models based on the defect inspection and PCM data. These ensemble models using data on defects alongside certain patterns in PCM parameters were used for a fine-grained prediction of die performance. The pass/fail wafer sort (WS) labels are represented by wafer bin maps (WBM).<br/>Considering the appearance of the data on defects, where certain imperfections are spread over the die surface and inspected at each level of the IC (eg. gate, contact, metal, etc.), the most generic approach is to use standard Convolutional Neural Networks (CNN) used for image recognition, and using the inspection levels as channels in the CNN. However, given the defect sparsity and size of the dataset, this approach is extremely demanding for computational resources. Thus, the second approach is based on applying convolution through the geometrical parameters of the defects without projecting them on a die map. The latter is more resource-efficient as a defect-free area of the dice is eliminated. This is very valuable, as the datasets can contain dozens of millions of dice.<br/>Interestingly, yield prediction on the data obtained from PCM parameters using neural networks (NN) significantly outperformed state-of-the-art tree-based algorithms (XGBoost, CatBoost, LightGBM) as data coming from the manufacturing processes contain lots of noise unbiased with the label, for various reasons. At the die level, dense neural network-based models show plausible results for binary fail classification, efficiently representing repeating fail patterns across the dataset eg. stepper field defect induced patterns. For the wafer level yield prediction from multiple-site PCM parameters, due to non-localized interrelation between the test sites, the 1D convolutional neural network shows superior performance by applying convolution over the PCM structures.<br/>Additionally, using both types of input data (both PCM and defects) it is possible to predict die performance using ensemble learning where the model can benefit from combining more parameters that lead to more accurate predictions. Applying the models, based on the above-mentioned parameters, yields and die performance, as well as low-yield areas on a wafer, can be predicted with high accuracy. As a result, depending on the technology used for the wafer production the overall cost can be considerably reduced, as testing patterns can be estimated, decreasing the number of physical tests needed.