Assessment of Charge Trap Memory for Synaptic Transistor Through Trap Time Control

Abstract:<br/>Neuromorphic computing systems have been required recently due to the nature of the von Neumann structure, which causes high power consumption and more time to require the process of big data and deep learning tasks [1].<br/>In new hardware architectures, two terminal-based neuromorphic devices with synaptic crossbar arrays have been studied widely but the regarding leakage current, reduction of Snake path has still been challenged [2]. On the other hand, synapse transistors have been attracting attentions in the substitute technology to overcome the leakage current and control the weight of the synapse independently [1].<br/>Here, we conducted to create synapse plasticity with transistors with potentiation and depression, which were consisted of IGZO transistors with Ga2O3 charge trap layer using a solution process and an ALD process. The linearity of synaptic devices plays an important role in evaluating synaptic plasticity.<br/>The magnitude of charge trapping in transistors highly depend on inducing pulse numbers and frequencies of applied voltages. However, detail explorations of the assessment in this factor have not been revealed widely. In order to support the guidance of the assessment, we studied this aspect of trap control and guide how to approach optimal condition of own devices as function of pulse time, input voltage, and initialization.<br/>As a result, we obtained high linearity of synaptic plasticity by several steps inducing different voltages and pulse numbers.<br/>It was also confirmed that the changes in weight were significantly changed according to the difference in roughness of the Ga2O3 surface and the defect-free tunneling layer through the ALD process.<br/>Acknowledgements<br/>This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. 2020R1A2C1013693), Korea Institute for Advancement of Technology (KIAT) grant funded by By the Ministry of Trade, Industry & Energy (MOTIE, Korea) (P0012451, The Competency Development Program for Industry Specialist) and the Technology Innovation Program - (20016102, Development of 1.2kV Gallium oxide power semiconductor devices technology) funded by MOTIE.<br/>References<br/>[1] IGZO/Al2O3 based depressed synaptic transistor”, Yu Liu1, Xiawa Wang1, Wenjie Chen, Linyuan Zhao, Wei Zhang, Weijun Cheng, Ziting Zhuo, Jing Wang, Tian-Ling Ren, Jun Xu, Superlattices and Microstructures 128 (2019)<br/>[2] Neuromorphic computing using non-volatile memory”, Geoffrey W. Burr, Robert M. Shelby, Abu Sebastian, Sangbum Kim, Seyoung Kim, Severin Sidler, Kumar Virwani, Masatoshi Ishii, Pritish Narayanan, Alessandro Fumarola, Lucas L. Sanches, Irem Boybat, Manuel Le Gallo,Kibong Moon, Jiyoo Woo, Hyunsang Hwang & Yusuf Leblebici, Taylor & Francis 2 (2017)