HZO FTJ analog NVM with Synaptic Plasticity for In-Memory Computing

Silicon compatible ferroelectric Hf_0.5Zr_0.5O₂ (HZO) [1] opens new opportunities for single-layer ferroelectric tunnel junction (FTJ)[2] non volatile memories (NVM) integrated with CMOS. Semiconductors are good candidates for the bottom electrode [3] since they allow for partial compentation of the polarization charge, consequently the efficient modulation of the potential barrier necessary for high tunneling electroresistance (TER).<br/>Using Ge [4] and ~ 0.7% Nb-doped SrTiO₃ (NSTO) [3] semiconductor substrates, amorphous HZO is prepared with plasma assisted molecular beam deposition [4] at 120 ⁰C, followed by in-situ deposition of TiN or W top electrodes. Crystallization annealing is performed at 400 ⁰C - 550 ⁰C for 45 -400 sec.<br/>Robust ferroelectricity is obtained after wake-up on capacitors with 5 nm HZO showing coercive voltage V_c below 1V and remanent polarization 10-20 μC/cm². Ferroelectricity persists in HZO as thin as 4 nm albeit with reduced P_r ~ 5 μC/cm². Best FTJ results are obtained for W/HZO/NSTO FTJs showing TER &gt; 4 at a read voltage of 0.4 V. The memory window (current vs programming voltage) is from -0.7 V to +1.3V which makes these devices suitable for low votage/low power applications. Despite the relatively low ON current of ~5μA/cm² and conductance ~ 0.1nS, the devices show more than 32 stable non-volatile intermediate states between conductance extrema corresponding to 5-bit memory cell. Synaptic plasticity in the form of long term potentiation (LTP) and depression (LTD) of the conductance synaptic weights is obtained by applying consecutive pulses of varying amplitude (1 to 1.5V for potentiation, -0.4 to -1.2 V for depression) or varying width (1μs-10ms). The LTP and LTD curves for varying amplitude are nearly symmetric and linear as required for analog in-memory accelerators with good inference accuracy. The ON and OFF states have an endurance of &gt;10⁵ cycles with cycling field of 1.6 V. The ON, OFF and all intermediate states show no retention loss for &gt;10⁴ sec. The low programming voltage and the good retention present advantages compared to the double-layer HZO/AlOx gate stacks [5] more often reported in the literature.<br/>For a deeper understanding of the mechanism giving rise to TER, temperature dependent I-V measurements up to 100 ⁰C are performed. A weak temperature dependence in both ON and OFF state current is observed indicating a thermal activation process with a low activation barrier of the order of 0.1 V. This is an indication of thermal injection over the Schottky barrier formed at the HZO/semiconductor interface which is modulated by the ferroelectric polarization. Appropriate Schottky barrier engineering by changing the Nb doping and the top metal workfunction could enhance the TER and the ON current.<br/>Given the high quality epitaxial STO on Si(100) [6], an STO/NSTO multilayer can be epitaxially grown on Si, then by etching and ALD conformal deposition of HZO/metal, it is possible to define a number of vertically stacked side wall HZO/NSTO FTJs. This can lead to a large and dense 3D cross bar array integrated on Si. Our FTJs operating at low read and write voltage (&lt;1 V) and low output current are ideally suited for the implementation of dense analog in-memory accelerators for ultralow power massively parallel data processing.<br/>We acknowledge financial support from the European Union through the H2020 project BeFerroSynaptic -contract No. 871737.<br/>References<br/>1. J. Müller et al, Appl. Phys. Lett. 99, 112901 (2011)<br/>2. Wen, Z., Wu, Adv. Mater. 32, 1904123 (2020)<br/>3. Xi, Z., Ruan, J., Li, C. et al, Nat. Commun. 8, 15217 (2017)<br/>4. C. Zacharaki, Appl. Phys. Lett. 117, 212905 (2020)<br/>5. B. Max et al, IEEE J. Electron Device Soc. 7, 1175-1181 (2019)<br/>6. McKee R. A. et al, Phys. Rev. Lett. 81 3014 (1998)