Optimized Weight Programming for Analog Memory-Based Deep Neural Networks

Analog memory-based deep neural networks provide energy-efficiency and per-area throughput gains relative to state-of-the-art digital counterparts such as graphics processing units. Recent advances focus largely on hardware-aware algorithmic training and improvements to circuits, architectures, and memory devices. Optimal translation of software-trained weights into analog hardware weights—given the plethora of complex memory non-idealities—represents an equally important task. We report a generalized computational framework that automates the crafting of complex weight programming strategies to minimize accuracy degradations during inference, particularly over time. The framework is agnostic to network structure and generalizes well across recurrent, convolutional, and transformer neural networks. As a highly flexible numerical heuristic, the approach accommodates arbitrary device-level complexity, making it potentially relevant for a variety of analog memories. Interestingly, this computational technique can optimize inference accuracy without the need to run inference simulations or evaluate large training, validation, or test datasets. By quantifying the limit of achievable inference accuracy, it also enables analog memory-based deep neural network accelerators to reach their full inference potential.