Fabrication and Characterization of Four-State Inverter utilizing Quantum Dot Gate Field-Effect Transistors (QDGFETs)

<i>Abstract: This paper presents experimental results of nMOS quantum dot gate field-effect transistor (QDG-FET) based four-state inverter fabricated and tested with Si/SiO₂ and Ge/GeO₂ quantum dots(QD). The site-specific self-assembly of SiOx-cladded Si and GeOx-cladded Ge QD layers in the gate region implements both the driver and load FETs in enhancement nMOS inverters. A four-state inverter will allow reduction of FET count in logic block in microprocessors. </i><br/><i>Keywords: </i>QDGFET, Multi-State, Multi-Bit, Inverters<br/><br/><b>I Introduction:</b> Quantum dot gate (QDG) FETs exhibiting three-state I-V characteristics have been reported using two layers of thin barrier SiOx-cladded Si quantum dots in the gate region [1]. This has been followed by reports of four-state QDG-FETs and enhancement mode inverters using self-assembled Si-Ge quantum dots [2]. This paper presents new results presented in our recent paper [3]<i>.</i> Moore’s<i> law</i> states that the number of transistors doubles every two years [4], and reducing transistor size sub 5nm presents challenges.<br/><b>II QDG-FET comprising of 2 layers of SiOx-Si and 2-laeyrs of GeOx-Ge QDs: </b>A quantum dot (QD) is a semiconductor structure that is confined in all three dimensions. A QD has two main layers, a small semiconductor core such as Si or Ge surrounded by a cladding layer of either SiOx or GeOx respectively. The cladding layer acts as a barrier layer which helps to trap charge inside the quantum dots. When a number of quantum dots are placed next to each other they form a quantum dot superlattice (QDSL). The formation of a QDSL results in mini energy bands which allows the FET device to exhibit multiple states [1]. Three-state inverters using SiOx-Si and GeOx-Ge QDG-FETs have been reported [1, 2]. We are reporting the QDG-FET based inverter employing both SiOx-Si QDs and GeOx-Ge QDs in the gate region that resulted in four-states for the inverter. In this device, we have two layers of cladded Si QD layers over tunnel gate oxide and two additional layers of Ge QDs are self-assembled on Si QDs. Every two layers of QDs provides a new threshold voltage which can be used to program the inverter at different states. The QDs are assembled using a colloidal solution over the gate region via a self-assembly method in which QDs are deposited on the p-Si channel region over the tunnel gate oxide. The Si sample was placed in the colloidal solution for 3 minutes after which an annealing process was preformed, this was done for every two layers of QDs.<br/><b>III Conclusion: </b>Formation of a Si QDSL and Ge QDSL in the gate region results in a four-state inverter. QD-NVRAMs have been experimentally demonstrated with a fast erase/write time [5]. The integration of QDG-FETs with QD-NVRAMs has been envisioned [6]. Finally, Moore’s law is prolonged by using extra states exhibited in QDG-FETs.<br/><br/>1. F. C. Jain et. al. "Device and circuit modeling using novel 3-state quantum dot gate FETs," <i>2007 ISDRS</i>, 2007, pp. 1-2, doi: 10.1109/ISDRS.2007.4422254.<br/>2. M. Lingalugari et al. “Novel multi-state quantum dot gate FETs using SiO2 and lattice-matched ZnS-ZnMgS-ZnS as gate insulators,” Journal of Electronic Materials, 42, pp. 3156-3163, 2013.<br/>3. B. Khan et. al. “Fabrication and Characterization of nMOS Inverters Utilizing Quantum Dot Gate Field Effect Transistor (QDGFET) for SRAM Device” IJHSES, 31, no. 01n04, Mar. 2022<br/>4. C. A. Mack, "Fifty Years of Moore's Law," <i>IEEE TSM</i>, 24, pp. 202-207, May 2011.<br/>5. M. Lingalugari et. al. “Quantum Dot Floating Gate Nonvolatile Random Access Memory Using Quantum Dot Channel for Faster Erasing”, Electronic Lett., 54, 36, 2018.<br/>6.F. Jain et. al. Integrating QD-NVRAMs and QDC-SWS FET based logic for multi-bit computing, IJHSES, 31, pp.2240020-1, 2022.