Low Temperature Fabrication of 3D Integrated CMOS Devices by Via-Hole-Less Structure on Flexible Substrate

Complementary metal oxide semiconductor (CMOS) inverter is basic building blocks for complex integrated logic circuits, which require both p- and n-type thin film transistors (TFTs). Si-based CMOS shows good performance across n- and p- type transistors, however, Si require high temperature process that is not suitable for next generation flexible devices. Organic, Oxides, and metal chalcogenides are proposed for the high performance p-type TFTs, however, their fabrication process, physical nature, and electrical properties are not suitable for cutting-edge CMOS inverter. There are some reports that compose an inverter with only n-type TFTs, however, they suffer from low output swing, small input capacitance, large power dissipation and poor noise margin. To realize high performance CMOS inverter logic circuit, high performance p-type semiconductor with simple fabrication process is strongly required.<br/>3-dimensional (3D) integration is an emerging technology that can offer minimized system, short interconnection, reducing packaging cost and integrate various devices. As Moore's Law reaches its limits, 3D integration technology becomes increasingly important. There are several 3D integration methods such as wire bonding and 3D through silicon via (TSV). Wire bonding is cheap and mature process, however, the process is only possible around die, low chip connection freedom, require interlayer, and suffer from RC delay. 3D-TSV shows the reduced footprint, improved Si efficiency, reduced RC delay and lower power consumption. However, 3D-TSV strongly limited to Si semiconductor and restricted on the use of other semiconductors. 3D via-hole-less is a novel multilevel integration system that is etchant-free, allows simultaneous metal interconnection, minimizes underlying device degradation and provides high substrate-compatibility.<br/>In this work, we present the 3D integration of n-type ZnON and p-type Te TFTs through 3D via-hole less structure. ZnON is well known n-type materials which shows high field effect mobility. Tellurium (Te) is promise 2D p-type materials which can be fabricated via solution process or evaporation process with very low substrate temperature. Here, Te is deposited by room temperature sputtering system which is cost-effective and allow large area uniformity. To demonstrate the 3D via-hole-less structure, ZnON based n-type TFT and Te based p-type TFT were fabricated on the bottom floor and top floor, respectively. Alumina (Al₂O₃) was deposited by plasma enhanced atomic layer deposition (PEALD) using precursor of TMA and reactant of O₂ for the interlayer dielectric (ILD) and dielectric layer. Overall process temperature is under 200 ^oC which is suitable for cheap flexible substrate. By using proposed etchant-free 3D via-hole-less structure, 3D stacked inverter was successfully fabricated, showing the high gain of ~ 20. Finally, flexible 3D via-hole-less CMOS inverter was fabricated on PI substrate.