3D-Stacked Organic Ternary Logic Circuits Utilize Nonvolatile Floating-Gate Memory

Nowadays, a large amount of information is generated in advanced electronic systems such as artificial intelligence (AI) and internet-of-things (IoT). Therefore, the method of increasing information processing density without increasing additional transistor have great attention. Multi-valued logic (MVL) circuits based on heterojunction transistor (HTR) are one solution. However, it is hard to satisfy all the important characteristics of T-inverters including 1) full-swing operation (in the sufficient input voltage (V_IN) range), 2) a well-defined intermediate logic state with the proper output voltage (V_OUT~ half of the supply voltage (V_DD/2), logic "1") and 3) hysteresis-free, low-voltage operation.<br/> Herein, Organic ternary logic inverter (T-inverter) with, a nonvolatile floating-gate (FG) flash memory is demonstrated. The T-inverter operation was controlled by the channel conductance control of the flash memory systematically. We adopt initiated chemical vapor deposition(iCVD) process, to fabricate vertically stacked 3-dimensional (3D) T-inverter. The vertical stacked structure allows increase the density per area. In the flash memory, ultrathin polymer dielectrics were utilized to obtain low-voltage operation. All process was done by in-situ patterning through shadow mask to achieve via-hole-less metal interconnection. Also, to electrically isolate the 1^st layer flash memory and 2^nd layer HTR, a 1 μm-thick interlayer dielectric (ILD) was deposited between the unit devices. For the polymer dielectric layers, poly(2-cyanoethyl acrylate-co-diethylene glycol divinyl ether) [p(CEA-co-DEGDVE)] (named pC1D1) was used as blocking dielectric layer (BDL) in this study. The pC1D1 has high dielectric constant, (k &gt; 6) and superb insulating performance (breakdown field, E_break &gt; 3 MV/cm). Poly(1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane) (pV3D3) was also employed as a tunneling dielectric layer (TDL) in the flash memory and also used as gate dielectric layer (GDL) in the HTR. The pV3D3 has low dielectric constant (k &lt; 2.3) and provides a non-polar interface for the facilitated charge transport in the organic semiconductors. The programming/erasing voltage (V_prg/V_ers) was successfully reduced and the operating voltage was less than 5 V, which is low voltage compared to previous organic 3D logic circuits. Fabricated 3D T-inverter showed full-swing operation, ideal intermediate logic value (~V_DD/2), high DC gain exceeding 20 V/V as well as low-voltage operation (&lt;5 V). Moreover, 3D T-inverter showed excellent long-term stability (change of output voltage less than 3% after 10⁴s). We believe the 3D T-inverter with flash memory developed in this study is expected to be one of the new platforms that can utilize in high-performance MVL circuits.