Paper Transistors for Logic and Analogic Applications

The aim of this presentation is to report the physics and electronics behaviour of a dual gate paper transistor where paper is simultaneously the substrate and the dielectric, while a metal-oxide-semiconductor (IGZO) is used as the active channel, and a back floating electrode is used, able to present logic functionalities simply by varying the amplitude and frequency of the input gate signals. These transistors operate at drain voltages of 1 V with low power, exhibiting I_ON/I_OFF &gt; 10⁴ and mobility ≈ 2 cm²V^-1s^-1, serving the specifications for a broad range of smart disposable low-power electronics. To sustain all this, an analytical compact model was developed able to precisely reproduce the response of paper-based dual-gate FETs and provide a full understanding of their unique and innovative operational characteristics.<br/> <br/><b>References</b><br/>Rodrigo Martins, Diana Gaspar, Manuel J. Mendes, Luis Pereira, Jorge Martins, Pydi Bahubalindruni, Pedro Barquinha, Elvira Fortunato, Papertronics: Multigate paper transistor for multifunction applications, Applied Materials Today 12, (2018) pp. 402–414.<br/>D. Gaspar, J. Martins, P. Bahubalindruni, L. Pereira, E. Fortunato, R. Martins, Planar Dual-Gate Paper/Oxide Field Effect Transistors as Universal Logic Gates, Advanced Electronics Materials, Vol. 4 (12),(2018), 1800423. DOI: 10.1002/aelm.201800423