Symposium Organizers
Paul A. Kohl Georgia Institute of Technology
Paul S. Ho University of Texas-Austin
Patrick Thompson Texas Instruments, Inc.
Rolf Aschenbrenner Fraunhofer IZM
F1: Mechanics and Chip-Package Interaction
Session Chairs
Wednesday PM, April 15, 2009
Room 2002 (Moscone West)
9:30 AM - **F1.1
Mechanical Scaling Trends and Methods to Improve Reliability of Packaged Interconnect Structures.
Michael Lane 1
1 Department of Chemistry, Emory & Henry College, Emory, Virginia, United States
Show AbstractInterfacial fracture of brittle dielectric films is a serious concern for the microelectronics industry. The industry continues to reduce the dielectric constant of films in order to improve/maintain interconnect performance. However, these lower dielectric constant materials typically have reduced mechanical properties. In addition, the dielectric films are often composed of a Si-O-Si backbone which is prone to environmental attack from ambient moisture which further reduces the strength of the interface. Processes such as mechanical dicing of a die from a wafer are particularly deleterious due to the use of water as a cooling agent for the wafering blade. During this process small flaws may be generated which later grow after the die is packaged. A central feature of the growth of these flaws is that the energy supplied by the package to the interface to drive the delamination depends on the delamination length. The central feature that typically provides reliability for interconnect structures is a monolithic structure of copper which completely surrounds the active die. This copper structure must not only stop delaminations but also must stay significantly intact to provide a hermetic seal for the active die. The strength of the crackstop structure is expected to decrease with each generation due to scaling of line and via structures to smaller dimensions. This work will discuss how these scaling trends impact overall die seal strength. In addition, this work will discuss the potential to reduce or eliminate the flaw created during dicing and the utility this has in greatly reducing the overall driving energy supplied for delamination. Accordingly, we discuss two possibilities for improving CPI performance. The first is optimization of crackstop structures and the second is a novel method of interfacial repair for Si-O-Si interfaces based on the use of molecular coupling agents. Finally, the presentation will include a discussion of the potential reliability implications for the microelectronics industry.
10:00 AM - **F1.2
Cracking and Delamination in Interconnect Structures
Thomas Shaw 1 , X. Liu 1 , E. Liniger 1 , S. Hosadurga 2 , D. Goldfarb 1 , M. Lane 3 , G. Bonilla 1
1 IBM Research, IBM, Yorktown Heights, New York, United States, 2 IBM in Albany Nano Technology Research Center, IBM, Albany, New York, United States, 3 Department of Chemistry, Emory and Henry College, Emory, Virginia, United States
Show AbstractThe trend towards the use low K dielectrics for interconnect structures has resulted in an increased susceptibility of these structures to delamination and cracking during processing and packaging of chips. Stresses that are generated by thermal expansion differences between the different materials used to fabricate the chip and the package can result in crack driving forces that are significantly enhanced relative to those driven by intrinsic film stresses alone. This makes the susceptibility of interconnect structures to cracking strongly dependent on their configuration. In the talk we will show how different features of interconnect and packaging structures change their susceptibility to cracking. At the interconnect level, spacing and alignment of metal features strongly influence the driving forces for channel and tunneling cracks to form. In particular we have found the coupling of the thermal expansion stresses from interconnects with the intrinsic stresses in the dielectric layers can result in stresses that are large enough to spontaneously initiate cracks. In contrast to previous studies of channel cracking, in which cracking was found to be enhanced at intermediate spacings between lines, we have found that this kind of cracking is favored in the narrow gaps between metal plates. In addition to vertical cracks, low K interconnect structures are susceptible to horizontal delaminations that are driven by packaging induced stresses at the edge of the chip. Again, the structure of the package as well as the configuration of the interconnects at the edge of the chip plays an important role in limiting the susceptibility of chips to these kinds of failure. We have found that the driving force for these horizontal delaminations is strongly dependent on the extent to which the crack is constrained at the edge of the chip by packaging materials such as the underfill. We will discuss strategies to limit delamination by enhancing interfacial adhesion and through the use of crackstop structures. Finally we will show, using a simple model system, how delamination mechanisms can interact with channel cracking to produce complex cracking patterns when both cracking mechanisms occur simultaneously. Acknowledgement: This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.
10:30 AM - F1.3
Probing the Mechanics of Complex Multilayer Structures for Emerging Technologies.
Alexander Hsing 1 , Reinhold Dauskardt 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States
Show AbstractAdvanced semiconductor technology nodes require the integration of heterogeneous multilayer thin-film microstructures with vastly different mechanical properties. Mechanical probing at the micron scale is a relatively unexplored area of characterization between the nanoscale (e.g. AFM and nanoindentation) where loading capabilities are too low and compliant, and conventional mechanical testing where the load capabilities are significantly too high. We use a novel micron-scale test metrology to accurately measure a number of key mechanical properties of multilayer thin-film microstructures, including stack stiffness, strength characteristics, delamination behavior, and fatigue resistance. We identify the interface where delamination is initiated in a complex multilayer thin-film structure under tensile loading and discuss how this relates to delamination of layers underlying Cu or solder bumps in modern integrated circuits. Damage evolution is characterized and the mode of failure is determined and SEM microscopy is used to image the region where failure has occurred. Precise positioning of the microprobe allows for the mapping of material properties, such as strength and stiffness, over a large area. The ability of the metrology system to resolve stiffness and strength differences across a given die and between different dies is shown. Simple models are used to demonstrate that measured stiffness values correspond well with theory. Models for delamination of underlying layers are also discussed.
11:15 AM - **F1.4
Impact of Chip-Package Interactions on Mechanical Reliability of Advanced Interconnects.
Rui Huang 1 , Xuefeng Zhang 2 , Suk Kyu Ryu 1 , Se Hyuk Im 1 , Paul Ho 2
1 Department of Aerospace Engineering and Engineering Mechanics, University of Texas at Austin, Austin, Texas, United States, 2 Laboratory of Interconnect and Packaging, University of Texas at Austin, Austin, Texas, United States
Show AbstractChip-Packaging Interaction (CPI) and implementation of low-k dielectrics are important factors affecting mechanical reliability of Cu/low-k interconnects. Packaging and assembly of a flip-chip package can induce large mechanical stress and deformation in the interconnects, significantly increasing the crack driving force to cause delamination failure. Moreover, most low-k materials have low elastic modulus, high CTE, weak adhesion to adjacent materials, thus further promoting interfacial delamination in the Cu/low-k structures. In this paper, we address several basic questions concerning CPI and its impact on interfacial cracking for multilevel Cu/low-k interconnect structures. A three-dimensional (3D) sub-modeling technique was adopted to analyze packaging induced deformation and stresses in a 4-level Cu/low-k interconnect structure. Four consecutive submodels were constructed to scale the global model at the package level down to the level of interconnects. In the interconnect structure, the pitch and line dimensions in the first two metal layers (M1 and M2) are doubled in the third layer (M3), which are doubled again in the fourth layer (M4), simulating the hierarchical layers in real interconnect structures. Cracks are introduced at interfaces of interest, and a virtual crack closure method was used to calculate the energy release rate and the mode mix, as quantitative evaluation of the driving force for interfacial delamination.Specifically, we examine the CPI effect on reliability with implementation of ultra low k dielectrics and the role of crackstop structures. Using different stacking of low k and ultra low k dielectric layers, we found that the ultra low k interface at the upmost level is the most critical and the multilevel stacking structure has to be optimized in order to minimize the CPI effect on ULK interconnect reliability. The effect of mechanical properties of the low k dielectrics is elucidated. To prevent cracks initiated at the edge of a chip from propagating into the functional area of the chip under thermomechanical loadings during packaging processes and service, patterned metal structures may be incorporated around the perimeter of a chip as the crackstop structure. The design of effective crackstop structures however requires understanding of crack propagation in the multilevel interconnects under the influence of chip-package interactions. We propose a general criterion for crack path selection and show that cracks often propagate from upper levels to lower levels, eventually causing failure by die cracking.
11:45 AM - F1.5
Improved All-Copper Flip-Chip Connections: Moving Towards Manufacturability.
Tyler Osborn 1 , C. Hunter Lightsey 1 , Paul Kohl 1
1 School of Chemical and Biomolecular Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractCurrent industry standard flip-chip interconnects employ the use of solder balls to make electrical connection between the chip and substrate. Solder has many weaknesses for this application that are becoming more important as the required interconnect size continues to shrink. Solder has limitations in many areas including the formation of brittle intermetallics and poor electromigration resistance. A novel method has been developed to replace solder for making flip-chip interconnects with all copper connections. To eliminate the concerns of using solder materials, we have developed a process to create chip-to-substrate connections that are made entirely of copper using electroless copper plating followed by low temperature annealing. However, for the all-copper process to gain acceptance with industry all aspects of the process must be made competitive with solder in every way. This includes practical requirements such as processing time and throughput. In addition, fragile low-k dielectric layers on the die must not be damaged by the elastically stiff copper connections. Therefore, the goals of this work are to address the issues posed and improve the manufacturability of the all-copper process.Limitations in the process exist due to the simple electroless process that was used. Electroless plating from a standard Shipley Circuposit 3350 bath uses formaldehyde as the reducing agent and EDTA to complex the Cu2+ in the hydroxide solution. Without any additional chemistry the resulting plated and bonded copper pillars are less than optimized in terms of voids in the bonded region and plating rate and plating quality. The final structure prior to the low temperature annealing step has a distinct microscale interface between the two electrolessly deposited copper regions. However, upon annealing at 180C the interface is entirely removed and a continuous copper connection is created. In addition to seeking improvements in the quality of the plate, reducing the time that the deposition process requires is key. Therefore, additive based electroless deposition using polyethyleneglycol (PEG) has been demonstrated to reduce the time this process takes.Also, in this work a model was developed to investigate methods to reduce the stress exerted on the low-k on-chip network due to the all-copper pillar interconnects. The benefits of different mechanical properties for the polymer collar material and alternative geometry for the copper pillars are considered. Finally, experimental confirmation of the benefits of the polymer collar in reducing stress is performed via shear testing.The authors would like to acknowledge the support of SRC under task 1341.001.
12:00 PM - F1.6
High Aspect Ratio, Aqueous-Develop, Photosensitive Polynorbornene Dielectric for Packaging and Interconnect Applications.
Venmathy Rajarathinam 1 , C. Hunter Lightsey 1 , Tyler Osborn 1 , Brian Knapp 2 , Edmund Elce 2 , Sue Ann Bidstrup Allen 1 , Paul Kohl 1
1 Chemical Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States, 2 , Promerus LLC, Brecksville, Ohio, United States
Show AbstractPolymers are widely used in the microelectronics industry as thin-film, dielectric layers with copper in substrates and packages, and as passivation layers on semiconductor devices. Epoxy based polymers are particularly useful in electronic packaging because they have excellent adhesion and react at modest temperatures. A challenging application space exists for photosensitive, thick-film, high aspect ratio materials in microelectronic and MEMS applications. In this work, the characterization of Avatrel 8000P, a new high aspect ratio (> 7:1) aqueous base develop, photosensitive polymer has been performed. High aspect ratio features were produced in thick films with straight side-wall profiles and high fidelity. The mechanical, electrical, optical, and chemical characteristics were evaluated for microelectronics applications. Epoxy crosslinking reactions were studied as a function of processing condition by use of Fourier transform infrared spectroscopy, nanoindentation, and dielectric measurements. The impact of curing condition and exposure dose on the mechanical, thermal, and electrical properties of Avatrel 8000P have also been evaluated. The relationship between processing conditions and material properties were examined to optimize the process conditions in order to obtain a high quality Avatrel 8000P film. Additionally, the impact of the different polymer structures of Avatrel 2000P, SU-8, and Avatrel 8000P on material properties and performance have been studied. The simple baking procedures make Avatrel 8000P easy to process, and the ability to develop it in aqueous base can reduce reduce cost and chemical waste. In addition to its excellent photo-definition properties, its high mechanical strength and excellent thermal stability make it suitable for MEMS and microelectronics packaging.
12:15 PM - F1.7
A Novel X-ray Diffraction-based Technique for Complete Stress State Mapping of Packaged Silicon Dies
Balaji Raghothamachar 1 , Vishwanath Sarkar 1 , Vladimir Noveski 2 , Michael Dudley 1 , Sujit Sharan 2
1 Materials Science & Engineering, Stony Brook University, Stony Brook, New York, United States, 2 , Intel Corporation, Chandler, Arizona, United States
Show AbstractNon-destructive measurement of package-induced stresses in traditional wire bonded and currently favored flip chip packages is critical to address performance, reliability and lifetime problems. Current stress measurement techniques such as the use of strain gages especially piezoelectric stress sensors, micro-Raman spectroscopy, scanning acoustic microscopy, photoelastic techniques, etc. suffer from one or more limitations related to their destructive nature, sensitivity, number of stress components measured and applicability to actual operating conditions. Recently, we have developed a method to measure the complete strain state (and thereby the stress state) of a single crystal by tracing the relative change in direction of an x-ray beam diffracted from a stressed crystal. This is based on the relationship between the stress state in a crystal and the local lattice plane orientation. Experimentally, this can be achieved by using a large area synchrotron white beam in conjunction with a precision grid of x-ray absorbing material placed in the path of the beam. The grid breaks the x-ray beam into an array of microbeams that are diffracted by the single crystal sample to produce an integrated x-ray topograph on which the inverse grid image is distorted due to changes in the paths of diffracted microbeams i.e. an x-ray reticulograph is created. The distortions are a result of the variations in the diffracting lattice plane orientation produced by strain present in the crystal. By measuring this distortion on multiple topographs and applying the ray tracing principle, the entire strain state can be calculated and mapped for the entire sample. This technique can be carried out both in the transmission geometry where the measured stress is averaged over the thickness of the crystal and in the reflection geometry where stresses can be measured up to the penetration depth of x-rays. We have carried out stress mapping of a wirebonded package by applying this non-destructive and non-invasive technique. Results will be discussed in terms of the advantages and limitations of this technique.
12:30 PM - F1.8
Viscoelastic Modeling and Reliability Assessment of Microelectronics Packages.
Aditya Karmarkar 1 , Charlie Zhai 2 , Xiaopeng Xu 3 , Xiao Lin 3 , Greg Rollins 3 , Victor Moroz 3
1 TCAD, Synopsys (India) Private Limited, Hyderabad, Andhra Pradesh, India, 2 Silicon Operations, Nvidia, Santa Clara, California, United States, 3 TCAD, Synopsys, Inc., Mountain View, California, United States
Show AbstractPerformance requirements for advanced systems result in higher integration densities and larger chip sizes. Three-dimensional integration methodologies are also used to integrate heterogeneous circuit blocks. These trends towards greater integration pose significant challenges for package reliability analysis. Advanced microelectronics packages consist of various materials with widely varying thermal and mechanical properties. Some packaging materials exhibit temperature dependent viscoelastic behavior in certain temperature ranges. During fabrication, packages are exposed to numerous thermal cycles that introduce thermo-mechanical stresses in packaging structures. Material viscoelastic behaviors lead to stress relaxation in viscous materials at elevated temperature and result in mechanical loading redistribution in the package structure. Moreover, material resistance to failure decreases with temperature. Large stresses and reduced material strengths at material interfaces can cause crack nucleation, propagation, and package delamination. Conventional linear elastic models are not sufficient to accurately predict the mechanical stresses and reliability in packages employing viscoelastic materials. In this paper, numerical simulations are performed to assess the impact of material viscoelastic behaviors on the package reliability using an advanced simulator. The simulator uses advanced algorithms to generate 3D structures and meshes and to solve the partial differential equations. The simulator employs viscoelastic material models to assess the effects of viscoelastic behavior under various thermal loading conditions. The cohesive zone model and the J-integral method are used to analyze the crack behavior. The impact of material viscoelastic behavior on crack formation and propagation is also examined. The simulation results are used to understand stress evolution and redistribution in packaging structures and to develop strategies to improve package reliability and yield.
Symposium Organizers
Paul A. Kohl Georgia Institute of Technology
Paul S. Ho University of Texas-Austin
Patrick Thompson Texas Instruments, Inc.
Rolf Aschenbrenner Fraunhofer IZM
F6/D8: Joint Session: Interconnect and Packaging
Session Chairs
Friday AM, April 17, 2009
Room 2003 (Moscone West)
9:30 AM - **F6.1/D8.1
Reconfigurable 3-D Integration and Super Chip.
Mitsumasa Koyanagi 1
1 Department of Bioengineering and Robotics, Tohoku University, Sendai Japan
Show AbstractThree-dimensional (3-D) integration is the most promising technology to achieve a future advanced LSI since we can easily reduce the wiring length, the chip size and the pin capacitance by employing 3-D LSIs and consequently we can increase the signal processing speed and decrease the power consumption. We have developed 3-D integration technology based on wafer-on-wafer bonding method and fabricated several 3-D LSI prototype chips such as 3-D image sensor chip, 3-D shared memory, 3-D artificial retina chip and 3-D microprocessor chip. In the wafer-to-wafer 3-D integration technology, however, the overall chip yield exponentially decreases with an increase in the number of stacked layers. Furthermore, we cannot stack chips with deferent size and different thickness in the wafer-to-wafer 3-D integration technology. We have proposed a new 3-D integration technology based on reconfigured wafer-on-wafer bonding technique to solve these problems in the wafer-to-wafer 3-D integration technology. 3-D LSIs are fabricated by bonding the reconfigured wafers onto the supporting Si wafer. The reconfigured wafer consists of many known good dies (KGDs) which are arrayed and glued on a holding Si wafer with Si steps by chip self-assembly technique. Therefore, the yield of the reconfigured wafer can be 100%. As a result, we can obtain a high production yield even after bonding many wafers. It is not necessary in the reconfigured wafer that the chip size has to be identical within the wafer. Therefore, we can stack various kinds of chips with different chip sizes, different materials and different devices in our new 3-D integration technology based on the reconfigured wafer-on-wafer bonding technique. We call this technology a reconfigurable 3-D integration technology. A batch self-assembly process using a multi-chip self-assembly machine is the key in our reconfigurable 3-D integration technology. We have developed a multi-chip self-assembly machine. A multi-chip picking-up holder can simultaneously pick up and transfer more than 500 chips in this machine. First, small volumes of aqueous liquid are coated on hydrophilic bonding areas formed on an 8-inch wafer and then a larger number of KGDs are roughly pre-aligned onto hydrophilic bonding areas on the 8-inch wafer. After that, the KGDs are released onto the bonding areas, and consequently, the many KGDs are quickly and precisely self-assembled onto the bonding areas by surface tension of the liquid. After evaporating the liquid at room temperature under ordinary pressure, these chips are directly and tightly bonded on the hydrophilic areas because these KGDs have hydrophilic SiO2 layer on their backside. We are aiming to realize a super chip using the reconfigurable 3-D integration technology with such self-assembly process. Various kinds of chips with different sizes such as MEMS chip, sensor chip, CMOS RF-IC, MMIC, power IC, control IC, analog LSI, and logic LSI are vertically stacked in a super chip.
10:00 AM - F6.2/D8.2
Low Temperature Direct Cu-Cu Immersion Bonding for 3D Integration.
Rahul Agarwal 1 , Wouter Ruythooren 1 , Ingrid DeWolf 1
1 Process Technology, IMEC, Leuven Belgium
Show AbstractDie-to-die stacking is a key enabler in 3-D integration with high density and high speed interconnections. At IMEC direct metal-to-metal bonding for die stacking is being investigated as an alternative to solder bonding due to its advantages, such as low processing cost due to fewer processing steps and predictable reliability because of single metal joints. Unlike solder bonding, in direct metal-to-metal bonding there is no solder reflow which makes this technology very useful for tighter pitch bump formation. The purpose of this paper is to demonstrate immersion thermo-compression bonding for direct (as plated) Cu-Cu interconnects. High yield and high strength direct Cu-Cu thermo-compression bonds are obtained at temperatures as low as 175°C and results from high density micro-bumps will be presented. Cu-Cu thermo-compression bonding requires higher temperature and pressure to make electrical connections as compared to solder bonding (for eg. Cu-Sn). Bonding temperature and pressure can be reduced by conditioning the plated Cu bumps. Since there is no reflow of metal the surface roughness plays an important role and hence most of the low temperature Cu-Cu bonding results presented in literature have relied on surface planarization steps like CMP or diamond bit cutting to obtain a surface roughness of a few nanometers and/or on surface activation in plasma and bonding at ultra high vacuum [1-4]. In the immersion bonding method presented here, citric acid is present between the samples being bonded providing in-situ cleaning of the Cu surface during the bonding. As plated Cu bumps with average roughness of more than 200nm are successfully bonded at temperatures as low as 175°C. Bonding is performed on two different test devices. First test device with 40µm pitch peripheral array (480 interconnections distributed over 2 daisy chains) have 100% yielding devices at temperatures as low as 175°C and 10g/bump load. The second test device with 100µm pitch area array (2018 interconnections distributed over 9 daisy chains) give a bump chain yield ranging from 87% to 100% depending on the bonding process conditions. For reference, samples which are bonded without citric acid clean prior to bonding did not show any cohesion while samples which are bonded after citric acid clean (but no in-situ cleaning) give only 44% electrically yielding daisy chains. Hence the results indicate an important strong beneficial impact of the immersion bonding method.Reference:1.Gueguen P., et al., “Copper direct bonding for 3D integration,” IEEE IITC, 2008.2.Ruythooren W., et al., “Cu-Cu bonding alternative to solder based micro-bumping,” IEEE ECTC, 2007. 3.Arai K., et al., “A new planarization technique by high precision diamond cutting for packaging,” IEEE ISSM, 2004.4.Kim T. H., et al., “Low temperature Direct Cu-Cu bonding with low energy Ion activation method,” IEEE EMAP, 2001.
10:15 AM - F6.3/D8.3
Thermo-Mechanical Reliability of 3-D Interconnect with Through-Si-Vias.
Xuefeng Zhang 1 , Kuan-Hsun Lu 1 , Suk-Kyu Ryu 2 , Jay Im 1 , Rui Huang 2 , Paul Ho 1
1 Microelectronics Research Center, UT Austin, Austin, Texas, United States, 2 Aerospace Engineering and Engineering Mechanics, UT Austin, Austin, Texas, United States
Show AbstractThree-dimensional integrated circuits with through silicon vias (TSVs) offer a solution to improve the device density and electical performance without scaling. However, process-induced thermal stresses around TSVs in 3-D interconnect structures raise serious reliability issues such as Si cracking and performance degradation of devices. Thermo-mechanical reliability was investigated using finite element analysis (FEA) combined with bending beam experiments. First a 3D TSV interconnect model was developed and verified using experimental results from bending beam measurements. After verification, the process-induced stresses in the 3D interconnect were calculated by FEA. The pitch-to-diameter ratio of the TSV and the die thickness were identified as important parameters in controlling the thermal stress distribution inside and near the TSVs. The surface stress in the Si was found to decrease as a function of distance from the fully filled Cu TSV but increase with the TSV diameter. Reducing the TSV pitch caused the stress fields from the adjacent vias to interact, which can lead to significant stress enhancement with a reduction of the pitch-to-diameter ratio less than 2.5. The effect of Si die thickness was also studied. The radial stress at the Si surface can increase by as much as 50% with the die thickness reducing from 200um to 20um. This indicates that die thickness can significantly influence the size of the keep-away zone for devices. Additional simulation results demonstrated that significant stress reduction can be achieved by optimizing the TSV interconnect structure, such as using partial Cu filling and adding a thin polymer buffer layer between Cu TSV and Si. Finally, silicon cracking induced by thermal stress interaction between TSVs was investigated. The critical cracking stress of silicon was found to depend on the maximum thermal load and the pitch to via diameter ratio. The crack driving force in silicon between TSVs was found to increase significantly with decreasing pitch-to-diameter ratio and will have to be considered in the design of the TSV structure.
10:30 AM - F6.4/D8.4
Failure Analysis and Process Improvement for Through Silicon Via Interconnects.
Bivragh Majeed 1 , Marc Van Cauwenberghe 2 , Deniz Tezcan 1 , Philippe Soussan 1
1 IPSI, IMEC, Leuven Belgium, 2 AMPS, IMEC, Leuven Belgium
Show AbstractThis paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV’s for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.
10:45 AM - F6.5/D8.5
Effects of Thinned Multi-stacked Wafer Thickness on Stress Distribution in the Wafer-on-a-Wafer (WOW) Structure.
Hideki Kitada 1 , Nobuyuki Maeda 1 , Koji Fujimoto 2 , Kousuke Suzuki 2 , Tomoji Nakamura 3 , Takayuki Ohba 1
1 , The University of Tokyo, Tokyo Japan, 2 , Dai Nippon Printing, Kashiwa Japan, 3 , Fujitsu Laboratories Ltd, Atsugi Japan
Show Abstract Since conventional shrink scaling based on an empirical More's law has reached the limitation of manufacturability, performance, and power consumption, an alternative integration technology such as 3-dimentional processes is anticipated. Recently, novel through silicon via (TSV) integration process formed after wafer bonding based on wafer on-wafer (WOW) has been developed [1]. The WOW process provides the wafer-scale 3D manufacturability and high productivity of chip integration. Because the WOW employ the thinned Si wafer (<20um) stack process, the TSV dry etching and the copper plating process can be simplified. In this report, the stress of multi stacked Copper-TSV/Si wafers and Copper/Low-k device structure was analyzed using Finite Element Method (FEM). The wafer was stacked with face to back by using the Cyclotene™ adhesive. And the TSV formation after bonding was developed by self-alignment process based on the BEOL process. Therefore, the TSV after bonding process enabled the low temperature process compared with the conventional metal-metal bump connection about 400 degree C. In the WOW process of wafer bonding and the TSV, a low temperature (250 degree C) process was expected to reduce the TSV stress more than general BEOL process (400 degree C). The FEM analysis result showed that the TSV stress was small in the case of low temperature via last process. Moreover, in the low aspect TSV structure, the result showed low internal stress in Cu-Via plug and low residual stress around copper via. This fact was an advantage for the reliability of the TSV structure by WOW process. Especially, the influence of stress on the device structure, such as Tr and BEOL interconnect, was comparatively small. This simulation result showed effectiveness of WOW process in the points of structural complex TSV and device deterioration by stress with TSV process. By using this process, it was succeeded in the fabrication of seven layer multi stacked of 20um thinned Si wafer with 30 um diameter and 80um pitch TSV. In addition, the electrical characteristic of the TSV chain with two levels in three layers WOW was confirmed without the failure. It is shown that via after bonding technique of the WOW base is very excellent method for the chip minimization of 3D-IC and reduction of TSV size. The electric characteristics and the stress analysis of TSV will discuss in this presentation.[1] N. Maeda, et al. Proc. Advanced Metallization Conference (2008) p91-92.
11:30 AM - **F6.6/D8.6
Power Delivery, Signaling and Cooling in 3D Integrated Systems.
Muhannad Bakir 1
1 MiRC, Georgia Tech, Atlanta, Georgia, United States
Show AbstractIn this paper, we describe a novel 3D system that features low-cost and fully compatible electrical and fluidic I/O interconnects between strata. The electrical interconnects are used for power delivery and signaling between strata, and the fluidic interconnects are used to enable the rejection of heat from each stratum in the 3D stack. Each silicon die in the 3D stack contains the following features: 1) a monolithically integrated microchannel heat sink (MCHS); 2) through-silicon electrical vias (TSEVs) and through-silicon fluidic (hollow) vias (TSFVs); 3) solder bumps (electrical I/Os) and microscale polymer pipes (fluidic I/Os) on the side of the chip opposite to the microchannel heat sink. Microscale fluidic interconnection between strata is enabled by the combination of through-silicon fluidic vias and polymer pipe I/O interconnects. The chips are designed such that when they are stacked, each chip makes electrical and fluidic interconnection to the dice above and below. Consequently, power delivery and signaling can be supported by the electrical interconnects, and the heat removal from each stratum can be supported by the fluidic I/Os and microchannel heat sinks. Using the fluidic I/Os, the chip junction-to-ambient thermal resistance has been measured to be 0.24 C/W for a single chip.Due to the integrated microchannel heat sink and fluidic interconnects, the high-power chips can be placed anywhere in the 3D stack and are no longer restricted only to being at the top most layer for direct interfacing to a heat sink. This is in sharp contrast to other 3D integration technologies. The thermal resistance and pressure drop in the microchannel heat sink are both a function of the channel geometry; for example, increasing channel height reduces thermal resistance and pressure drop. However, as the microchannel heat sink height increases, so does the aspect ratio of the TSEVs (assuming fixed diameter). Unlike other 3D integration technologies that seek to thin down the silicon wafer to as small a thickness as possible before mechanical handling becomes challenging (~30-100μm), the microchannel heat sink requires a silicon wafer thickness of ~ 250 μm. This is an important fundamental difference and imposes different constraints on TSEV fabrication and optimization. To this end, we have developed novel processes for the integration of a MCHS and TSEVs in a Si wafer. Moreover, modeling and optimization algorithms are used to provide optimal designs for the electrical and thermal interconnect networks in a 3D system based on various performance constraints. The impact of TSV density on power supply noise in a 3D stack is also shown.
12:00 PM - F6.7/D8.7
Copper Deposition Technology for Thru Silicon Via Formation Using Supercritical Carbon Dioxide Fluids Using a Flow Type Reaction System.
Masahiro Matsubara 1 , E. Kondoh 1
1 , University of Yamanashi, Kofu Japan
Show AbstractNew interconnect process technologies are required to fabricate high performance LSIs. One of the crucial technological targets is the formation of MEMS-based thru Si vias in 3D IC. Cu electroplating is the most popular deposition technology being currently investigated; however, the deposition technology in supercritical fluids is becoming of crucial interest as a replacement of electroplating because of its excellent penetration capability of supercritical fluids. In this study, Cu deposition in thru via was carried out using a flow-type deposition processor that was designed to enable long time deposition [1,2].
A precursor, Cu(dibm)2, was dissolved in acetone and was supplied to a reaction chamber continuously. We used a one-dimensional deposition reactor. Cu films were fomed directly on Si having TSV holes formed by a usual BOSCH method. Deposition temperature was varied from 180 degC to 280 degC, and the precursor and H2 concentrations were fixid at 0.0292 mol%, 1.53 mol% respectively. Deposition time was 60 min. Cross-sectional view of Cu deposited in thru via at 220degC revealed Cu film reached 129 µm in a hole of 10 µm in dia.
The temperature dependence of the Cu-coating depth was studied. At 180 degC, Cu film reached full-depth (350 µm) but its thickness was very small. As the temperature increased, the maximum depth was decreased, whereas the film thickness increased. At 280 degC, a large film thickness at the via opening decreased rapidly with depth. At lower temperatures, the film thickness profiles became less depth-dependent. These experimental results were compared with numerically simulated results.
[1] M. Matsubara and E. Kondoh, 40th Autumn Meeting of Society of Chemical Engineering Japan, (Sep. 2008)
[2] M. Matsubara, M. Hirose, K. Tamai, and E. Kondoh, submitted to J. Eelctrochem. Soc.
12:15 PM - F6.8/D8.8
Fully Low Temperature (350°C) Processed Si PMOSFET with Poly-Ge Gate, Radical Oxidation of Gate-Oxide and Schottky Source/Drain for Monolithic 3D-ICs.
Munehiro Tada 1 2 , Jin-Hong Park 1 , Duygu Kuzum 1 , Gaurav Thareja 1 , Yoshio Nishi 1 , Krishna Saraswat 1
1 , Stanford University, Palo Alto, California, United States, 2 , NEC corporation, Sagamihara Japan
Show AbstractThe 3D integration paradigm addresses the power/delay issue of wires in devices by realizing shorter interconnect line length as well as higher logic density. A more promising 3D approach is monolithic stacking whereby active devices are built in back end of the line. The advantages of such approach are that it can achieve high vertical via density and scale geometries at the same rate as the CMOS technology. The monolithic 3D requires process temperature below 350°C in order not to damage the underlying devices and interconnects. In this paper, we have developed a novel low temperature LPCVD Ge growth technique and in-situ dopants activation for a gate electrode coupled with fully low temperature gate oxide and Schottky S/D processes.Conventionally, a LPCVD Si layer deposited at 500°C has been used as a seed for the Ge growth on SiO2. We have newly developed a technique to grow Ge on SiO2 below 350°C, featuring a diborane pretreatment. Depending on the partial pressure of diborane in the pretreatment, the substrate SiO2 is contentiously covered by boron and the Ge film is uniformly grown with a smooth surface (RMS~1nm). Weaker B-H bonds of B2H6 than Si-H bonds of SiH4 promote attachments of boron atoms on the SiO2 surface.Boron and phosphorous are in-situ doped using B2H6 and PH3 during the Ge growth and activated at 310°C and 350°C. By increasing the diborane flow ratio, the resistivity of the poly-Ge film decreases and significantly low resistivity of ~1mΩcm is obtained around the 0.2 diborane ratio. The crystalinity of Ge (111) and deposition rate also depend on the diborane flow ratio and excess doping makes the phase amorphous, resulting in high resistivity. This low resistive Ge is useful for gate electrodes on Fin and/or Gate-all-around type transistors due to the conformal electrode deposition by LPCVD. Here, we select the heavily boron doped Ge film for a p-type gate electrode and demonstrates the in-situ dopants activation in the fully low temperature planer type transistor.Si PMOS transistors using the in-situ boron activated Ge gate electrode are integrated with a radical oxidizing gate oxide and Schottky Ni, Pd or Pt silicide S/D at temperatures below 350°C. A 8.3nm gate oxide is formed by using SPA plasma with 2.45GHz microwave and O2/Ar chemistry at 350°C. The junctions of NiSi, PdSi and PtSi to n-Si are formed below 350°C. Significantly high forward/reverse current ratio of the diodes is obtained in the PtSi/n-Si junction, in which Ioff of the transistor is reduced below 10-14A/μm. Characteristics of the Si PMOSFET show excellent Ion/Ioff ratio over 107, low gate leakage and steep SSmin=77.9mV/dec. The estimated hole mobility is ~150cm2/Vs, which is compatible to a thermally grown oxide at 850°C. The low temperature Ge growth, gate oxide and Schottky S/D technologies are indispensable for a low thermal budget processing below 350°C, enabling to fabricate a transistor within metal interconnects for 3D applications.
12:30 PM - F6.9/D8.9
Metal-Induced Dopants Activation (MIDA) on Amorphous Germanium for Monolithic 3D-ICs.
Jin-Hong Park 1 , Munehiro Tada 1 2 , Kyeongran Yoo 1 , Woo-Shik Jung 1 , H. -S. Philip Wong 1 , Krishna Saraswat 1
1 Electrical Engineering, Stanford University, Stanford, California, United States, 2 Device Platforms Research Laboratories, NEC corporation, Sagamihara, Kanagawa, Japan
Show Abstract Germanium (Ge), by virtue of its low melting point, is a highly suitable material for 3D-ICs, which requires a low process temperature to prevent damaging the underlying devices and interconnects. A critical aspect currently plaguing Ge transistor integration for 3D application is the lack of dopant activation technique at sub-400°C. In this work, we demonstrate low temperature boron (B) and phosphorus (P) activation in amorphous (α)-Ge using metal-induced crystallization (MIC). This method can prove to be indispensible for gate, source, and drain formations at a low temperature required for 3D ICs. A 200nm thick α-Ge is deposited at 300°C by LPCVD on top of a thermally grown SiO2 on a Si (100) substrate. Then p- and n- type Ge films were created by implanting B (49BF2, 40keV, and 4e15cm-2) and P (P31, 90keV, and 4e15cm-2) ions. In total, three kinds of α-Ge films (undoped, B doped, and P doped) are prepared to investigate dopants activation. Reference (or control) samples are created by annealing each of these three types of samples for 1 minute at 600°C. A 5nm thick metal film is subsequently deposited on the α-Ge films to study dopants activation at a low temperature using MIC process. The samples are isothermally annealed in a N2 ambient for 1-3 hours at below 360°C. The annealed samples are then analyzed by x-ray diffraction (XRD), resistivity measurement, and transmission electron microscopy (TEM) systems. We first investigated the temperature at which MIC process occurs with eight different metals (Pd, Cu, Ni, Au, Co, Al, Pt, and Ti) on undoped Ge film after annealing for 1 hour at various temperatures (300-450°C). Then, we selected five metals (Pd, Cu, Ni, Au, and Co) which have a MIC process temperature below 380°C, having no self-nucleation in the α-Ge film. The selected MIC samples show a lower XRD peak intensity and a broader width at the half maximum points of Ge (111) XRD peak (thus, a lower crystal grain size) than the sample thermally annealed for 1 minute at 600°C. Because B and P atoms in the α-Ge film are rearranged and activated during the MIC process, we can conclude that B (with the above five metals) and P (with Co) atoms were activated during the MIC process at below 360°C. We predict that the reason why Co MIC process only activates P atoms is compensation process between P atoms and metals, mostly working as acceptor-like traps. The metal themselves also seem to contribute to a slight reduction in the resistivity of the film, and the amount of activated B and P atoms by MIC process are expected to be lower than one activated by thermal annealing process at 600°C. The low temperature dopants activation technique featuring the MIC process is demonstrated for (1) a Ge gate electrode in a Si P-MOSFET and (2) Ge N+/P & P+/N junction diodes in Ge MOSFETs. This technique is promising for integrating Ge transistors at low temperatures which is a critical requirement for 3D ICs.