Symposium Organizers
Tingkai Li Sharp Laboratories of America, Inc.
Yoshihisa Fujisaki Hitachi Ltd.
Jon Slaughter Freescale Semiconductor, Inc.
Dimitris Tsoukalas National Technical University
I1: Organic Nonvolatile Memories
Session Chairs
Tuesday PM, April 10, 2007
Room 3006 (Moscone West)
9:30 AM - **I1.1
Organic- and Bio-based Digital Memory Devices.
Yang Yang 1 2 3 , Ricky Tseng 1 3 , Liping Ma 1 2
1 Materials Sci. & Eng., UCLA, Los Angeles, California, United States, 2 California Nano System Institute, UCLA, Los Angeles, California, United States, 3 FENA Center, UCLA, Los Angeles, California, United States
Show Abstract10:00 AM - I1.2
Memory Effect in Organic Diodes containing Self-assembled Gold Nanoparticles
Hai Ping Wang 1 , S. Pigeon 2 , R. Izquierdo 3 , R. Martel 1
1 Chimie, Université de Montréal , Montréal , Quebec, Canada, 2 Thin films and microfabrication laboratory, OLA Display Corp., Montréal , Quebec, Canada, 3 Département d'informatique, Université du Québec à Montréal, Montréal , Quebec, Canada
Show AbstractElectrical bistability is reported in metal-organic-metal diodes. The device consists of two Al electrodes separated by a layer of organic material that contains embedded Au nanoparticles (NPs) supported by parylene nanopillars. The organic materials used in present work are 2-amino-4, 5-imidazoledicarbonitrile (AIDCN) and aluminum tris(8-hydroxyquinoline) (Alq3). Electrical characterization of the device made under vacuum condition shows two well-defined states with high (OFF) and low (ON) impedances. The ON/OFF ratio is about 104 for both kinds of devices. A negative differential resistance (NDR) in the current-voltage (I-V) characteristics is clearly observed. These bistable devices can be programmed and maintained in either the ON or OFF state for 8 months in air without any evidence of degradation. This conspicuous memory effect is rationalized in terms of charge storage mediated by the NPs states. The fabrication method is general and provides a good control on both the size-uniformity and the self-assembly of Au NPs embedded in the organic materials. The relationship of the electrical bistability to the nature and the thickness of the organic materials as well as the density of Au NPs will be addressed.
10:15 AM - I1.3
Programmable Memory Devices Using Semiconducting Nanoparticles in Insulating Polymers.
Basudev Pradhan 1 , Sudip Batabyal 1 , Amlan Pal 1
1 Dept. of Solid State Physics, Indian Association for the Cultivation of Science, Kolkata, West Bengal, India
Show Abstract10:30 AM - I1.4
Synthesis and Magnetism of 2D Mn(II) Carboxlates: Evidence of Remnant Moment at Room-Temperature
Shengming Liu 1 , Marshall Bremer 1 , Brandon Brandon 1 , John Lovaasen 1 , Anthony Caruso 1 , Douglas Schulz 1
1 Center for Nanoscale Science and Engineering, North Dakota State University, Fargo, North Dakota, United States
Show AbstractInitial studies toward the development of manganese(II) metal-organic complexes that possess a remnant moment at room temperature led us to the isolation of a new class of materials. A manganese(II) mixed-carboxylate complex, {Mn5(OC(O)CH3)6(OC(O)C6H5)4}n, was synthesized through a ligand exchange reaction under solvothermal conditions. Single-crystal XRD reveals a honeycomb-like 2D structure with the basic hexagonal Mn12 loops sharing edges. The sheets are spaced at 12 Å and linked into a 3D network with phenyl(benzoate) groups from one sheet interacting with both phenyl(benzoate) and methyl(acetate) groups of an adjacent sheet. Magnetic susceptibility characterization of {Mn5(OC(O)CH3)6(OC(O)C6H5)4}n) indicates antiferromagnetic exchange with a Weiss constant of -174 K and a transition toward ferromagnetic exchange below 10K observed in the χT(T). The absence of an imaginary component in the variable temperature susceptibility data indicates true antiferromagnetism yet no remnant moment was observed in M vs. H at 5K. By way of comparison, a closely related complex with the nominal stoichiometry Mn5(OC(O)CH3)5(OC(O)C6H5)5 does exhibit a remnant moment at room-temp (i.e., Hc = 30 Oe at 305K) with a powder x-ray diffraction pattern similar to {Mn5(OC(O)CH3)6(OC(O)C6H5)4}n. Recent results of this investigation will be discussed.
10:45 AM - I1.5
Resistance Switching in Organic–Based Devices; Mechanism and Addressability Issues.
Fredrik Jakobsson 1 , Xavier Crispin 1 , Magnus Berggren 1
1 Department of Science and Technology, Linköping University, Norrköping Sweden
Show AbstractIn the past few years, an increasing number of scientific contributions have reported bias-induced resistance switching for organic-based devices. These devices are appealing due to their low cost manufacturability, e.g. printing, and since they can be integrated into simple cross-point arrays.One example of such an organic memory device is Rose Bengal sodium salt sandwiched between indium tin oxide (ITO) and aluminum (Al) electrodes. Up to now, proposed switch mechanisms include electroreduction and field-induced conformational changes of the organic dye molecules (Bandyopadhyay et al, Appl. Phys. Lett. 2004, 84(6), 999-1001 and J. Phys. Chem. B 2003, 107, 2531-2536). However, conclusive evidence for either mechanism has not yet been presented.Here, we present a systematic study to rule out various mechanisms for the switching (redox reaction with ion motion, bistability of charge transfer salt, conformational changes). Similar switching behaviors are measured for many other molecules. The switch property does not appear to depend on the chemical nature of the organic molecules. Moreover, upon trying various electrode materials, ITO and/or Al electrodes have been identified to be the origin of the switch phenomenon. ITO and Al electrodes separated by the organic layer form conducting filaments, as demonstrated by the local dissipation of heat from the filaments analyzed using a high-resolution IR-camera.Switching of filaments has been reported for several decades, both in organic and inorganic materials. However, the switch behavior of Rose Bengal devices is polarity dependent, indicating that the switch mechanism is not of the same thermal run-away kind suggested for filamentary switch devices in the past. Moreover, the same filaments seem to be active after cycling the devices many times, indicating reversible filament formations. Similar results were recently reported for material systems commonly employed for organic light emitting diodes (M. Cölle et al, Org. El. 7 (2006) 305-312).When it comes to systems such as cross-point arrays of switch devices, several issues needs to be considered. A potential problem with filamentary switch devices is that they commonly require a very high current density to switch. This might result in problems such as potential drop along interconnect lines as well as very high circuit input currents (F.L.E. Jakobsson et al, Appl. Phys. Lett. 87, 063503 (2005)). By adding an extra semiconducting layer on top of the switch layer, leakage current from unaddressed devices can be greatly reduced, thus significantly improving system performance.
11:00 AM - I1: Organic
BREAK
11:30 AM - **I1.6
Silicon/Molecule Hybrid Devices.
James Tour 1
1 , Rice University, Houston, Texas, United States
Show AbstractAlthough a number of alternatives to silicon-based materials have been proposed, silicon remains the stalwart of the electronics industry. Generally, the behavior of silicon is controlled by changing the composition of the active region by impurity doping; while changing the surface (interface) states is also possible. As scaling to the sub-20 nm-size region is pursued, routine impurity doping becomes problematic due to its resultant uncertainty of distribution. Provided back-end processing of future devices could be held to temperatures that are molecularly permissive (300-350°C) and taking advantage of the dramatic increase in the surface-area-to-volume-ratios of small features, it is attractive to seek controllable modulation of device performance through surface modifications. If there is no intervening oxide between the p-rich molecules and the silicon, sequentially tuned molecular-structure changes can predictably regulate the device performances over a wide range. In this contribution, an electronically controlled series of molecules, from strong p-electron donors to strong p-electron acceptors, were prepared and systematically covalently attached as molecular monolayers onto the channel region of pseudo-MOSFETs (back gated), and the device modulation was studied. Changes of >2.5 V could be obtained in the threshold voltages by attaching monolayers atop the active regions of the transistors. Additionally, three-terminal field-effect transistors (FETs) were fabricated using intrinsic Si nanowires. Forming an F-terminated oxide surface significantly decreased the resistivity, increased the mobility, and they had a large hysteresis, enabling their possible use in memory devices.
12:00 PM - I1.7
Co Nanocyrstal Memory Devices Using Diblock Copolymer Micelle Templates
Chiyoung Lee 1 , Yongmu Kim 1 , Jang-Sik Lee 1 , Jaegab Lee 1 , Jeonghwa Kwon 2 , Byeong-Hyeok Sohn 2
1 School of Advanced Materials Engineering, Kookmin Univ., Seoul Korea (the Republic of), 2 Chemistry College of Natural Sciences, Seoul National Univ., Seoul Korea (the Republic of)
Show Abstract In this work, we present self-assembled diblock copolymer micelles can be used as a template to assemble Co nanocrystal arrays for charge storage layers in flash memory devices. Co-embedded diblock copolymer micelles were synthesized on the p-Si substrates having thin tunneling oxide of HfO2. Micelle templates were successfully removed by oxygen plasma treatment, resulting in CoOx nanocrystal arrays. It is demonstrated that CoOx nanocrystals were reduced to metallic Co by the hydrogen annealing. The resulting metallic nanocrystals were confirmed with a chemical shift of the Co2p3/2 peak by X-ray photoelectron spectroscopy analysis. We employed high-k dielectrics (HfO2 for both tunneling and blocking oxides) and high-work function metal gate (Pt) to engineer band-structures of memory devices. Co nanocrystals show very good distribution uniformity and the densities can be increased by a novel process. Devices exhibit program/erase characteristics that depend on the density of Co nanocrystals and thickness of tunneling oxide. The effects of nanocrystal density and tunneling oxide thickness on the memory windows as well as data retention characteristics will be discussed in detail.This work was supported by the ERC(CMPS, Center for Materials and Processes of Self -Assembly) program of MOST/KOSEF(R11-2005-048-00000-0)
12:15 PM - I1.8
Hierarchically Self-assembled Gold Nanoparticles in Polymer Matrix for Nonvolatile Memory.
Jung-Ah Choi 1 , Seong Jae Choi 2 , Sangkyu Lee 1 , Taeseup Song 1 , Chul Kim 1 , Jae-Young Choi 2 , Ungyu Paik 1
1 Division of Advanced Materials Science Engineering, Hanyang University, Seoul Korea (the Republic of), 2 Display Device & Material Lab, Samsung Advanced Institute of Technology, Yongin Korea (the Republic of)
Show Abstract12:30 PM - I1.9
Organic Composite Submicron Rods for Memory Applications.
Ashavani Kumar 1 , Victor Pushparaj 1 , Saravanababu Murugesan 2 , Jin Xie 2 , Caterina Soldano 1 , George John 3 , Omkaram Nalamasu 1 , Ajayan Pulickel 1 , Robert Linhardt 2
1 Materials Science and Engg., Rensselaer Polytechnic Institute, troy, New York, United States, 2 Department of Chemical and Biological Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States, 3 Department of Chemistry, City college of New York, New York, New York, United States
Show Abstract12:45 PM - I1.10
Electrical Properties of CuTCNQ Based Organic Memories Targeting Integration in the CMOS Back End-of-line.
Robert Mueller 1 , Joris Billen 1 3 , Rik Naulaerts 1 3 , Olivier Rouault 1 4 , Ludovic Goux 2 , Dirk Wouters 2 , Jan Genoe 1 , Paul Heremans 1 3
1 MCP/PME, IMEC vzw., Leuven, Vlaams-Brabant, Belgium, 3 ESAT, KULeuven, Leuven, Vlaams-Brabant, Belgium, 4 , INSA Toulouse, Toulouse France, 2 SPDT/FE, IMEC vzw., Leuven, Vlaams-Brabant, Belgium
Show AbstractI2: Nano-Particle and Advanced Flash Memories
Session Chairs
Erwin Prinz
Dimitris Tsoukalas
Tuesday PM, April 10, 2007
Room 3006 (Moscone West)
2:30 PM - **I2.1
Materials Challenges in Automotive Embedded Non-Volatile Memories.
Erwin Prinz 1
1 Technology Solutions Organization, Freescale Semiconductor, Austin, Texas, United States
Show AbstractSilicon-based nonvolatile memories are widely used in microcontrollers, where they are embedded into a monolithic system on a chip (SoC) which also includes high speed logic transistors, cache SRAM, and peripheral circuits for communicating with the external world. The physical principle most widely exploited for nonvolatile code and data storage is charge storage in floating gates. Recently, charge storage in nitride traps and nanocrystals also has been explored. The most demanding use profiles with respect to temperatures, data retention times, and low failure rates are encountered in automotive engine control applications, where junction temperatures up to 150°C are common, for 1000's of hours. Starting with the 130nm technology node, embedded Flash technology has been integrated with copper interconnects, and at the 90nm node, low dielectric constant interlevel dielectrics are also employed to increase circuit performance. To achieve automotive reliability, the materials surrounding the silicon floating gate, nanocrystal, or nitride charge storage area must be evaluated for parasitic charge storage, write/erase stress-induced leakage current, and other parameters important for reliability. Any movement of parasitic charge, potentially over a long period of time, can reduce the sensing window of the Flash EEPROM bitcell.In this talk, materials options for the various parts of the Flash bitcells are outlined, and the state of the art for 90nm embedded nonvolatile memory is summarized. Aspects of scaling to 65nm and beyond are also discussed.
3:00 PM - I2.2
Formation of Ge Nanocrystals in Lu2O3 High-k Dielectric and its Application in Non-Volatile Memory Device
Mei Yin Chan 1 , Pooi See Lee 1
1 Materials Science and Engineering, Nanyang Technological University Singapore, Singapore Singapore
Show AbstractA simple technique for the formation of Ge nanocrystals embedded in amorphous Lu2O3 high-k dielectric was demonstrated by pulsed laser ablation followed by rapid thermal annealing in N2 ambient. The structure and composition of the Ge nanocrystals in the oxide matrix have been studied by atomic force microscopy (AFM), transmission electron microscopy (TEM) and x-ray photoelectron spectroscopy (XPS). A significant change in the structural properties and chemical composition of the film was obtained upon annealing. Dot-shaped topography was observed from AFM characterization on the surface morphology of the annealed sample indicating the formation of Ge nanocrystals. Cross-sectional and plan-view TEM images confirmed the formation of small Ge nanocrystals in amorphous Lu2O3 matrix with a mean size of about 9nm in diameter and a high areal density of 7 x 1011cm-2. The nanocrystals are well-isolated by the amorphous Lu2O3 in between, with almost spherical shape which are favorable for non-volatile memory (NVM) application due to an effective charge confinement. XPS measurements on the as-deposited sample indicate the existence of Ge in its oxidized state, consisting of GeO2 and Ge suboxides. A complete reduction of GeO2 and GeOx was obtained after the annealing treatment which provides Ge nuclei for nanocrystal formation. It is found that a low annealing temperature of 400oC is sufficient to dissociate the GeO2 and GeOx leading to the formation of Ge nanocrystals. The application of the nanocrystals in NVM devices was demonstrated by C-V characterization of the memory capacitor devices fabricated with Al2O3 control oxide layer. C-V results show a significant effect of the structure and composition of the film on the electrical performance of the device. The annealed device exhibits good memory behavior with a large memory window of 1.2Vachieved with a low operation voltage.
3:30 PM - I2.4
Floating Nanodot Gate Memory Fabrication with Biomineralized Nanodot as Charge Storage Node.
Atsushi Miura 1 , Yukiharu Uraoka 1 , Takashi Fuyuki 1 , Ichiro Yamashita 1 2
1 Graduate School for Materials Science, Nara Institute for Science and Technology, Ikoma Japan, 2 , JST, Kawaguchi Japan
Show AbstractFloating nanodot gate memory (FNGM) is a promising candidate for future non-volatile memory. The performance of FNGM depends on the characteristics of utilized nanodots such as material, size, shape, distribution and density. Although the control of these issues is major challenge, it is still difficult by conventional methods. We adopted a biological path to solve these issues. Utilization of a cage-shaped supramolecular protein, ferritin, is potential option to achieve uniform and high-density memory node fabrication with size defined nanodots. Ferritin can biochemically form varieties of inorganic nanoparticle in its cavity by biomineralization such as metal oxides and compound semiconductors. Biomineralized nanodots are uniform in size and shape due to the restricted size of protein shell. Moreover, chemical flexibility of protein enables high-density and selective 2D arrangements of bionanodot on the substrate. Utilization of ferritin and its bionanodot offers precise control of size, shape, distribution and density of charge storage node of FNGM. In this contribution we demonstrate the FNGM fabrication with supramolecular protein ferritin and its inorganic bionanodot.The memory effect in FNGMs was investigated by fabricating bionanodot embedded metal-oxide-semiconductor (MOS) devices. Cobalt oxide bionanodot (Co-core) accommodated ferritin was deposited on p-type Si substrate with a 3 nm tunnel SiO2 layer. After the elimination of protein, Co-core array were buried into control SiO2 layers and metal electrode was deposited to make MOS structure. SEM and TEM images revealed uniform distribution of Co-cores on SiO2 surface with high density (>8E11 cm-2) and discrete distribution in stacked MOS structure. High frequency capacitance-voltage (CV) characteristics of Co-core embedded MOS capacitor at 1 MHz showed the obvious flat band shift with gate voltage sweep. Note that the CV of MOS capacitor fabricated without Co-core or with apoferritin showed no hysteresis. It suggests that observed flat band shift is due to the charge confinement to the embedded Co-core. Good charge retention after 10000 sec and endurance characteristics up to 100000 cycles of program/erase operation were observed on Co-core embedded MOS capacitor. The drain current-gate voltage (ID-VG) characteristics of Co-core embedded MOSFET showed threshold voltage shift due to the charge confinement to the embedded bionanodot as well as in capacitors. Co-core embedded MOSFET showed similar programming pulse duration dependence and obvious increase in memory window width with increasing of pulse duration. Charge retention characteristics of Co-core embedded MOSFET retained good memory window width after 10000 sec.These results indicate ferritin cores can be used as charge storage node of flash memory. This work proved the feasibility of the biological path for fabrication of electronic device components.
3:45 PM - I2.5
Self-aligned TiSi2/Si Hetero-nanocrystal Floating Gate Nonvolatile Memory
Yan Zhu 1 , Bei Li 1 , Jianlin Liu 1
1 EE Department, University of California, Riverside, Riverside, California, United States
Show AbstractSi nanocrystal as discrete floating gate in nonvolatile MOSFET memory devices has been extensively investigated [1, 2]. The issue of defect-related traps as reported in [2] for Si nanocrystals has led to device thermal instability. Although metal nanocrystal provides stable deep storage levels, the metal/oxide reaction has hindered its further application. In this work, we report that a novel MOSFET memory device with TiSi2/Si hetero-nanocrystals floating gate could resolve these issues.Using self-aligned silicidation method [3], TiSi2/Si hetero-nanocrystals were fabricated on ultra-thin thermal oxide. The process involved is thoroughly compatible to existing silicon process. The experiments showed very good self-aligned growth of TiSi2/Si hetero-nanocrystals on thin oxide with a slight size increase as compared to the original Si nanocrystals [4]. The metallic silicide on Si nanocrystal behaves as an extra quantum well to trap electrons. The activation (de-trapping) rate exponentially depends on the quantum well depth. Therefore, it enables a much lower charge loss rate, namely, much longer retention time. The prototype MOSFET memory cells with TiSi2/Si hetero-nanocrystal floating gate were fabricated. Programming/erasing performance of the device was investigated using both F-N tunneling and hot carrier injection. In both cases, the devices exhibited much better programming/erasing speeds, larger memory window, and very promising retention characteristics. The dual-bit/cell function was also investigated by writing charges to the hetero-nanocrystals near drain or source side, which showed a decent threshold voltage different between different read schemes. The TiSi2/Si hetero-nanocrystal memory showed similar endurance characteristics to the Si nanocrystal memory. In summary, TiSi2/Si hetero-nanocrystal memory is very promising in replacing Si nanocrystals for future-generation nonvolatile memory devices, fulfilling the target of being smaller, faster, and less power consuming.References[1] S. Tiwari, et al. Appl. Phys. Lett. 68, 1377 (1996).[2] Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, Jpn. J. Appl. Phys. 38, 425 (1999).[3] J. P. Gambino, and E. G. Colgan, Mater. Chem. Phys. 52, 99 (1998).[4] Yan Zhu, Dengtao Zhao, Ruigang Li, and Jianlin Liu, Appl. Phys. Lett. 88, 103507 (2006)* Corresponding author: Jianlin LiuEmail:
[email protected]: (951) 827-7131; Fax: (951) 827-2425
4:00 PM - I2: Post-Flash
BREAK
4:30 PM - I2.6
Temperature Dependence of Hole and Electron Conductance in Silicon Nanocrystal Arrays in SiO2
Gerald Miller 1 , Tao Feng 1 , Harry Atwater 1
1 Applied Physics, California Institute of Technology, Pasadena, California, United States
Show Abstract4:45 PM - I2.7
Magnetic Resonance Studies of Silicon Nano-Crystal Flash Memory Structures.
Jason Ryan 1 , Patrick Lenahan 1 , Lucky Vishnubhotla 2 , Sherry Straub 2 , Muralidhar Ramachandran 2 , Rajesh Rao 2 , Tushar Merchant 2 , Peter Kuhn 2
1 Materials Science and Engineering, The Pennsylvania State University, University Park, Pennsylvania, United States, 2 , Freescale Semiconductor, Austin, Texas, United States
Show AbstractAs the fundamental physical limits of conventional flash memory are approached, new forms of non-volatile charge storage structures must be explored. Conventional Flash memory devices suffer from stress induced leakage currents (SILC) caused by trap assisted tunneling which results in a reduction of data retention time [1-5]. The continued scaling of Flash memory devices has caused trap assisted tunneling related reliability problems to become more prominent [1-5].A promising potential solution to the trap assisted tunneling problems is the use of very small (mean diameter <10 nanometers) silicon nano-crystals [6]. In theory, silicon nano-crystal flash memory structures could reduce or eliminate the reliability problems associated with trap assisted tunneling because the tunneling process clearly involves highly localized tunneling current paths [4, 5, 7]. The introduction of nano-crystals will clearly help with the SILC problems involving the dielectric between the silicon channel and the nano-crystals (tunnel oxide) but the open spaces between the nano-crystals may lead to new problems. In a nano-crystal device, oxides “above” the nano-crystal layer (interlayer oxide) are exposed to charge carriers. In this study, we have begun to utilize electron spin resonance (ESR) measurements on silicon dioxide/silicon nano-crystal/silicon dioxide structures to explore the interaction of charge carriers and oxide defects in these systems. To simulate device operation, ESR measurements were made before and after the structures were subjected to electron and hole flooding. The densities of several intrinsic paramagnetic defects (most importantly, E’ centers) are greatly altered by the electron or hole flooding. We find that various post-deposition treatments quite significantly reduce or enhance the generation of these paramagnetic defects. A comparison of ESR and “electronic” measurements provides some physical insight into “electronic” roles these defects play. We find a strong, but imperfect, correlation between E’ generation and oxide leakage current. Preliminary results also suggest that, at least for the electron injection case, the generated E’ centers are electrically neutral. An additional interesting observation is that our results also indicate that there are far lower densities of silicon/silicon dioxide interface defects (Pb centers) located at the silicon nano-crystal/silicon dioxide interface than at the silicon channel/silicon dioxide interface. This surprising result may provide insight into the underlying physical mechanisms involved in interface trap generation. [1] P. Pavan et al., Proc. IEEE 85, (8) 1997[2] R. Bez et al., Proc. IEEE 91, (4) 2003[3] D. Ielmini et al., Microelectron. Eng. 80, 2005[4] R.A. Rao et al., Solid-State Electron. 48, (9) 2004 [5] J. De Blauwe, IEEE Trans. Nanotech. 1, (1) 2002[6] S. Tiwari et al., IEDM Tech. Digest 1995[7] B. De Salvo et al., IEEE Trans. Dev. Mater. Reliab. 4 (3) 2004
5:00 PM - I2.8
Charging Model of a Si Nanocrystal-based Floating Gate in a Quantum Flash Memory.
Yann Leroy 1 , Anne-Sophie Cordan 1 , Bertrand Leriche 1 , Daniel Mathiot 1
1 Solid State Electronics, InESS-ENSPS, Illkirch France
Show AbstractTuesday, April 10New Presenter - I2.8 @ 4:00 pmCharging Model of a Si Nanocrystal-based Floating Gate in a Quantum Flash Memory. Daniel Mathiot
5:15 PM - I2.9
Charge-trap Flash Memory by Partially-oxidized Amorphous Si Containing Nanodots.
Sangjin Park 1 , Daigil Cha 1 , Kwang Soo Seol 1 , Sangmin Shin 1 , Sangmoo Choi 1 , JungHun Sung 1 , Yoondong Park 1 , Joong Jeon 1 , InKyeong Yoo 1 , Eunha Lee 2 , Yo-Sep Min 3
1 Semiconductor device and material lab, Samsung Advanced Institute of Technology, Suwon Korea (the Republic of), 2 AE center, Samsung Advanced Institute of Technology, Suwon Korea (the Republic of), 3 Nano Fabrication Technology Center, Samsung Advanced Institute of Technology, Suwon Korea (the Republic of)
Show AbstractWe introduce a fabrication method of Si nanodots (NDs) by partially-oxidizing amorphous Si (a-Si) grown by ion beam sputtering deposition (IBSD). A 2nm-thick a-Si layer was grown on top of a 5nm-thick thermal-oxide tunneling layer by reactive IBSD in ultra high vacuum, and subsequently oxidized by annealing the a-Si layer in 10% O2/N2 ambient at 900 oC for 1~9 min. After oxidation, a 20 nm thick Al2O3 control-oxide layer was grown by atomic layer deposition. We observed a positive shift of the memory window as the oxidation time increases, resulting from the decrease of the hole-trap sites. By 3-min oxidation we obtained Si NDs with an average size of 1~1.5nm and an areal density of ~2x1012/cm2 in partially-oxidized a-Si matrix. With this storage node, we successfully achieved a small charge-loss rate with a flat-band voltage shift less than 0.5V at 200oC, 2hr, which corresponds with 10 year data retention and a good endurance up to 105 cycles.
5:30 PM - I2.10
Multi-Bit Localized Charge Trapping Memories – Device Scaling of Twin Flash Cells to a 60nm Generation.
Torsten Mueller 1 , Ch. Kleint 1 , M. Isler 1 , S. Riedel 1 , T. Hoehr 1 , M. Strassburg 1 , F. Beug 1 , V. Pissors 1 , J. Sachse 1 , D. Manger 1 , D. Caspary 1 , S. Parascandola 1 , D. Olligs 1 , H. Boubekeur 1 , F. Heinrichsdorf 1 , V. Polei 2 , J. Gupta 1 , D. Pritchard 1 , U. Bewersdorff-Sarlette 1 , M. Verhoeven 1 , M. Markert 1 , Ch. Ludwig 1 , E. Stein v. Kamienski 1 , Th. Mikolajick 3 , N. Nagel 1
1 , Qimonda, Dresden Germany, 2 , Infineon Technologies, Dresden Germany, 3 Chair of Electronic- and Sensor Materials, Technical University of Technology and Mining, Freiberg Germany
Show Abstract5:45 PM - I2.11
Self-Organization of Ge Nanocrystals on FIB Patterned Substrates for Memory Applications
Isabelle Berbezier 1 , Alim Karmous 1 , Pierre-David Szkutnik 1 , Antoine Ronda 1
1 L2MP, CNRS, Marseille France
Show AbstractThe aim of this work is to develop a fabrication process based on Si or SiO2 FIB nanopatterning followed by Ge NCs self-organization. One of the major challenges of the study is to perfectly understand and control the fabrication of NC floating gate nanostructures in order to determine and to investigate electrical charging, discharching and retention mechanisms still under debate. The originality of the process developed is the scalability of NC size and density and the precise placement and ordering of NCs induced by the regular array of focused ion beam (FIB) nanoscale patterns. Combination of FIB nano-patterning and natural formation of Ge islands permits to circumvent most of the problems induced by self-organisation with a fabrication process of device structures with minimum perturbation of the conventional MOS transistor technology.The work has been divided in 5 major tasks : (1) Nano-patterning of the substrate by Focused Ga+ Ions Beam at the nanometer scale. The results indicate that holes of 15 nm diameter can be milled with a 50kV single beam FIB. The smallest pitch of 2D holes array created was 23 nm (hole diameter ~ 15 nm) which confirms the possibility to reach a hole density of ~ 2x1011 /cm2 which approximately corresponds to the optimized density obtained for memory devices in the literature. (2) Cleaning of the substrate by thermal annealing in ultra-high vacuum. Investigations have focused on the conditions for soft thermal annealing to guarantee total removal of crystalline defects and desorption of Ga implanted atoms without modifying the holes shape/size. Two different cleaning procedures based on chemical etching and rapid thermal annealing cycles have been developed on Si substrate and on SiO2. (3) Fabrication of an array of isolated Ge quantum dots (QD). Two processes using FIB patterning have been developed one on Si substrate and the other on thin SiO2 layer. We show that Ge NC are ordered either inside the FIB holes or in between the FIB holes on Si substrate depending on the growth temperature. We explain this behaviour by kinetically limited nucleation at low temperature and by minimization of elastic energy at high temperature. On SiO2, NC size and density can be controlled by adjusting the initial deposited thickness. Positioning of Ge NC is mainly controlled by surface energy minimization. 2D arrays of perfectly ordered highly dense (> 1011/cm2) and ultra-small (~ 20 nm) Ge dots have been obtained. (4) Fabrication of the oxide (tunnel and control oxide) by thermal oxidation. Tunnel SiO2 oxide layers used were 3.5 and 5 nm thick, showing perfect C-V characteristics and low leakage currents. Control oxide was a TEOS stoichiometric SiO2 layer.(5) Memory device fabrication and electrical characterisation. Capacitors and transistors samples were fabricated. The C-V characteristics of samples without and with FIB ordering will be presented and compared.
I3: Poster Session: Organic and Nano-particle Flash Memories
Session Chairs
Dimitris Tsoukalas
Y. Yang
Wednesday AM, April 11, 2007
Salon Level (Marriott)
9:00 PM - I3.1
Making Plastic Remember: Electrically Rewritable Polymer Memory Devices.
Dominic Prime 1 , Shashi Paul 1
1 Emerging Technologies Research Centre, De Montfort University, Leicester, Leicestershire, United Kingdom
Show AbstractIn recent years there has been a growing interest in both academia and industry in the field of organic electronics and organic semiconducting materials as low cost, easily processible alternatives to silicon and other inorganic semiconductors. There have so far been successful implementations of devices such as organic field effect transistors (OFETs), organic solar cells and organic light emitting diodes (OLEDs), with OLED’s being the main organic devices to have achieved commercial success. In the field of non-volatile polymer memory devices (PMDs) there has been considerably less research conducted. Plenty of structures have shown bistable behaviour, however to make a viable memory devices any new organic memory must either match, or surpass the performance of conventional silicon memory in terms of retention time, memory cycles and power consumption [1]; criteria which so far polymer memories fail to meet sufficiently in one, or more areas.
Among the most promising PMDs to date are devices consisting of an admixture of organic polymer, nanoparticles, and small organic molecules deposited between top and bottom metal electrodes to form a crossbar structure [2, 3]. When voltages are applied, the device can switch between two different conductivity states, with the state being read by an intermediate voltage.
PMDs based on active layers containing gold nanoparticles with 8-hydroxyquinoline (8HQ), and also C
60 with 8HQ will be presented, showing the devices’ electrical characteristics and memory performance attributes. Results presented will give a greater understanding of the physical mechanisms responsible for the change in conductivity states of these devices, which is essential for the realisation of viable organic memory technologies.
References:
[1] J. C. Scott. "Is There an Immortal Memory?" Science, 304, 62-63, (2004)
[2] J. Ouyang, C. -W. Chu, C. Szmanda, L. Ma, Y. Yang, "Programmable Polymer Thin Film an Non-Volatile Memory Device" Nature Materials, 3, 918-922, (2004)
[3] S. Paul, A. Kanwal, M. Chhowalla. "Memory Effect in Thin Films of Insulating Polymer and C60 Nanocomposites" Nanotechnology, 17, 145-151, (2006)
9:00 PM - I3.10
Oxide-nitride-oxide Dielectric Stacks with Embedded Si-nanoparticles Fabricated by Low-energy Ion-beam-synthesis.
Vassilis Ioannou-Sougleridis 1 , Caroline Bonafos 2 , S. Schamm 2 , G. Ben-Assayag 2 , P. Dimitrakis 2 , V. Vamvakas 2 , P. Normand 2 , Dimitris Tsoukalas 3
1 , IMEL/NCSRD, Aghia Paraskevi Greece, 2 , CEMES/CNRS, Toulouse France, 3 Applied Sciences, National Technical University, Athens Greece
Show Abstract9:00 PM - I3.11
The Study on Charge-trapping Mechanism in Nitride Storage Flash Memory Device.
Jia-Lin Wu 1 , Hua-Ching Chien 1 , Chi-Kuang Chang 1 , Chien-Wei Liao 1 , Chih-Yuan Lee 1 , Je-Chuang Wang 1 , Yung-Fang Chen 2 , Chin-Hsing Kao 1
1 Semiconductor Laboratory, Chung-Cheng Institute of Technology, National Defense University, Taoyuan Taiwan, 2 Department of Physics, National Taiwan University, Taipei Taiwan
Show AbstractThe nitride storage flash memory with polysilicon-oxide-nitride-oxide-silicon (SONOS) structure has received much interest recently due to lower operation voltage, simpler fabrication process, higher density, and elimination of the drain induced turn on effect and multi-bit operation. Contrary to the floating gate device where charges are uniformly stored in the floating gate, the charges are discretely trapped in the nitride thin film. Therefore, the distribution of nitride trap is very significant in understanding the trapping efficiency of flash memory devices.In this work, the charge-trapping energy level distributions of SiNx films with different composition ratio deposited by low-pressure chemical vapor deposition (LPCVD) were first characterized by photoluminescence (PL) measurement. Moreover, using F-N/CHE program and charge pumping techniques, the vertical location and the lateral distribution of programmed charges are investigated in the nitride films with different composition ratio.The study offers strong evidence that the density of charge-trapping levels in the Si-rich nitride is higher than the standard nitride. A simple qualitative model and calculation explains that the trapping level distributions in the SiNx films are shallower by increasing relative Si-content. Furthermore, we have observed the nitride trap vertical location was changed by adjusted Si/N composition ratio. And the lateral distribution of hot electron programmed charges in the Si-rich nitride is broader than that in the standard nitride because it offered more charge-trapping sites and shallower charge-trapping levels. In summary, the study can help researchers to understand the nitride charge-trapping mechanism and the analysis of optical/electrical characteristics.
9:00 PM - I3.12
A Comparison of N+ type and P+ type Polysilicon Gate in High Speed Non-Volatible Memories
Moon Kyung Kim 1 , Soodoo Chae 2 , Chungwoo Kim 2 , Sandip Tiwari 1
1 Electrical and Computer Eng., Cornell University, Ithaca, New York, United States, 2 Semiconductor R&D Center, Samsung Electronics, Kiheung Korea (the Republic of)
Show AbstractSilicon-Oxide-Nitride-Oxide-Silicon (SONOS) [1] and nano-crystal memory [2] have been considered as a replacement floating gate memory due to simple process, low voltage operation and high speed. In the SONOS memory, an ultra-thin oxide-nitride-oxide (ONO) film with high trap density and strong localization of the trapping provides the scalability and retention. This may allow longer retention with thinner tunneling dielectrics, leading to lower operating voltages.However for the high speed performance, SONOS needs improvement in erase time - the discharging process of electrons from the traps. Thus we have speculated on the effect of electric fields in the trapping-control gate region, and characterized the effects of doping on poly-silicon gate in SONOS memory device. Our experiments compare the characteristics of SONOS memories between n+ type and p+ type polysilicon gate. Figure 1 shows the schematics of these structures. SONOS memory devices have been fabricated with 0.5 um n+ type gate or p+ type gate on SOI substrates using the conventional CMOS processing technology. The tunneling oxide of 3 nm thickness was grown at 900 C and then a Si3N4 film of 5.5 nm and the blocking oxide layer of 7 nm were deposited by low pressure chemical vapor deposition (LPCVD). Figure 2 shows a transmission-electron micrograph of the cross-section of this grown and deposited memory stack with the dark region as the silicon nitride. After these gate stacks process, n+ type or p+ type poly-silicon is deposited. Using the program/erase threshold voltage window as 4 V in p+ type poly-silicon gate memory, the program time is approximately 20 us at 16 V program voltage and the erase time is about 1 ms at a –16 V erase voltage using FN tunneling method. The capture and erase characteristics also show asymmetries in the capture and erase processes due to the physical differences in the processes themselves. The capture process is based on Fowler-Nordheim injection where the relevant capture cross-section is related to the extent of the potential perturbation of the defect. This capture cross-section is one to two orders of magnitude smaller than that of silicon nanocrystals. The erasure process is presumably a Poole-Frenkel mechanism, or other similar de-trapping process with strong localization and field-dependence. The erase time of SONOS memory device is somewhat slow, and it is due to the injection of electrons through top oxide from the gate and heavy mass of holes. To solve this problem, several methods have been introduced recently. Using a high k material instead of SiO2 thin film is useful for decreasing the transmission of electrons in the top oxide due to the capacitive coupling [3].Also we expect that the higher work-function of p-type gate to improve erase speed. Figure 4 shows that the erase speed of p+ gate is much faster than that of n+ gate. The work will describe detailed experimental measurements in support of this conclusion.
9:00 PM - I3.13
The Effects of the LDD process on Short-channel effects in Nano-scale Charge Trapping Devices.
Moon Kyung Kim 1 , Soodoo Chae 2 , Chungwoo Kim 2 , Jooyeon Kim 3 , Sandip Tiwari 1
1 Electrical and Computer Eng., Cornell University, Ithaca, New York, United States, 2 Semiconductor R&D Center, Samsung Electronics Co, Kiheung Korea (the Republic of), 3 School of Electricity & Electronics, Ulsan college, Ulsan Korea (the Republic of)
Show Abstract9:00 PM - I3.14
Silicon Compatible Nonlinear Dielectric as Tranistor Gate for use as Nonvolatile Memory Element.
Joseph Cuchiaro 1 , Edwin Dons 1 , Jie Yao 1 , S. Sun 1 , Catherine Rice 1 , Lloyde Provost 1 , Gary Tompa 1
1 , Structured Materials Industries, Inc., Piscataway, New Jersey, United States
Show AbstractNonvolatile memory elements have been demonstrated using nonlinear dielectric thin films (NLD) implemented as a transistor gate (NLDFET). The NLD films are formed using Metal Organic Chemical Vapor Deposition (MOCVD). The NLD films exhibit a hysteresis characteristic obtained from application of an applied voltage to the transistor gate in sufficient magnitude to modulate the inversion region of the underlying silicon post removal of the applied voltage. The hysteresis property is obtained at extremely high speed (< 10 ns) for both write and erase operation and at low voltages compatible with state-of-the-art silicon integration (90nm and below). Thus, the our NLD films have a significant potential to be implemented as a high-density nonvolatile memory element that meet and surpass existing FLASH technology in a single transistor memory. Further, the NLD films can replace SiO2 gate materials in logic elements. Successful implementation of NLD films into silicon integrated circuits would revolutionize existing stand-alone and embedded memory technology.In this work, we report the materials properties of NLD thin films grown by SMI’s MOCVD technology for NLDFET application into silicon integrated circuit devices. General NLD film process parameters relevant to silicon transistor integration, NLD material properties, NLDFET device electrical performance are addressed.
9:00 PM - I3.16
Effect of AlON Thin Films as Top Blocking Oxide for NVM.
Kyungsoo Jang 1 , Sunghyun Hwang 1 , Kwangsoo Lee 1 , Jeoungin Lee 1 , Hyungjune Park 1 , Seongwook Jeong 1 , Junsin Yi 1 , Ho-kyoon Chung 2 , Byoung-Deog Choi 2 , Ki-yong Lee 2
1 , SungKyunKwan University, Suwon Korea (the Republic of), 2 , Samsung SDI Co, Ltd., Gyeonggi-do Korea (the Republic of)
Show AbstractThe state-of-the-art techniques for Non-volatile Memory (NVM) have been an important part of modern information processing systems. Among them, one of noticeable technique is the usage of Silicon-Oxide-Nitride-Oxide-Silicon (SONOS). According to previous studies, as physical size of SONOS structure gradually become smaller, vertical size of device material is tend to decrease as well. Specifically in the case of gate oxide, this characteristic causes leakage current problem when oxide size is within special size. To solve this problem effectively, various technique are considered to achieve increase of dielectric constant of gate oxide layer. One of them is to apply material with increased dielectric constant. Throughout ensuring of charge storage, we can expect decrease of leakage current which flows within gate. In this study, we examined the electrical properties of AlON among various high-k materials which will be used for top blocking oxide layer. For the preparation of thin film, AlON thin films of 35Å~65Å thickness were deposited by RF magnetron sputtering on n-type silicon (Si) substrate of (100) orientation using Ar and O2 gas at substrate temperature of 300C. After that, electrical properties of Metal-Insulator-Semiconductor (MIS) type of AlON was analyzed and then characteristic of high-k(K)/Nitride(N)/Oxide(O) structure in MIS was studied. From this experiment, we observed significant result from the case of AlON which has approximate depositing thickness of 40Å. As the value of capacitance-voltage (C-V) hysteresis of this AlONwas 0V, the size of memory is almost value of 0 as well. Therefore, we concluded that this AlON can function as good insulator as well as blocking oxide in KNO structure under specific circumstance. Besides, we also found new characteristic, increased state of flatband voltage(VFB) according to increase of depositing thickness of AlON.
9:00 PM - I3.17
Synthesis and Non-volatile Memory Behavior of Redox Active Conjugated Polymer Containing Ferrocene Unit
Tae-Lim Choi 1 , Kwang-Hee Lee 2 , Won-Jae Joo 2 , Sangkyun Lee 2
1 Electronic Chemical Material Division, Cheil Industries, Inc, Uiwang-si, Gyunggi-do, Korea (the Republic of), 2 Display Device and Material Lab, Samsung Advanced Institute of Technology, Yongin-si, Gyunggi-do, Korea (the Republic of)
Show AbstractDuring the past decade, organic electronics have attracted great amount of attentions after demonstrating their applications on OLEDs, OTFTs and photovoltaic cells. It is due to their advantages such as flexible and low-cost devices arising from solution process such as spin-casting and ink-jetting. Among the several research fields on organic electronics, one of the newly emerging areas is the organic memory application where information is stored in organic materials. In addition to the common advantages for organic electronics, the organic memory can take advantages from its good scalability and 3D stacking to achieve high-density memory. Recently, many research groups have reported non-volatile organic memory device based on various mechanisms. Here, we demonstrate the synthesis of a new conjugated polymer with redox active functionality, ferrocene and its non-volatile memory behavior. In organic memory devices, the data are stored based on a change in the resistance of the organic layer. Our study focuses on ferrocene as the active component since its redox is well-studied and ferrocinium (Fe3+), the oxidized form is also stable which gives possibility for the non-volatility. Therefore, the design concept was to attach ferrocene to conjugated polymer to induce bistability by redox process and this could be applied a resistance memory. With this consideration, a new polymer, PFT2-Fc was synthesized by Suzuki polymerization similar to the well-known polymer, PFT2 used in OTFT devices. Ferrocene group was randomly inserted in the polymer backbone to give high molecular weight PFT2-Fc. HOMO and the band gap of the polymer were found to be 5.3 eV and 2.4 eV respectively. CV revealed two oxidation potentials at 0.6 and 1.0 V. This polymer was fabricated into device with ITO/polymer/LiF/Al structure. The initial memory behavior was observed with I-V characteristics by sweep mode. The device was turned on at -2V allowing high current to flow and turned off at 1.4V. The endurance of our memory device was examined by write-read-erase-read cycles (-2 V/0.2 V/2 V/0.2 V respectively) in pulse mode. More than fifty cycles with on/off ratio up to 1000 was observed. It is notable that the threshold voltages for both on and off states of are low at ± 2 V. Lastly, to demonstrate the non-volatility of the organic memory device, the retention time for PFT2-Fc device was measured and found that the device stably retained the on/off states for several hours. In conclusion, we demonstrated non-volatile organic memory device using ferrocene containing conjugated polymer, PFT2-Fc. The device operated at low driving voltages with high on/off ratio. Although the retention time and the switching cycle are still far from the satisfactory level compared to the current Si technology, the research on organic memory is still in infant stage and its device performance is expected to increase as the methods of the fabrication process improves.
9:00 PM - I3.18
Material Properties of Mixed Polymer and Gold Nanoparticles Structure for Memory Applications
Yan Song 1 , Qidan Ling 2 , Siew Lay Lim 2 , Eric Yeow Hwee Teo 1 , Yoke Ping Tan 1 , En-Tang Kang 2 , Daniel Siu Hung Chan 1 , Chunxiang Zhu 1
1 Electrical and Computer Engineering, National University of Singapore, Singapore Singapore, 2 Chemical and Biomolecular Engineering, National University of Singapore, Singapore Singapore
Show AbstractOrganic materials have been aggressively explored for semiconductor device applications. Very recently, organic memories have received a great attention due to their simple structure, good scalability, CMOS compatibility, and most importantly, low cost. Several kinds of organic materials were found to exhibit memory effects. Of these organic materials, poly (N-vinylcarbazole) (PVK) mixed with gold nanoparticles is a promising candidate due to their simple structure. By using PVK mixed with gold nanoparticles as the active layer, the device showed a good flash-typed memory performance. Till now, the research about the effect of mixing ratio of PVK to gold nanoparticle on the material property is still absent, which makes it difficult to fully understand the mechanism of memory behavior. In this paper, we present a study of the material properties (such as optical, physical and electrical properties) of mixed PVK/gold nanoparticles thin films with various mixing ratio. By using different characterization tools, we shall understand the effect of the mixing ratio of PVK to gold nanoparticles on the material properties.
9:00 PM - I3.2
Memory Effect in Ferroelectric PVDF Copolymer Integrated MOS Structure for Nondestructive Readout Memory Devices.
Sang-Hyun Lim 1 , Rastogi Alok 1 , Seshu Desu 1
1 Electrical and Computer Engineering, Univ. of Massachusetts, Amherst , Massachusetts, United States
Show Abstract9:00 PM - I3.3
Nonvolatile Memory Characteristics of Si-nanocrystal Floating-gate MOSFETs Fabricated by Using 0.5 μm CMOS Standard Processes.
Min Choul Kim 1 , Yong Min Park 1 , Sung Kim 1 , Suk-Ho Choi 1 , Kyung Joong Kim 2
1 College of Electronics and Information, Kyung Hee University, Yongin, Kyungkido, Korea (the Republic of), 2 Division of Advanced Technology, Korea Research Institute of Standards and Science, Taejon Korea (the Republic of)
Show Abstract9:00 PM - I3.4
Silicon Nanocluster Formation by a Pulse-type Gas Feeding Technique in the LPCVD System for the Nonvolatile Memory Applications.
Kyongmin Kim 1 , Eunkyeom Kim 1 , Myeongwook Bae 2 , Daeho Son 1 , Juhyung Lee 1 , Moonsup Han 2 , Junghyun Sok 1 , Kyoungwan Park 1
1 Dept. of Nano Science and Technology, University of Seoul, Seoul Korea (the Republic of), 2 Dept. of Physics, University of Seoul, Seoul Korea (the Republic of)
Show Abstract9:00 PM - I3.5
The Optical and Electrical Properties of SiOx (x<2) Thin Films Prepared by Pulsed Laser Deposition Technique.
Byoung Youl Park 1 , Sol Lee 1 , Chang Hyun Bae 2 , Seung Min Park 2 , Kyoungwan Park 1
1 Dept. of Nano Science and Technology, University of Seoul, Seoul Korea (the Republic of), 2 Dept. of Chemistry, Kyung Hee University, Seoul Korea (the Republic of)
Show Abstract9:00 PM - I3.6
Nonvolatile Memory Device Based On Nanoparticle Functionalized Tobacco Mosaic Virus.
Chunglin Tsai 1 , Ricky Tseng 2 , Liping Ma 2 , Yang Yang 2 , Cengiz Ozkan 3
1 Electrical Engineering, University of California Riverside, Riverside, California, United States, 2 Material Science and Engineering, University of California Los Angeles, Los Angeles, California, United States, 3 Mechanical Engineering, University of California Riverside, Riverside, California, United States
Show AbstractNanostructured protein shelled viruses are attractive templates in ordering quantum dots for constructing self-assembled building blocks towards next generation electronic devices.1 So far, only a few examples of electronic devices have been fabricated from biomolecules due to the lack of charge transport through biomolecular junctions. Here, we report a novel electronic memory effect by incorporating platinum nanoparticles over Tobacco Mosaic Virus templates. The recorded memory effect is based on conductance switching which leads to the formation of bistable states with an on/off ratio larger than three orders of magnitude. The mechanism of this process is attributed to charge trapping in the nanoparticles for data storage and a tunneling process in the high conductance state. Such hybrid bio-inorganic nanostructures are promising for applications in nanoelectronics.
9:00 PM - I3.7
A Low-voltage-operative Nanocrystal Memory Made with High-k Control Oxide.
Chen Chan Wang 1 , Chun-Sheng Liang 1 , Jiun-Yi Tseng 1 , Tai-Bor Wu 1
1 Materials Science and Engineering, National Tsing Hua University, Hsinchu Taiwan
Show Abstract9:00 PM - I3.8
Deposition of Uniform Size Metallic Nanoparticles for use in Non Volatile Memories
Emanuele Verrelli 1 , Dimitris Tsoukalas 1 , Konstantinos Giannakopoulos 2 , Dimitris Ioannou 3
1 Physics, National Technical University of Athens, Athens, Attikis, Greece, 2 Institute of Material Science, NCSR Demokritos, Aghia Paraskevi, Attikis, Greece, 3 Electrical Engineering, George Mason University, Fairfax, Virginia, United States
Show AbstractAn important issue in nanocrystal memories that is still remaining open it is the control of size and density uniformity of the nanoparticle layer. Especially for metallic nanoparticles the existing methods which rely on the deposition of a thin metal film and subsequent annealing to form the nanoparticles result in uncontrolled size distribution. In this work we are presenting results on the formation of nickel nanoparticles on a thin tunneling thermal SiO2 layer using a new nanoparticle manufacturing technique. The technique is based on a physical vacuum deposition process. Particles are generated using a high-pressure magnetron sputtering device and carried away from the target area by the discharge gas into a condensation zone where nanoparticles are grown. The nanoparticles after being swept through this zone enter the chamber through a final aperture and they are soft-landed on the oxide surface. This way room temperature formation of nanoparticles becomes possible under high purity vacuum conditions. Nanoparticles with size distributions of ±20% and density distributions that can vary between 10^10 cm-2 and 10 ^12 cm-2 are formed. Minimum achieved size of the nanoparticles is 2 nm and maximum size 14 nm by proper variation of process parameters. After analysis of the above results which have been obtained by Transmission Electron Microscopy imaging, we have realized two terminal devices by depositing a control oxide (HfO2) and a patterned metal electrode over the nanoparticle layer. The non volatile memory properties of the structure were then monitored by electrical measurements and correlated with size and surface density distribution of the nanoparticles.
9:00 PM - I3.9
Characteristic of Tellurium films by Remote Plasma Atomic Layer Deposition
Do-Heyoung Kim 2 3 , Hun Jung 1 3 , Yeon-Hong Kim 1 3 , June-Key Lee 4
2 School of Applied Chemical Engineering, Chonnam National University, Kwangju Korea (the Republic of), 3 BK21 Division of Functional nano-novel chemical materials, Chonnam National University, Kwangju Korea (the Republic of), 1 Department of Fine Chemical Engineering, Chonnam National University, Kwangju Korea (the Republic of), 4 School of Materials Science & Engineering, Chonnam National University, Kwangju Korea (the Republic of)
Show AbstractTellurium(Te) films were prepared on TiN/Si and SiO2/Si substrates by remote plasma assisted atomic layer deposition (RPALD). The effects of process parameters, such as deposition temperature, plasma power, plasma pulse time, reactant gas composition, purge pulse time on the characteristics of the films were investigated. Precursor used for tellurium deposition is di-isopropyl-tellurium, [Te(C3H7)2], and hydrogen / argon gases were used as activated reactant. The vapor pressure of tellurium precursor at room temperature were found to be high enought for ALD in this work. Tellurium films were deposited at 423 ~ 573 K, deposition pressure of 1 Torr, plasma power of 250 W. The characteristics of the deposited films were characterized by using the following techniques : The thickness and crystallinity of the films was determinded by x-ray reflectivity (XRR) and x-ray diffraction (XRD), respectively. The cross-section of the films was observed by a field-emission scanning electron microscope (FESEM) and the surface morphology was investigated by atomic force microscopy (AFM) in contact mode under air atmosphere. A chemical composition of the film was obtained by depth profile of auger electron spectroscopy (AES). Also, the reaction mechanism involving tellurium RPALD was investigated by using gas-chromatorgraphy mass spectroscopy (GC-MS).
Symposium Organizers
Tingkai Li Sharp Laboratories of America, Inc.
Yoshihisa Fujisaki Hitachi Ltd.
Jon Slaughter Freescale Semiconductor, Inc.
Dimitris Tsoukalas National Technical University
I4: Resistive Switching Non-volatile Memories I
Session Chairs
Wednesday AM, April 11, 2007
Room 3006 (Moscone West)
9:30 AM - **I4.1
RRAM electronics and Switching Mechanism
ShengTeng Hsu 1 , Tingkai Li 1
1 5, Sharp Laboratories of America, Camas, Washington, United States
Show AbstractThere are several mechanisms proposed to explain the pulse induced resistance change in RRAM resistor. Those models are unable to explain the uni-polar switching of the memory resistors. All as-symmetrical RRAM devices we fabricated showed bipolar as well as uni-polar switching properties. All symmetrical RRAM devices we fabricated exhibit unipolar switching property. For uni-polar switching a narrow pulse caused the resistance to increase while a wider pulse having the same polarity reduces the resistance of the devices. We studied the temperature dependent on resistance, charge transport property, frequency dependent of RRAM impedance, resistivity distribution, and dynamic property of the memory resistor. The experimental data indicated the resistivity is reduced by high electric field. The data also clearly show that a narrow pulse caused an electron packet injection from cathode into the RRAM resistor. When the density of the non-equilibrium electron is larger then the certain value the resistivity near the cathode increases. The injected electron packet corrupts when the pulse width is much wider than the lifetime of the electron packet. Therefore, the RRAM resistance cannot be increased with wider pulse. This leads to the conclusion that the high resistivity is due to the reduction of free valence electron density caused by the high density of non-equilibrium electrons, the well known Jahn-Teller effect. A large non-equilibrium electron density may also be induced at the virtual cathode when the space-charge limited current (SCLC) flow occurs in the RRAM resistor. This also increases the resistivity at the virtual cathode region. Since the charge packet at the virtual cathode of a SCLC flow does not corrupt with time the resistivity can be increased statically via the SCLC flow process.
10:00 AM - I4.2
Direct Observation of Conducting Filament of a Few Nanometer Sizes in NiO Thin Film by Conducting Atomic Force Microscopy Under High Vacuum Condition.
Sejin Kim 1 , Jung-Bin Yun 1 , Changdeuck Bae 1 , Sunae Seo 2 , Myoung-Jae Lee 2 , Dong-Chul Kim 2 , Seung-Eon Ahn 2 , In-Kyeong Yoo 2 , Hyunjung Shin 1
1 School of Advanced Materials Engineering, Kookmin University, Seoul Korea (the Republic of), 2 Semiconductor Device & Material Lab., Samsung Advanced Institute of Tech., Seoul Korea (the Republic of)
Show Abstract10:30 AM - I4.4
Electrode Influence on the Resistive Switching at SrRuO3/Cr-doped SrZrO3/metal Junctions.
Hwan-Soo Lee 1 , Sukwon Choi 2 , Paul Salvador 2 , James Bain 1
1 Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States, 2 Materials Science and Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania, United States
Show Abstract10:45 AM - I4.5
Nonvolatile Resistive Switching Devices Based on Nanoscale Metal/Amorphous Silicon/Crystalline Silicon Junctions
Sung Hyun Jo 1 , Wei Lu 1
1 EECS, University of Michigan, Ann Arbor, Michigan, United States
Show AbstractConventional micron-scale Metal/a-Si/Metal based nonvolatile resistive switching devices have the advantages of high on/off resistance ratio, full CMOS compatibility, and only rely on simple fabrication processes and relatively inexpensive material. However, the high voltage forming process typically required in such devices lowers the device yield, and it is not clear whether a-Si based resistive switching devices can be scaled down to nanoscale. Here we report studies on nanoscale metal/a-Si/c-Si devices in which forming is better controlled by using a heavily doped substrate as the bottom contact material. Devices based on the metal/a-Si/c-Si structure retain all the benefits of conventional amorphous silicon based devices. The a-Si layer sandwiched between a metal layer and the crystalline silicon substrate can be switched reversibly between the high resistance state and the low resistance state by controlling the magnitude and the polarity of the applied voltage. a-Si was prepared by decomposition of silane (Si3H4) either by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) on a heavily doped p-type silicon substrate. Silver, gold and nickel were explored as the top metal electrode. The devices show improved on/off resistance ratio as the device size is scaled down. A device with 50×50 nm^2 active area exhibits similar on-current compared with a device with 30×30 um^2 active area, and 10^6 better on/off ratio, demonstrating excellent scaling capability. Unlike conventional micron-scale metal/a-Si/metal structures, metal/a-Si/c-Si structure does not require high voltage forming, and high device yield (>98%) can be readily obtained. The switching behavior can be further controlled to be either rectifying or non-rectifying such that at on-state the device can be modeled as either a resistor or a diode, adding functionalities at the circuit level. Very promising properties for nonvolatile memory applications were observed, including, on/off resistance ratio larger than 4 orders of magnitude, endurance cycle larger than 10^6, switching speed faster than 5 ns and retention time longer than 70 days without noticeable degradation of the stored data. Such nanoscale CMOS compatible resistive switching devices will be ideally suited as next generation, high-density non-volatile memory devices, and may be used in logic operations based on the cross-bar architecture.
11:00 AM - I4: RRAM I
BREAK
12:00 PM - I4.7
Coexistence of Bipolar and Unipolar Resistive Switching Behavior in a Pt/TiO2/Pt Thin Film Stack.
Doo Seok Jeong 1 , Herbert Schroeder 1
1 Institute of solid state research, Research center Juelich, Juelich, NRW, Germany
Show Abstract12:15 PM - I4.8
New Nonvolatile Memory Effect Showing Reproducible Large Resistance Ratio Employing Nano-gap Gold Junction.
Yasuhisa Naitoh 1 2 , Masayo Horikawa 1 , Tetsuo Shimizu 1
1 NRI, AIST, Tsukuba Japan, 2 , PRESTO-JST, Kawaguchi Japan
Show Abstract Recent research reports have described resistance switches using nanoscale spaces. Most switches are composed of organic molecules possessing a switching effect sandwiched between two metal electrodes, which consist of a great variety of materials, for example, conductive organic wires, carbon nanotubes, or amorphous carbon. Also, K. Terabe et al. have reported atomic switches that employ solid-state electrochemical reactions between Pt electrodes and AgS or CuS. (Terabe et al., Nature, (2005) 433, 47-50.) These atomic switches employ absolutely no physical charge, such as electric charge or magnetization, and therefore they appear to be the ultimately small resistance switches. With the exception of magnetic random access memory, the miniaturization of memory devices generally results in an improvement of the switching speed and operation power, but the lifetime for maintaining the signals tends to shorten. The long lifetime of an atomic switch is maintained even when the device is miniaturized, because there is no diffusion of physical charges. This atomic switch technology will be the basis to realize nonvolatile memory devices for the next generation.In this study, we observed a reversible resistance switching effect in a structure composed of metal electrodes separated by about a 10 nm gap. (Y. Naitoh et al, Nanotechnology (2006) in press.)The structure of the device shown here is relatively simple, requiring no molecules having complicated structures or special combinations of materials, but just simply consisting of Au electrodes on a SiO2-coated Si substrate. A large negative resistance is observed in the I-V characteristics of this junction when high-bias voltages are applied. This phenomenon is characteristic behaviour on the nanometre scale. Furthermore, this junction exhibits a non-volatile resistance hysteresis when the bias voltage is reduced very rapidly from a high level to around 0 V, and when the bias voltage is reduced slowly. The high and low resistance conditions were performed by the rapid and slow reductions of applied bias voltages, respectively. The maximum resistance ratio between high and low resistance was over six orders of magnitude.This study is the first to describe a reversible resistance switching effect occurring across a nanogap between metal electrodes. It has been shown that this effect is peculiar to gaps on the nanometre scale, dependent on the gap width, and that its mechanism is speculated by the reversible migration of gold atoms. The resistance switching ratio can be adjusted by controlling the applied voltage, where it can tolerate over 1,000 cycles. Due to the simplicity of the construction of this device, it appears that this device has great potential for future application in nonvolatile memory and other information storage devices.
12:30 PM - I4.9
Nonvolatile Memory Effects of Ti Oxide Thin Films by a Plasma-enhanced Atomic Layer Deposition.
Min Ki Ryu 1 , Hu Yonng Jeong 1 , Lee-Eun Yu 2 , Yang-Kyu Choi 2 , Sung-Yool Choi 1
1 Nano-Bio-Electronic Devices Team, ETRI, Daejeon Korea (the Republic of), 2 Dept. of Electrical Engineering and Computer Science, KAIST, Daejeon Korea (the Republic of)
Show AbstractI5: Resistive Switching Non-volatile Memories II
Session Chairs
Wednesday PM, April 11, 2007
Room 3006 (Moscone West)
2:30 PM - **I5.1
Memory Devices Based on Solid Electrolytes.
Michael Kozicki 1
1 Center for Applied Nanoionics, Arizona State University, Tempe, Arizona, United States
Show AbstractThe semiconductor industry has acknowledged that it faces ever-increasing difficulty in attaining the goals set forth in the International Technology Roadmap for Semiconductors. The Roadmap states that the problems associated with physical and operational scaling are particularly acute for solid state memory, where current mainstream charge storage technologies have a very doubtful existence in anything like their current form as we move beyond the 32 nm node. The scaling quandary has led to an avalanche of alternative memory technologies and particularly of those that rely on resistance change mechanisms. A wide variety of efforts has been highlighted in the technical press but even though investment has been significant in the most promising cases, no new technology has been universally adopted by the industry, mostly due to non-scalable operational characteristics. This has kept the door open for new contenders. One such new technology is resistance change memory based on solid electrolytes. A number of semiconductor companies and research institutions are developing resistance change devices that utilize a variety of solid electrolytes and mobile ions. The lowering of the resistance is attained by the reduction of ions in the relatively high resistivity electrolyte to form a conducting bridge between the electrodes. The resistance is returned to the high value via the application of a reverse bias (or in some cases a high-current forward bias) that results in the breaking of the metallic filament. Our own variant, Programmable Metallization Cell (PMC), uses deposited thin films of copper- or silver-doped germanium sulfide, germanium selenide, tungsten oxide, or silicon oxide between two electrodes; Cu or Ag is used as an oxidizable electrode on the electrolyte and the lower electrode can be the W via plug in a standard CMOS process. Switching is attainable within a few tens of nanoseconds for voltages of a few hundred mV and currents in the μA range. In addition to possessing the endurance, retention, and CMOS compatibility required of future memory and storage elements, solid electrolyte devices have excellent scaling prospects due to their low operational energy and demonstrated physical scalability to below 20 nm. This presentation will review the state-of-the-art in solid electrolyte resistance-change memory devices and will discuss how the process/thermal stability and electrical characteristics of the most promising variants depend on the unique nanostructure of the ion-containing films and the nanoscale electrodeposits that form within them.
3:00 PM - I5.2
Resistance Switching In Ferroelectric Materials.
Tingkai Li 1 , Sheng Teng Hsu 1
1 , Sharp Labs of America, Inc., Camas, Washington, United States
Show AbstractA ferroelectric crystal with perovskite structure such as PbZr1-xTixO3 (PZT), SrBi2Ta2O9 (SBT), Bi3La1-xTixO12 (BLT) and non-perovskite structure such as Pb3Ge5O11 (PGO) have two polarization states, which can generate two resistance states, which are high resistance and low resistance states. These properties can be used for resistance random access memory applications (RRAM). When a ferroelectric capacitor is polarized an internal electric field opposite polarity to the external applied field is generated. As a result there is a large resistance change at a given bias voltage between the two polarization states of the capacitor. It is the purpose of this paper to show that the ferroelectric capacitor may be used as a current memory cell of non-destructive readout (NDRO) non-volatile Random Access Memory array. It will also be shown that each current sensing ferroelectric memory cell stores two bits of memory information and exhibits long memory retention and excellent endurance properties.
3:15 PM - I5.3
Electric Pulse Induced Programmable Resistance Change in Oxide Films
Alex Ignatiev 1 , Naijuan Wu 1 , Xin Chen 1 , Yibo Nian 1 , Christina Papagianni 1 , John Strozier 1
1 Center for Advanced Materials, University of Houston, Houston, Texas, United States
Show AbstractRecent research on the electric-pulse-induced resistance (EPIR) switching effect in manganite oxide devices is being reviewed. The EPIR effect encompasses the reversible change of resistance of a thin oxide film such as Pr1-xCaxMnO3 (PCMO) under the application of short, low voltage pulses. Positive voltage pulses of < 4V can switch the resistance of the thin film oxide device from a high resistive state into a low resistive state, and negative voltage pulses can return the system back to the high state in times shorter than ~10ns. A resistance change of more than two orders of magnitude has been obtained for samples pulsed at 3 to 4V, in an operating temperature range of 23 oC to 100 oC. It has been shown that the resistance change is non-volatile with retention times >108sec. Moderate fatigue is exhibited by the effect, however, this seems to depend on film processing parameters. Two groups of EPIR devices have been investigated: one with the PCMO layer sandwiched between a top and a bottom electrode; the other with both electrodes on top of the PCMO thin films, which were grown on insulating substrates. I-V switching characteristics, electric pulse switching hysteresis, as well as the dynamic resistance during nanosecond switching pulses of the EPIR devices were measured in the delimitation of the physical basis for the EPIR effect. Scanning Kelvin Probe and Current (I) AFM measurements have shown resistance switching over extended regions from the metal electrode-oxide film interface, with data pointing to enhanced and reversible diffusion of oxygen ions (vacancies) in these extended regions under pulsing conditions. The device performance indicates that a two–state non-volatile resistance random access memory (RRAM) can be realized based on this EPIR effect. This would present the possibility of a new nonvolatile, high density, fast write/read, and low power-consumption memory system.
3:30 PM - I5.4
Scanning Resistive Probe Microscopy: A New Electric Field Sensor as R/W Head for Non-volatile Storage Devices.
Kyunghee Ryu 1 , Hyunjung Shin 1 , Hyoungsoo Ko 2 , Seungbum Hong 2 , Chulmin Park 2 , Yongkwan Kim 2 , Sung-Hoon Choa 2 , Ho Nyung Lee 3
1 School of Advanced Materials Engineering, Kookmin University, Seoul Korea (the Republic of), 2 Semiconductor Device and Material Lab, Samsung Advanced Institute of Technology, Kyunggi-do Korea (the Republic of), 3 Condensed Matter Sciences Division, Oak Ridge National Laboratory, Oak Ridge, Tennessee, United States
Show Abstract3:45 PM - I5.5
Femtosecond Laser Structuring of As2S3 Glass for Erasable and Permanent Optical Memory.
Andrei Rode 1 , Saulius Juodkazis 2 , Toshiaki Kondo 2 , Hiroaki Misawa 2 , Eugene Gamaly 1 , Marek Samoc 1 , Barry Luther-Davies 1
1 Laser Physics Centre, RSPhysSE, The Australian National University, Canberra, Australian Capital Territory, Australia, 2 Nanotechnology Center, Hokkaido University, Sapporo Japan
Show Abstract4:00 PM - I5: RRAM II
BREAK
I6: Ferroelectric Non-volatile Memories I
Session Chairs
Wednesday PM, April 11, 2007
Room 3006 (Moscone West)
4:30 PM - **I6.1
ITO-Channel Ferroelectric-Gate Thin Film Transistor with Large On/off Current Ratio.
Eisuke Tokumitsu 1 , Tomofumi Fujimura 1 , Takashi Sato 1
1 Precision and Intelligence Lab, Tokyo Institute of Technology, Yokohama Japan
Show Abstract5:00 PM - I6.2
No Interfacial Layer for PEDOT Electrodes on PVDF:Characterization of Reactions at the Interface P(VDF/TrFE)/Al and P(VDF/TrFE)/PEDOT:PSS.
Klaus Mueller 1 , Dipanka Mandal 1 , Dieter Schmeisser 1
1 , BTU Cottbus, Cottbus Germany
Show Abstract5:15 PM - I6.3
Large Ferroelectricity of Thin Poly (vinylidene fluoride-trifluoroethylene) Copolymer Films Suitable for Non-Volatile Memory Applications
Sumiko Fujisaki 1 , Yoshihisa Fujisaki 2 , Hiroshi Ishiwara 1
1 Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama Japan, 2 Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo, Japan
Show Abstract Organic ferroelectrics such as Poly vinylidene fluoride (PVDF) are promising material for next generation ferroelectric random access memories (FeRAMs) due to lower processing temperatures. PVDF was the first found organic material that exhibited significant piezoelectric and ferroelectric properties [1]. The challenges to make ferroelectric non-volatile memories with PVDF related materials had begun in 1990s but most of the activities faced with a serious problem in reducing operating voltages. There are two reasons that make the operating voltages great; one is the thickness of the ferroelectric films, and the other one is large coercive field (Ec). In most cases, thickness of films was greater than several hundred nanometers and Ec was larger than 400 kV/cm. In this paper, we tried to reduce the film thickness by introducing trifluoroethylen (TrFE). We optimized the composition of VDF and TrFE first, and then we investigated the dependence of ferroelectricity on the crystallization condition. We prepared P(VDF-TrFE) (Poly vinylidene fluoride-trifluoroethylene) copolymer films with solvent cast process on Pt and Si substrates. Three compositions of VDF/TrFE = 77/23 mol%, 70/30 mol% and 57/43 mol% were tried. The deposited films were at first dried at 120 °C in air. The spin-coating and drying processes were repeated until the appropriate film thickness was obtained. The films were crystallized at temperatures around 140 °C. By optimizing the growth conditions, the maximum remanent polarization (Pr) of 8.6 µC/cm2 was obtained in a 60 nm-thick film. The coercive voltage and field of that ferroelectric capacitor were 1.5 V and 250 kV/cm, respectively. We also fabricated Au/100nm-P(VDF-TrFE)/TaO/Si MFIS (Metal Ferroelectric Insulator Semiconductor) structure. The memory window larger than 2.8 V was observed under the sweep bias of ± 4 V. These sophisticated ferroelectric properties are equivalent to those of oxide ferroelectrics and are much advanced compared to the previous reports on organic ferroelectrics.References[1] H. Kawai, Jpn. J. Appl. Phys., vol.8, pp.975-97 (1969).
5:30 PM - I6.4
Oxygen Bonding in Bismuth Layered Compounds SrBi2Ta2O9.
Dong Su 1 , Nan Jiang 1 , Jianguo Wen 2 , Jianshe Liu 3
1 Department of Physics, Arizona State Universtiy, Tempe, Arizona, United States, 2 Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, Urbana, Illinois, United States, 3 Institute of Microelectronics, Tsinghua University, Beijing China
Show Abstract5:45 PM - I6.5
Dielectric Characteristics of Donor Doped Nonlead Ba(Cu1/3Nb2/3)O3 Perovskite Material Synthesized by Microwave-assisted Citrate-nitrate Sol-gel Route.
Alp Manavbasi 1 , Jeffrey LaCombe 1
1 Materials Science & Engineering, University of Nevada, Reno, Reno, Nevada, United States
Show AbstractI7: Poster Session: Resistive Switching and Ferroelectric Memories I
Session Chairs
Tingkai Li
Eisuke Tokumitsu
Thursday AM, April 12, 2007
Salon Level (Marriott)
9:00 PM - I7.1
Metal Organic Chemical Vapor Deposition of Titanium Dioxide Thin Films for Applications of Resistive Switching Characteristics.
Ying-Ching Zhang 1 , Yun-Shan Lo 1 , Tai-Bor Wu 1
1 Materials Science and Engineering, National Tsing-Hua University, Hsin-Chu Taiwan
Show AbstractThe resistive switching mechanism of TiO2 crystalline thin films grown on Pt/Ti substrate by MOCVD is studied by current-voltage measurement(sweep mode, HP4155). The anatase structure of TiO2 thin films is obtained at low temperature of 335∼375°C, which is useful for non-volatile memory device of industrial applications. The titanium dioxide(binary transition metal oxide)MIM structure is fabricated by sputtering Pt as top electrode of diameter 300μm at room temperature. The crystalline structure and surface uniformity of TiO2 thin films were investigated by x-ray diffraction(low angle XRD), field-emission scanning electron microscopy(FE-SEM), transmission electron microscopy(TEM)and x-ray photoelectron spectroscopy(XPS). Furthermore, the switching phenomenon shows a voltage-controlled N-shaped negative resistance characteristic consistent with the theory of conducting filamentary current composed of oxygen ions in the TiO2 thin film.
9:00 PM - I7.11
The Microstructure and C-V Characterization for Lanthanum-doped Bi4Ti3O12 Ferroelectric Memory Capacitors Based on MFS and MFIS Structures
Dan Xie 1 , Tianling Ren 1 , Litian Liu 1
1 , Institute of Microelectronics, Tsinghua University, Beijing China
Show Abstract9:00 PM - I7.12
Preferred Orientation Control and Electrical Properties of Sputtered BiFeO3 Thin Films.
Chia-Ching Lee 1 , JennMing Wu 1
1 , National Tsing Hwa Unervisty, Taiwan, R.O.C., Hsinchu Taiwan
Show Abstract9:00 PM - I7.13
Reversible Multi-level Resistance Switching of Ag-La0.7Ca0.3MnO3-Pt Heterostructures.
Dashan Shang 1 2 , Lidong Chen 1 , Qun Wang 1 , Zihua Wu 1 , Wenqing Zhang 1 , Xiaomin Li 1
1 , Shanghai Institute of Ceramics, CAS, Shanghai China, 2 , Graduate School of Chinese Academy of Sciences, Beijing China
Show AbstractWednesday, April 11Transferred I4.3 @ 9:15 am to Poster I7.13Reversible Multi-level Resistance Switching of Ag-La0.7Ca0.3MnO3-Pt Heterostructures. Dashan Shang
9:00 PM - I7.14
Optical, Structural and Surface Properties of Silicon Dioxide Films Doped with Terbium.
Zhe Feng 1 , S. Lien 1 , C. Huang 1 , L. Cheng 1 , P. Huang 1 , Ting Li 2
1 Electrical Engineering, National Taiwan University , Taipei Taiwan, 2 , Sharp Labs of America, Inc., Camas, Washington, United States
Show AbstractWednesday, April 11Transferred I4.10 @ 11:45 am to Poster I7.14Optical, Structural and Surface Properties of Silicon Dioxide Films Doped with Terbium. Zhe Chuan Feng
9:00 PM - I7.3
Effects of SrRuO3 Buffer Layers in Enhancing Resistance Change of Ag/Pr0.7Ca0.3MnO3/Pt Heterostructure.
Seungwoo Han 1 , Junghyun Sok 1 , Kyungwan Park 1 , Wanshik Hong 1 , Sanghyun Joo 1 , Yunsun Park 2
1 Department of Nano Science and Technologies, Univ. of Seoul, Seoul, Seoul, Korea (the Republic of), 2 Department of Industrial and Systems Engineering, Myongji university, Yong-in, kyunggi-do, Korea (the Republic of)
Show Abstract9:00 PM - I7.4
HfOx Thin Films for Resistive Memory Device by Use of Atomic Layer Deposition.
Pang Shiu Chen 1 , Heng-Yuan Lee 2 , Ching-Chiun Wang 2 , Ming-Jinn Tsai 2 , Kou Chen Liu 3
1 Materials Science and Engineering, MingShin University of Science and Technology, Hsin Chu Taiwan, 2 Electronics and Optoelectronics Research Laboratory, Industrial Technology Research Institute, HsinChu Taiwan, 3 Graduate Institute of Electro-Optical Engineering, Chang Gung University, Taoyuan Taiwan
Show Abstract9:00 PM - I7.5
Characteristics of (Pr,Ca)MnO3 Thin Films on LaNiO3-electrodized Si Substrate for Nonvolatile Resistance Random Access Memory(RRAM) Application
Cheng-Wei Wu 1 , Wen-Yuan Chang 1 , Tai-Bor Wu 1
1 , National Tsing-Hua University, Hsinchu Taiwan
Show Abstract9:00 PM - I7.6
Study of Effect of Metal/semiconductor Interfaces Properties on Resistance Switching Device.
M. Villafuerte 1 , G. Juarez 1 , Silvia Heluani 1 , G. Braunstein 3 , D. Comedi 2 , F. Golmar 4
1 Dto. de Física, Universidad Nacional de Tucuman, Tucuman, San Miguel de Tucuman, Argentina, 3 , University of Central Florida, Orlando, Florida, United States, 2 , CONICET, Tucumán Argentina, 4 , Universidad de Buenos Aires, Buenos Aires Argentina
Show Abstract9:00 PM - I7.7
Influence of Bottom Electrode on the Characteristics of PrCaMnO Thin Film
Young-Sun Kim 1 , Sung-Geun Kang 1 , Seung-Won Lee 1 , Won-Jun Lee 1
1 Department of Advanced Materials Engineering, Sejong University, Seoul Korea (the Republic of)
Show Abstract9:00 PM - I7.8
Reproducible Resistance Switching in Ni/NiO/Ni Trilayer.
Hisashi Shima 1 , Fumiyoshi Takano 1 , Hiro Akinaga 1 , Isao Inoue 2 , Hide Takagi 2 3
1 Nanotechnology Research Institute, National Institute of Advanced Industrial Science and Technology, Tsukuba, Ibaraki, Japan, 2 Correlated Electron Research Center, National Institute of Advanced Industrial Science and Technology, Tsukuba, Ibaraki, Japan, 3 Department of Advanced Materials, University of Tokyo, Kashiwa, Chiba, Japan
Show Abstract9:00 PM - I7.9
A Proposal of a Parallel Resistance Model for the Conduction Mechanism of Binary Transition Metal Oxide ReRAM.
Kentaro Kinoshita 1 , Yuichi Yamazaki 1 , Hideyuki Noshiro 1 , Takashi Iizuka 1 , Chikako Yoshida 1 , Yoshihiro Sato 1 , Masaki Aoki 1 , Yoshihiro Sugiyama 1
1 , Fujitsu Laboratories Ltd., Atsugi, Kanagawa, Japan
Show Abstract
Symposium Organizers
Tingkai Li Sharp Laboratories of America, Inc.
Yoshihisa Fujisaki Hitachi Ltd.
Jon Slaughter Freescale Semiconductor, Inc.
Dimitris Tsoukalas National Technical University
I8: Ferroelectric Non-volatile Memories II
Session Chairs
Xu Jianbin
Eisuke Tokumitsu
Thursday AM, April 12, 2007
Room 3006 (Moscone West)
9:45 AM - **I8.1
Ferroelectric Thin Films Investigated by Piezoresponse Force Microscopy.
Huizhong Zeng 1 2 , S. Lu 1 , J. Liu 1 , W. Huang 1 , Y. Li 1 , Jianbin Xu 2 , H. Guo 2
1 State Key Laboratory of Electronic Thin films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu China, 2 Department of Electronic Engineering, and Materials Science and Technology Research Center, The Chinese University of Hong Kong, Hong Kong China
Show AbstractIn this presentation, we report on the study of domain evolution of the strained epitaxial BaTiO3 thin films near ferroelectric-paraelectric phase transition by in-situ variable-temperature peizo-response force microscopy (PFM), and the development of piezoresponse spectroscopy.BaTiO3 thin films grown on (001) SrTiO3 single crystal substrate covered by a conducting (001) LaNiO3 layer were fabricated by pulse laser ablation (PLD). Microstructure and strains of BaTiO3 thin films were well characterized by x-ray diffraction methods, including θ-2θ scan, φ-scan and high resolution reciprocal space mapping (RSM). The RSM measurement indicates that the BaTiO3 thin film suffers anisotropic strains of εa-axis = 1.3×10-3 and εb-axis = 0.2×10-3 respectively. Two important transitions were identified from PFM measurements at the temperature ranging from 25 °C to 240 °C. One is the transition between a-domains and c-domains. The fraction of the population of a-domains begins to decrease at about 130 °C. The other is the ferroelectric-paraelectric transition which occurs at TC ~ 200 °C. The piezoresponse that is approximately proportional to polarization decreases gradually when the temperature approaching to TC and shows a second-order characteristics near TC, that is, there is a power law for the temperature and the average measured piezoresponse (PR) at the selected a-domains (PR2 ~ τ = (TC - T) /TC). All these features are different from the first-order characteristics of BaTiO3 bulks. The enhancement of TC and transition between a-domains and c-domains manifest the role of anisotropic strain in the ferroelectric epitaxial thin films.Meanwhile, we introduce a method to investigate the domain stability issue based on piezoresponse microscopy. The switching and back-switching processes of sol–gel derived (Pb0.76Ca0.24)TiO3 thin films were investigated by comparing the local piezoelectric hysteresis loops in continuous mode and pulse mode. It was found that the local hysteresis loops acquired by the pulse mode in shorter pulse width were dominated by the back-switching process while the continuous mode piezoelectric hysteresis loop provides information on the domain switching process.
10:15 AM - I8.2
Comparative Study of Pb(Zr,Ti)O3/Electrode Interface Layer Engineering of Ferroelectric Random Access Memory Capacitors with Pt and IrO2 Top Electrodes
Ye (Mike) Chen 1 , Paul McIntyre 1
1 , Stanford University, Stanford, California, United States
Show AbstractFerroelectric fatigue, imprint and opposite-state retention failure are important phenomena that limit the reliability of ferroelectric random access nonvolatile memories (FeRAM / FRAM). Recent reports have suggested that these processes may be caused, at least in part, by the presence of a nonferroelectric interface layer (passive layer) between the ferroelectric film and the electrode. Conductive oxide electrode such as IrO2 has shown to improve reliability. In this presentation, we report a systematic comparison study of the effects of modifying the Pb(Zr,Ti)O3(PZT)/top electrode interface of thin film ferroelectric capacitors with IrO2 and Pt top electrodes. X-ray photoemission spectroscopy (XPS) determined that there is a Pb-rich surface layer approximately one nanometer thick in as grown metalorganic chemical vapor deposited PZT film. Dilute aqueous nitric etch was used to remove the excess Pb prior to top electrode deposition. In-situ XPS analyses showed that, in case of the Pt electrode system, Pb from the PZT reacts with the Pt, creating a Ti/Zr-rich interface layer in samples that underwent the nitric etch. Consistent with the XPS results, electrical measurements showed decreased steady state leakage, stretch-out of the hysteresis loop of nitric acid-treated samples as well as inferior polarization switching reliability. Identical PZT capacitors with IrO2 top electrode exhibited improved voltage cycling fatigue reliability and hysteresis loops. Interpretation of these results based on the chemical stability of the PZT/electrode interface will be discussed.
10:30 AM - I8.3
Nanosecond Separation of Domain Nucleation and Propagation in Thin Ferroelectric Films.
Alexei Grigoriev 1 , Rebecca Sichel 1 , Dal-Hyun Do 1 , Dong Min Kim 1 , Chang-Beom Eom 1 , Bernhard Adams 2 , Eric Dufresne 2 , Paul Evans 1
1 , University of Wisconsin-Madison, Madison, Wisconsin, United States, 2 Advanced Photon Source, Argonne National Laboratory, Argonne, Illinois, United States
Show Abstract10:45 AM - I8.4
Nanoscale Ferroelectric Domain Reading and Writing Using High Speed Piezo Force Microscopy for Memory Device Applications.
Ramesh Nath 1 , David Shuman 1 , Ying-Hao Chu 2 , Ramamoorthy Ramesh 2 , Bryan Huey 1
1 Chemical, Materials and Biomolecular Engineering, University of Connecticut, Storrs, Connecticut, United States, 2 Materials Science and Engineering, University of California, Berkeley, Berkeley, California, United States
Show Abstract11:00 AM - I8: FeRAM II
BREAK
11:30 AM - **I8.5
Recent Researches for Realizing High-Density Ferroelectric Memories
Hiroshi Ishiwara 1
1 Graduate School of Science and Engineering, Tokyo Institute of Technology, Yokohama, Kanagawa, Japan
Show Abstract In this presentation, ferroelectric materials suitable for realizing high-density 1T1C-type (capacitor type) FeRAM cells are first reviewed. BiFeO3 (BFO) is one of the most promising candidates for realizing future high-density FeRAMs, because the remanent polarization of the thin films is as large as 90 μC/cm2. However, it is difficult to obtain their polarization characteristics at room temperature (RT), because their resistivity and breakdown field are generally low. We prepared BFO thin films on Pt/Ti/SiO2/Si(100) structures using chemical solution deposition and succeeded in improving the leakage current characteristics of BFO films without degrading their ferroelectric properties by substituting Mn or Cr atoms for Fe atoms. Mn substitution improved the breakdown characteristics of the films, although the leakage current density steadily increased with increase of the Mn concentration in the films. Because of the better breakdown characteristics, the leakage current densities in the 3 and 5% Mn-substituted films were lower than that in an undoped BFO film at an applied electric field of 1MV/cm at RT, and thus well saturated hysteresis loops in P-V (polarization vs electric field) characteristics were observed in these films. Next, recent technological progress in another type of FeRAM (FET-type FeRAM), in which data are stored in a single ferroelectric-gate FET, is discussed. We demonstrated that the data retention time of ferroelectric-gate FETs was much improved by use of HfO2-based buffer layers which were inserted between the ferroelectric gate film and Si substrate for preventing interdiffusion of constituent elements. Particular attention was paid to FETs with a Pt/SrBi2Ta2O9/HfO2/Si structure, in which the current on/off ratio was larger than 1000 even after 30 days had elapsed.
12:00 PM - I8.6
Conduction Mechanisms of BiFeO3 Thin Films.
Hao Yang 1 , M. Jain 1 , B. Kang 1 , Y. Li 1 , R. DePaula 1 , Q. Jia 1
1 , Los Alamos National Laboratory, Los Alamos, New Mexico, United States
Show Abstract12:15 PM - I8.7
Investigation of Magnetic Behaviour of Mechanical Activation Derived Multiferroic BiFeO3
Ashish Garg 1 , Thota Harikishan 1 , Brajesh Pandey 2 , Harish Verma 2
1 Department of Materials and Metallurgical Engineering, Indian Institute of Technology Kanpur, Kanpur, U.P., India, 2 Department of Physics, Indian Institute of Technology Kanpur, Kanpur, U.P., India
Show Abstract12:30 PM - I8.8
Sol-gel Synthesis and Characterization of Multiferroic BiFeO3-PbTiO3 Thin Films
Soumya Kar 1 , Anju Dixit 2 , Ashish Garg 1 , D. Agrawal 2
1 Department of Materials and Metallurgical Engineering, Indian Institute of Technology Kanpur, Kanpur, 0, India, 2 Materials Science Programme, Indian Institute of Technology Kanpur, Kanpur, U.P., India
Show AbstractIn this work, we report on the synthesis and characterization of thin films of (BiFeO3)1-x-(PbTiO3)x (BFPT) solid solutions of compositions at and around morphotropic phase boundary (MPB) grown on platinized silicon (111) Pt/Ti/SiO2/Si substrate by sol-gel spin coating technique. The films were annealed at various temperatures upto 750°C in air. Morphological analysis of the films was carried out by scanning and atomic force microscopy. Grazing incidence X-ray diffractometry revealed the perovskite structure of the films and peaks suggested on the presence of pure BFPT structured phase in polycrystalline form. The room temperature dielectric constant (k) and loss (tanδ) at frequency 1 kHz were measured to be ~600 and 0.04 respectively showing that our films have good insulation resistance. Ferroelectric response measured by Radiant Ferroelectric Tester shows the presence of hysteresis behaviour in thin films. I-V measurements showed good leakage characteristics as opposed to results shown in the literature with current densities as low as 10-4 A/cm2.
12:45 PM - I8.9
Biaxial Stress-Induced Domain Wall Motion at Room Temperature in Polycrystalline Lead Zirconium Titanate Thin Films
Ricardo Zednik 1 , Paul McIntyre 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States
Show AbstractLead zirconium titanate (PZT) thin-films are some of the most studied ferroelectric materials, and show particular promise for non-volatile memory applications due to their high polarization, low coercive voltage and low thermal budget. As a ferroelastic material, PZT film deposition and device integration can result in large stresses which affect its ferroelectric and dielectric properties. Nevertheless, these effects in PZT thin-films are not yet fully understood.Wafer curvature methods can be used to impose pure biaxial tensile and compressive stresses on thin-films. This makes it possible to study the isolated effects of biaxial stress on the ferroelastic domains in ultra-fine grained PZT. Electrical measurements, such as capacitance-voltage and polarization-field hysteresis, were conducted as a function of applied stress and complemented with in-situ high resolution synchrotron X-ray diffraction measurements performed at the Stanford Synchrotron Radiation Laboratory. Systematic correlation of synchrotron scattering data with the electrical properties of the films shows that applied biaxial stress results in a marked change in the film’s ferroelastic domain populations at room temperature. The large magnitude changes in ferroelectric and dielectric properties of thin film capacitors are consistent with the observed changes in relative volume fractions of the in-plane (a-axis) and out-of-plane (c-axis) oriented tetragonal PZT domains. This fully-reversible effect is symmetric in both tensile and compressive stress states. Our results, obtained from columnar-structure, fiber-textured PZT thin films, will be compared to reported data for ferroelastic domain wall motion in bulk and epitaxial specimens to assess the influence of PZT crystallite size and sample geometry on this phenomenon.
I9/J7: Joint Session: MRAM Materials and Devices
Session Chairs
Thursday PM, April 12, 2007
Room 3006 (Moscone West)
2:30 PM - **I9.1/J7.1
Advancements In Writing Technology For Dense MRAM
Hiroaki Yoda 1
1 R&D center, Toshiba, Kawasaki Japan
Show AbstractA room temperature TMR discovery made reading signal quite large. MgO barrier made scalability regarding reading easy. However, write selectivity and large write current have been the two major issues. In this paper, write technologies are reviewed and MRAM scalability is discussed.Designs to open the window,called a disturb-robust design have been a main topic.A first disturb-robust design called “toggle switching” was demonstrated in 4Mbit MRAM. In this design, a synthetic storage layer made of anti-ferromagnetic coupled magnets was used and a write sequence was properly set.The window was quite large and solved the first issue. To lower the current while keeping the window open, a synthetic layer made of four magnets and interlayers was proposed. The film growth is the point and is under development.Another disturb robust design using unique MTJ shape was proposed. At a selected state, the magnetization rotates coherently. At a half-selected state, the two curving magnetization configuration is formed in storage layer which resists switching. Then,the window was enlarged. The shape was optimized to have fabrication friendliness. The resultant shape is called “propeller shape". Chip yield of diagnostic arrays with one million MTJs was over 50% and the design was proved. This design led to another success of 16Mbit MRAM demonstration with 1.8V voltage supply and 42.3% array efficiency. The design also lowered the current to 4mA. Another disturb robust design was proposed in which both synthetic storage layer with unbalanced magnets and unique shape were used. This design has borderless write window along word line current. Optimization of the parameter is under development.Another important technology for writing is an electromagnet wire. To enhance the field, soft magnet covers a metal wire on its three sides except the side facing MTJs. An advanced proces technology was developed to make the magnet protrude to right beside the MTJs. At 90 nm node, 4mA write current can generates magnetic field of about 60-100 Oe or larger. Even toough the switching fields are increased to assure the non-volatility of small MTJs, the increase in available field compensates. These write technologies are believed to push MRAM to scale to 256Mbit.Recently, new write principle called spin momentum transfer was demonstrated. The spin polarized current flips the storage magnet. This new principle realizes the potential cell size of 6F^2 if the threshold current density is reduced to 5-10 x10-5 A/cm^2. Summary:There were great advancements in write technology just in three years. These advancements realized 4Mbit and 16Mbit MRAM chip demonstrations and are thought to extend MRAM scalability to 256Mbit. Write efficiency improvements extend the scalability further.ACKNOWLEDGMENT:The authors would like to acknowledge NEDO and NEC for supports and discussions.
3:00 PM - **I9.2/J7.2
Materials and Device Technology of Toggle Magnetic Random Access Memory.
Jason Janesky 1 , N. Rizzo 1 , M. Deherrera 1 , K. Smith 1 , K. Nagel 1 , M. Martin 1 , J. Craigo 1 , J. Sun 1 , J. Slaughter 1 , B. Engel 1 , G. Grynkewich 1 , M. Durlam 1
1 Technology Solutions Organization, Freescale Semiconductor, Chandler, Arizona, United States
Show Abstract3:30 PM - I9.3/J7.3
Thermally Stable and Scalable Magnetic Structure for High Density Magnetic Random Access Memory
Hao Meng 1 , Jian-Ping Wang 1
1 Electrical and Computer Engineering, University of Minnesota, Minneapolis, Minnesota, United States
Show Abstract3:45 PM - I9.4/J7.4
Electrical Study of Ferromagnet Metal Gate MOS Diode: Towards a Magnetic Memory Cell Integrated on Silicon.
Mehdi Kanoun 1 , Rabia Benabderrahmane 1 , Christophe Duluard 1 , Bsiesy Ahmad 1 2 , Claire Baraduc 1 , Nicolas Bruyant 1 , Herve Achard 3 , Antoine Filipe 4
1 SPINTEC, CEA, Grenoble France, 2 , Université Joseph fourrier, Grenoble France, 3 , CEA/LETI, Grenoble France, 4 , Spintron, Marseille France
Show Abstract4:00 PM - I9/J7:MRAMs
BREAK
4:30 PM - **I9.5/J7.5
Manipulating Nanomagnets Using Spin-Transfer Torques.
Dan Ralph 1
1 Physics Department, Cornell University, Ithaca, New York, United States
Show AbstractWhen a spin-polarized current interacts with a magnet, it can transfer spin angular momentum to the magnet and thereby apply a torque. This spin-transfer effect can be used to manipulate the magnetic-moment direction of small magnets much more efficiently than using magnetic fields, so that the mechanism is under investigation to see whether it might provide improved performance for the writing process in magnetic random access memories (MRAM). To enable this application of spin transfer, it will be important both to minimize the current levels needed to produce magnetic switching and and also to understand how the nanomagnet responds to a spin transfer torque so as to make the switching process reproducible.I will describe development of experimental techniques that have allowed us to probe the detailed magnetic dynamics that result from spin-transfer torques in magnetic tunnel junctions and spin-valve devices. We find that spin transfer from a DC current can be used either to produce magnetic reversal between static states or to excite steady-state precessional modes. Time-domain measurements using current pulses show that the switching time as a function of current amplitude follows the form expected from the conservation of angular momentum, and switching times less than 1 ns can be achieved. In the regime of steady-state precession driven by a DC current, we have achieved linewidths comparable to 1 part in 2000 of the precession frequency for nanopillar-shaped devices. We have also used spin-transfer from an AC current, and from combinations of AC and DC currents, to perform ferromagnetic resonance (FMR) measurements of single nanomagnets in magnetic tunnel junctions and spin valves. This enables a detailed characterization of both the fundamental normal mode for precession and higher-order more spatially-nonuniform modes in individual magnetic devices. An analysis of spin-transfer FMR lineshapes provides information about the mechanism behind the spin-transfer torque, and a direct measurement of the damping in a single nanomagnet. I will close by summarizing progress at Cornell in developing spin-transfer devices suitable for non-volatile MRAM elements and also for frequency-tunable nanoscale microwave oscillators.
5:00 PM - I9.6/J7.6
Low-RA MgO Tunnel Junctions for SMT- MRAM
Renu Dave 1 , P. Mather 1 , F. Mancoff 1 , N. Rizzo 1 , B. Butcher 1 , J. Slaughter 1
1 , Freescale Semiconductor, Inc, Chandler, Arizona, United States
Show AbstractSpin momentum transfer (SMT) switching is a candidate programming method that may enable higher density and lower power operation for future magnetic random access memory (MRAM). SMT switching employs a current passing directly through the magnetic tunnel junction (MTJ) bits with a current density high enough for the torque from the spin-polarized tunneling current to switch the free layer. SMT-MRAM requires MTJ material with higher magnetoresistance ratio (MR) and lower resistance than used in the field-switched MRAM currently in production. Here, we report several key properties of high-quality MTJ material and devices with low-RA MgO tunnel barriers. Different oxidation processes were evaluated to fabricate the tunnel junctions with RA in the range of 2-50 Ω-μm2 , including: plasma oxidation, radical oxidation, and natural oxidation of thin Mg layers. A comparison of MTJ material attributes will be given for different oxidation processes, including: MR, RA range, breakdown voltages (Vbd), and the fitted electrical barrier height and width. We also measured the physical barrier width using a novel x-ray reflectivity (XRR) technique and compare it to the electrical barrier width parameter for MgO barriers made with different processes. Surprisingly, the XRR results show an expansion of the layer upon oxidation of metallic Mg, rather than contraction as predicted by bulk density calculations. Expansion factors in the range of 1.06 to 1.17 were measured for different MgO processes. MTJ devices were fabricated on 200 mm Si wafers using optical lithography to form bits with sizes as small as 100 nm X 200 nm. Low-bias MR values upto 120% were obtained in patterned bits with CoFeB free layers with RA~7 Ω-μm2. Quasistatic critical currents of 0.8 mA (5x106 A/cm2) were obtained with thermally-stable bits having a thermal energy barrier of 45kT, corresponding to a zero-temperature critical current density of 1x107 A/cm2.
5:15 PM - I9.7/J7.7
Interfacial Oxide and Barrier Engineering in MgO Based Magnetic Tunnel Junctions.
John Read 1 , Phillip Mather 2 , Robert Buhrman 1
1 , Cornell University, Ithaca, New York, United States, 2 , Freescale Semiconductor, Inc., Chandler, Arizona, United States
Show Abstract5:30 PM - I9.8/J7.8
Defect-Mediated Properties of Magnetic Tunnel Junctions.
Julian Velev 1 , Kirill Belashchenko 1 , Sitaram Jaswal 1 , Evgeny Tsymbal 1
1 Department of Physics, University of Nebraska, Lincoln, Nebraska, United States
Show AbstractMagnetic tunnel junctions (MTJs) have recently attracted considerable interest due to their potential applications in magnetic field sensors and non-volatile magnetic random access memories. Defects play an important role in the properties of metal oxides which are currently used as barrier layers in MTJs. However, so far first-principles models of MTJs have mostly been limited to ideal MTJs. In this work we study the effect of O vacancies on the interlayer exchange coupling (IEC) and tunneling magnetoresistance (TMR) in Fe/MgO/Fe tunnel junctions. First-principles calculations based on density functional theory show that the presence of neutral O vacancies (F centers) affect significantly the IEC. We find that resonant tunneling through the F centers makes the IEC antiferromagnetic for thin barriers but with increasing MgO thickness the resonance contribution to IEC is reduced resulting in the ferromagnetic coupling typical for perfect MgO barriers. This behavior is consistent with the available experimental data. Also we demonstrate that O vacancies have a profound effect on TMR. F centers produce occupied localized s states and unoccupied resonant p states in the gap of MgO. We demonstrate that F centers affect the conductance by either resonant transmission or non-resonant scattering of tunneling electrons both causing a substantial reduction of TMR as compared to the ideal MTJs. These results are important for the understanding of the physical mechanisms responsible for IEC and TMR in industrially-important MTJs. Supported by NSF-MRSEC.
5:45 PM - I9.9/J7.9
Magnetic Junctions Exhibiting Spin Filter and Magnetic Tunnel Junction Behavior as a Function of Temperature.
Brittany Nelson-Cheeseman 1 , Rajesh Chopdekar 2 1 , Joanna Bettinger 1 , Yayoi Takamura 1 , Elke Arenholz 3 , Yuri Suzuki 1
1 Materials Science and Engineering, University of California - Berkeley, Berkeley, California, United States, 2 School of Applied and Engineering Physics, Cornell University, Ithaca, New York, United States, 3 , Advanced Light Source, Lawrence Berkeley National Lab, Berkeley, California, United States
Show AbstractI10: Poster Session: Phase Change Volatile Memories I
Session Chairs
Karen Attenborough
Yoshihisa Fujisaki
Friday AM, April 13, 2007
Salon Level (Marriott)
9:00 PM - I10.1
Material and Device Characteristics of Ge-doped SbTe-N Phase Change Memory Material
Zhe Wu 1 , Su Youn Lee 1 , Jeung-hyun Jeong 1 , In Ho Kim 1 , Seul Cham Kim 2 , Kyu Hwan Oh 2 , Byung-ki Cheong 1
1 , Korea Institute of Science and Technology, Seoul Korea (the Republic of), 2 , Seoul National University, Seoul Korea (the Republic of)
Show AbstractReduction of reset current and suppression of thermal interference between memory cells are considered to pose major technical challenges to the development of successful high-density phase-change memory device. To overcome these challenges, a memory device may need a phase change material featuring a low melting temperature combined with a high crystallization temperature. Ge-doped SbTe appears to be a proper candidate fulfilling these requirements. In fact, our recent study of the devices having certain Ge-doped SbTe’s demonstrated remarkable reduction of reset currents as compared to the case of Ge2Sb2Te5. Herein, we proceed further along the same direction to study a material system, consisting of Ge-doped SbTe for a base material and nitrogen for a complementary property-modifier. Sputtered Ge-doped SbTe thin films of varying nitrogen (N) content were examined in terms of phase change, electrical, structural properties and the characteristics of the devices made thereof. The crystalline Ge-doped SbTe-N films were found to have electrical resistivities increasing with N content. These changes are entirely caused by decrease in carrier mobility, which may be explained, according to XRD and TEM observations, to result from the growing carrier scattering with N addition at structural defects such as grain boundaries. By this nature, decrease in thermal conductivity is expected to accompany increase in electrical resistivity with N addition, which would contribute to a significant reduction in reset current. The effect of N addition on crystallization temperature and speed was examined using an electrical hot probe and a static laser tester respectively, to suggest that N addition may increase the stability of a reset state with little sacrificing the set speed as the size of a melt-quenched region is small. Device characteristics of Ge-doped SbTe of varying N are being examined using a test vehicle fabricated to have a contact of 200 nm or less in a pore-type device. Reset and set characteristics of devices having films of various N contents are measured and compared and will be presented at the conference.
9:00 PM - I10.11
Characteristics of N-doped Sb2Te3 Films by X-ray Diffraction and Resistance Measurement for Phase-change Memory.
You Yin 1 , Naoya Higano 1 , Kazuhiro Ohta 2 , Akihira Miyachi 1 , Masahiro Asai 1 , Daisuke Niida 1 , Hayato Sone 1 , Sumio Hosaka 1
1 Department of Nano-Material Systems, Gunma University, Kiryu, Gunma, Japan, 2 Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Show Abstract9:00 PM - I10.12
Ge Doped Ge2Sb2Te5 Films as Multilevel Storage Media for PCRAM.
Kin-Fu Kao 1 , Huai-Yu Cheng 1 , Chi-Jui Lan 1 , Tsung-Shune Chin 1
1 , Department of Materials Science and Engineering, National Tsing Hua University, HsinChu Taiwan
Show Abstract9:00 PM - I10.13
Changes in the Chemical States and Optical Bandgap of Ge2Sb2Te5 and N-doped Ge2Sb2Te5 during Phase Transition
Youngkuk Kim 1 , Uk Hwang 2 , M. Cho 1 , H. Park 2
1 Institute of Physics and Applied Physics, Yonsei University , Seoul, 120-749, Korea (the Republic of), 2 Div.of Advan. Tech., Korea Research Institute of Standards and Science, Daejeon Korea (the Republic of)
Show Abstract9:00 PM - I10.2
Temperature Dependence of Phase Change Memory Cell on Film Thickness of Phase Change Layer
Xiangshui Miao 1 , Luping Shi 1 , Hock Koon Lee 1 , Kian Guan Lim 1 , Hongxin Yang 1 , Jianming Li 1 , Rong Zhao 1 , Tow Chong Chong 1
1 , Data Storage Institute, Singapore Singapore
Show AbstractPCRAM is regarded as one of the most promising next-generation nonvolatile memory technologies because it has near-ideal properties such as a high scalability, a low process complexity, a low cost and a fast writing time. The thermal engineering is the key challenge for PCRAM technology. Although thermal energy induces data writing and erasing on the basis of phase transitions between the amorphous and crystalline states, it also causes thermal deterioration in PCRAM devices. The thermal properties of a PCRAM cell are dominated by the phase-change recording material. To evaluate the thermal properties and thermal deterioration of PCRAM cells with film thicknesses of phase change recording layer, the temperature dependences of the cell properties of PCRAM cells on the film thickness of Ge2Sb2Te5 phase-change layer were simulated and experimentally studied.The computer simulation of the PCRAM cell was carried out using our in-house developed PCRAM cell design software. The thermal simulation was conducted based on the fundamental linear transient thermal conduction equation, and the equation was solved using the three dimensional finite element method (3D-FEM) with appropriate initial and boundary conditions. The dependences of current density, 3D electric field and temperature field of PCRAM cell on phase change layer thickness and environment temperature were simulated. The simulation results showed phase change layer thickness and the environment temperature significantly changed the thermal properties of PCRAM cells and would greatly affect the electric properties of PCRAM cells. The PCRAM cells with different film thicknesses of Ge2Sb2Te5 phase change layer were fabricated. The set/reset resistances and DC I-V curves of the PCRAM cells were measured using an in-house-developed PCRAM tester. The I-V curves and set/reset resistance of the PCRAM cells with different Ge2Sb2Te5 phase change layer thicknesses at different temperatures will be reported in the meeting. The temperature dependences of the threshold voltages of the Ge2Sb2Te5 PCRAM cells with phase change layer thicknesses of 25nm to 150nm were studied. The threshold voltage of the cells decreased with increasing temperature. The results indicated the Ge2Sb2Te5 PCRAM cell with the thicker phase change layer had the higher threshold voltage and the higher thermal stability.
9:00 PM - I10.3
Characteristic of Sb Thin Film Deposited by PEALD.
Yeon-Hong Kim 2 3 , Hun Jung 2 3 , June Key Lee 4 , Do-Heyoung Kim 1 3
2 Department of Fine Chemical Engineering, Chonnam National University, Gwangju Korea (the Republic of), 3 BK21 Division of Functional nano-novel chemical materials, Chonnam National University, Gwangju Korea (the Republic of), 4 Department of Materials Science & Engineering, Chonnam National University, Gwangju Korea (the Republic of), 1 School of Applied Chemical Engineering, Chonnam National University, Gwangju Korea (the Republic of)
Show Abstract9:00 PM - I10.4
Solution Processing – A Low Tech Route to Chalcogenide Phase Change Materials.
Delia Milliron 1 , Simone Raoux 1 , David Mitzi 2 , Andrew Kellock 1 , Robert Shelby 1 , Martha Sanchez 1 , Janette Bunten 1 , Jean Jordan-Sweet 1
1 , IBM Almaden Research Center, San Jose, California, United States, 2 , IBM Watson Research Center, Yorktown Heights, New York, United States
Show AbstractChalcogenide films with reversible amorphous-crystalline phase transitions have been commercialized as optically rewritable data storage media and intensive effort is now focused on adapting them for electrically addressed nonvolatile memory. We report a solution phase route to phase change chalcogenide films, using low temperature processing (<200°C). We achieve ready tunability of phase change properties through composition variation by selecting from a range of novel precursors and combining them in the casting solution. Thermally induced crystallization is monitored by x-ray diffraction and rapid crystallization can be induced by laser annealing. Solution processing also enables simplified fabrication of optical or electrical phase change media.
9:00 PM - I10.5
Analysis of Nucleation and Growth Processes in the Amorphous to fcc Transition of Ge2Sb2Te5.
Stefania Privitera 1 , Salvatore Lombardo 2 , Corrado Bongiorno 2 , Emanuele Rimini 2 4 , Agostino Pirovano 3
1 R&D, STMicroelectronics, Catania Italy, 2 IMM, CNR, Catania Italy, 4 Physics Department, University of Catania, Catania Italy, 3 FTM Advanced R&D, STMicroelectronics, Agrate (Mi) Italy
Show Abstract9:00 PM - I10.6
Calculation of Threshold Voltage in Phase Change Memory Cells.
Edward Voronkov 1
1 Semiconductor Electronics, Moscow Power Engineering Institute, Moscow Russian Federation
Show Abstract9:00 PM - I10.7
Hard x-ray Photoelectron Spectroscopy of Amorphous and Crystalline GeTe-Sb2Te3 Pseudo-binary Compound.
Jung-Jin Kim 1 , Keisuke Kobayashi 1 2 , Toshiyuki Matsunaga 3 , Kouichi Kifune 5 , Eiji Ikenaga 1 , Masaaki Kobata 1 , Shigenori Ueda 1 , Rie Kojima 4 , Noboru Yamada 4
1 , JASRI/SPring-8, Hyogo Japan, 2 , NIMS/SPring-8, Hyogo Japan, 3 , Matsushita Techno Research, Osaka Japan, 5 , Osaka Prefecture University, Osaka Japan, 4 , Matsushita Electric Industrial Company, Osaka Japan
Show Abstract9:00 PM - I10.8
Metal-Organic Chemical Vapor Deposition (MOCVD) of GeSbTe-based Chalcogenide Thin Films.
Edwin Dons 1 , Catherine Rice 1 , Gary Tompa 1
1 , Structured Materials Industries, Inc., Somerset, New Jersey, United States
Show AbstractChalcogenide RAM (C-RAM) has shown significant promise in uniting all the desired attributes of an ideal memory such as nonvolatility, fast write/erase speed, low write/erase voltage, high endurance and radiation hardness. Current C-RAM production technology relies on sputtering to deposit the active chalcogenide layer. The sputtering process leads to difficulties in meeting requirements for device conformality, film adherence, compositional control and wafer yield. Ultimately, an advanced CVD process is needed for high-density products to realize the full potential of C-RAM.In this work, we report the materials properties of GeSbTe-based chalcogenide thin films that are grown by Metal-Organic Chemical Vapor Deposition (MOCVD). Films were grown in a vertical, quartz tube, MOCVD reactor that is heated by halogen lamps. Films were grown at temperatures ranging from 400 C to 600 C. X-Ray Fluorescence (XRF) and Auger Electron Spectroscopy (AES) were performed and showed the film to be uniform in composition (Ge (10%), Sb (30%) and Te (60%)). In this work, we will discuss additional materials and electronic properties of GeSbTe-based chalcogenide thin films grown by MOCVD.
9:00 PM - I10.9
Adhesion of Crystalline GeSbTe/TiN Interface Characterized by Four Point Bend, Nanoindentation, and Nanoscratch.
Guohua Wei 1 , Jun Liu 2 , David Fillmore 1 , Mike Violette 2 , Shifeng Lu 1
1 Surface Analysis Laboratory, Micron Technology, Inc., Boise, Idaho, United States, 2 R & D Department, Micron Technology, Inc., Boise, Idaho, United States
Show AbstractReversible structural phase change phenomenon of certain chalcogenide materials has been investigated extensively in the past decades. It has been successfully applied to commercial optical disk production, and proposed as the functioning mechanism of a promising emerging memory technology. Among various phase change chalcogenide materials, Ge2Sb2Te5 (GST) is the mostly studied material due to its superior optical, electrical, and mechanical properties. One of the challenges for using GST is the poor adhesion between crystalline GeSbTe (c-GST) and the substrate, such as TiN. In this work, two sputtering methods, DC and RF, were utilized to deposit c-GST films on TiN, and the adhesion of c-GST/TiN interface was characterized using four-point bend, nanoindentation, and nanoscratch techniques. Four-point bend technique has been widely used in semiconductor industry for adhesion measurement, but nanoindentation and nanoscratch techniques have received little attention in the field of adhesion characterization. In this paper, these three techniques were combined to study the adhesion of c-GST/TiN, and they all showed that DC-sputtered c-GST/TiN has better adhesion than RF-sputtered c-GST/TiN. The paper also discusses that in some cases, although nanoindentation and nanoscratch cannot provide quantitative adhesion values as four-point bend, they can deliver fast and qualitative adhesion evaluation. This is beneficial if turnaround time is a concern and/or if qualitative data is sufficient, considering that the sample preparation for four-point bend is time-consuming.
Symposium Organizers
Tingkai Li Sharp Laboratories of America, Inc.
Yoshihisa Fujisaki Hitachi Ltd.
Jon Slaughter Freescale Semiconductor, Inc.
Dimitris Tsoukalas National Technical University
I11: Phase Change Non-volatile Memories II
Session Chairs
Friday AM, April 13, 2007
Room 3006 (Moscone West)
9:30 AM - **I11.1
Energy Band States of an Oxygen-doped GeSbTe Phase-change Memory Cell; Mechanism of Low-voltage Operation.
Yoshihisa Fujisaki 1 , Nozomu Matsuzaki 1 , Kenzo Kurotsuchi 1 , Yuichi Matsui 1 , Osamu Tonomura 1 , Takahiro Morikawa 1 , Masaharu Kinoshita 1 , Naoki Kitai 2 , Satoru Hanzawa 1 , Hiroshi Moriya 3 , Norikatsu Takaura 1 , Motoyasu Terao 1 , Masamichi Matsuoka 4 , Tsuyoshi Koga 4 , Masahiro Moniwa 4
1 , Central Research Laboratory, Hitachi Ltd., Tokyo Japan, 2 , Hitachi ULSI Systems Co. Ltd., Kokubunji, Tokyo Japan, 3 , Hitachi Mechanical Engineering Research Laboratory, Hitachi Ltd., Hitachinaka, Ibaraki Japan, 4 , Renesas Technology Corp., Itami, Hyogo Japan
Show AbstractPhase-change memory is promising because it has a simple structure and has scalability that originates from its unique operating mechanism. However, the programming current should be reduced in accordance with the scaling of cell size [1]. We previously reported PCM cells that operate under 1.5-V/100-μA writing pulses [2]. This PCM had a cell structure composed of 180-nm-W (tungsten) bottom contact to an O-GST film. Its low-power characteristic is suitable for 0.13-μm generation embedded applications. In the present study, we introduced a new O-GST/TaO/W cell structure and found further decrease of programming current and more stable operations. We analyzed the mechanism by which oxygen and the additional TaO layer reduces power consumption during SET/RESET operations. A memory cell was composed of a cell-selection MOS transistor with a 0.48-μm gate width and a PCM diode. The doping level to the GeSbTe film was 4.2%. Typical reset current of 100 μA was achieved with an O-GST/W structure that is almost 100 times smaller than those for the pure-GST/W structure. The programming conditions of a PCM cell used were as follows; the bit-line voltages during the pulse application were 1.4 V for RESET operations and 1.2 V for SET operations, the durations of the pulses were 100 ns for RESET and 10 μs for SET operations. In order to improve the fabrication process stability, we introduced a 2-nm-thick TaO adhesion layer between an O-GST film and a W plug electrode. With this O-GST/TaO/W structure, the smallest RESET current of 55 μA is achieved. This low current may be attributable to the thermal confinement due to the TaO layer. To obtain the energy levels of defects, we performed Schottky analysis on PCM cells. At low temperature, just above carrier freeze, trapping of electrons is found when the cell is in RESET state. Arrhenius plots both for SET and RESET states indicate that the current limitation mechanism is Schottky type. The energy level around 0.12 eV corresponds to the acceptor in O-GST. This defect works to transfer current flow to heat effectively resulting in the reduction of RESET current. We also analyzed the energy-band states of PCM cells with a TaO adhesion layer. We found much difference compared to the activation energy of the device without TaO especially in the case of SET states. The SET state of a PCM cell with TaO layer shows Schottky-type conduction when writing current is large enough, whereas it shows tunneling type conduction with the activation energy of 0.07 eV when writing current is small. This means that the interface becomes almost defect-free, if we set a W/O-GST/TaO/W cell with a smaller current. This is because the adhesion TaO layer works effectively to confine the heat in a phase-change layer and reduces the defects at the interface. References[1] S. L. Cho et al., Symp. On VLSI Technology, pp. 96-97, 2005.[2] N. Matsuzaki et al., IEDM Tech. Dig., pp. 31.1.1-31.1.4, 2005.
10:15 AM - I11.3
Device Characteristics of Ge-doped SbTe Material System for Phase Change Random Access Memory (PRAM).
Jeung-hyun Jeong 1 , Su Youn Lee 1 , Wu Zhe 1 , Taek Sung Lee 1 , Won Mok Kim 1 , Seul Cham Kim 2 , Kyu Hwan Oh 2 , Byung-ki Cheong 1
1 Thin Film Materials Research Center, Korea Institute of Science and Technology, Seoul Korea (the Republic of), 2 School of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of)
Show AbstractPhase change random access memory (PRAM) is under spotlight as a promising next generation non-volatile memory because of its excellent functions in terms of writing speed, reading margin, endurance and the possibility of multi-bit storage, etc. However, reduction of reset current and suppression of thermal interference between memory cells are considered to pose major technical challenges to the development of a successful high-density PRAM. To overcome these challenges, a future memory device may need a new phase change material (pcm) featuring a low melting temperature combined with a high crystallization temperature. Here we study a candidate material system known as Ge-doped SbTe (Ge:SbTe). According to our own characterization of a Ge:SbTe, it has a melting temperature (540oC) of about 100oC lower than that of Ge2Sb2Te5 and a higher crystallization temperature (170oC), satisfying the material requirements set above. The Ge-doped SbTe material system, famous for its use in rewritable optical disks, has been hardly studied in terms of device characteristics with a conventional device except for with a new device named phase change line memory having a planar pcm/electrode structure. The device characteristics of Ge-doped SbTe’s of a few selected compositions were examined and compared with the case of Ge2Sb2Te5 using simple pore-type memory cells, each having an electrode/pcm/electrode vertical structure fabricated to have a 200 nm contact hole with e-beam lithography. Reset and set currents were measured by way of resistance vs. current curves resulting from incremental application of reset (50ns) and set voltage pulse (300ns), respectively. As it turned out, the reset currents of Ge:SbTe’s were lower than that of Ge2Sb2Te5 by about 50% and the set currents were significantly lower as well. The lower reset currents of Ge:SbTe’s are presumed to result not only from lower melting temperatures but also from higher dynamic resistances that would yield larger joule heating. Ge:SbTe’s were also found to have significantly smaller set times, as somewhat expected from increasingly faster crystallization with decreasing programmable volume in the growth dominant mode. Between Ge:SbTe’s of different compositions, one with an increased Sb/Te ratio was found to yield a smaller reset/set current and, more pronouncedly, a smaller set time. From TEM analysis, the observed tendency of set time was found to have a strong correlation with an increasingly prevailing growth dominant mode of crystallization with increasing Sb/Te. In conclusion, the present study strongly suggests that Ge-doped SbTe’s could be a better choice for a high density PRAM due to their capability of low power and high speed operation.
10:30 AM - I11.4
New Kind of Microstructure Essential for Amorphous-Crystalline Transitions in Chalcogenide-Based Films.
Vladimir Kolosov 1 , Lev Veretennikov 1
1 , Ural State Economic University, Ekaterinburg Russian Federation
Show AbstractChalcogenide-based films are widely used as the active media for rewritable information storage and are prospective for further developments. Anyway detailed microstructure characterisation of the crystallised spots seems lacking. Using some initially amorphous vacuum condensates (Se-Te, Sb2Se3 and bilayers Ge-Sb2Se3) we study the crystals growing under the influence of local electron beam annealing in transmission electron microscope (TEM). Primarily we focus on the specific feature inherent to amorphous-crystalline transformation in thin films - "transrotational" structure [1], most prominent between micro- and nanoscale [2]. Extinction bend contours indicating such regular imperfections on the TEM images of crystallised spots of chalcogenide thin films (e.g., phase change materials for optical recording) are widespread and can be found in corresponding publications (e.g., [3-4]). We used bend contour technique preferentially for measurements of local and integral magnitudes of lattice bending and for estimates of geometry and general character of lattice disorientations in the crystallized areas.To study the effect of thickness (10-100 nm) and composition the films with strong gradient either of composition (Se-Te) or thickness (Sb2Se3, bilayers Ge-Sb2Se3) were prepared and placed on the TEM grids. Samples were irradiated by the electron beam inside TEM thus making possible a broad choice of various intensities, different irradiated spots (~ 1 μm and above) and also in situ studies.Strong internal lattice bending around axes lying in the film plane are observed for the materials studied. In Se-Te films the relative concentration strongly affects the magnitude of internal lattice bending. In Sb2Se3 films the internal lattice bending strongly increases as the film gets thinner, while growth rate decreases. In Ge-Sb2Se3 bilayers (with variable thicknesses of the layers) the influence of Ge layer on the crystal growth and microstructure can be more or less pronounced but depends upon the layer position (sublayer or overlayer). The intensity of the electron beam strongly influences the crystallization and the structure of crystallized spot in the case of Ge sublayer. Above microstructure parameters (primarily magnitude of internal lattice bending) that may be revealed by TEM (but usually missed in the papers) can strongly influence the time, energy an other features essential for writing/rewriting in chalcogenide films used as phase change materials.[1] V.Yu. Kolosov and A.R. Tholen, Acta Mater. v. 48 (2000), p. 1829 [2] V. Yu. Kolosov, Proc. 13th EMC, Antwerp, v. 2, 255 (2004).[3] S. J. Price; A. L. Greer; C. E. Davies, Optical Data Storage 2000 (2000).[4] B. J. Kooi, and J. Th. M. De Hosson, J. of App. Phys., 95, 4714 (2004).This work was supported by INTAS (00-100), pending support from RFBR.
10:45 AM - I11.5
Crystallization Kinetics of As-Deposited and Melt-Quenched Phase-Change Materials
Yi-Chou Chen 1 , Charles Rettner 2 , Simone Raoux 2 , Geoffrey Burr 2 , Bob Shelby 2 , Martin Salinga 3
1 IBM/Qimonda/Macronix PCRAM Joint Project , Macronix International Co. Ltd., Hsin-Chu Taiwan, 2 IBM/Qimonda/Macronix PCRAM Joint Project , IBM Almaden Research Center, San Jose, California, United States, 3 IBM/Qimonda/Macronix PCRAM Joint Project, I. Physikalisches Institut IA, RWTH, Aachen, Aachen Germany
Show AbstractSolid state phase-change memory (PCM) is considered one of the most promising next generation memory technologies due to its excellent electrical and scaling properties. The combination of long data retention and fast operating speed make PCM a candidate for a “universal” memory. The crystallization mechanism of the phase-change material is thus a crucial topic. However, the crystallization kinetics of phase change materials are almost always studied on as-deposited amorphous thin film materials, even though phase-change memory devices typically exhibit only the melt-quenched amorphous state during operation. This difference arises because on the one hand it is difficult to prepare large-area melt-quenched samples, and on the other hand, the high temperatures required during conventional device fabrication inevitably lead to crystallization. Therefore it has been all but impossible to fabricate fully-processed devices that contain as-deposited amorphous material for direct comparison to thin-film studies. In order to compare the as-deposited and melt-quenched amorphous states of phase-change materials, we fabricated line-device structures using an e-beam lithography process that keeps the sample temperature well below the crystallization temperature of the phase change material. Thus finished devices contain the phase change material Ge2Sb2Te5 in the as-deposited amorphous state. Some devices were subsequently annealed at different temperatures to crystallize the phase change material into either the fcc or hcp crystalline phase, and laser pulses were used to switch a portion of the device into the melt-quenched amorphous phase. The resistivity both as a function of temperature and as a function of time at elevated temperature were measured for otherwise identical devices containing material in the as-deposited and in the melt-quenched states. By applying the Johnson-Mehl-Avrami-Kolmogorov (JMAK) theory, the crystallization kinetics of the as-deposited and melt-quenched devices were quantified. The results show drastic differences between the as-deposited and melt-quenched devices, with lower crystallization temperatures and shorter incubation times for melt-quenched devices. While these results can be partly ascribed to the presence of crystal growth from crystalline/melt-quenched amorphous boundaries, they also suggest that crystal nucleation differs between the melt-quenched and as-deposited amorphous phases.
11:00 AM - I11: PCRAM II
BREAK
11:30 AM - I11.6
Phase-Change Nanowires for Non Volatile Memory
Yi Cui 1 , Stefan Meister 1 , Hailin Peng 1
1 , Stanford University, Stanford, California, United States
Show AbstractThe crystalline to amorphous phase-change in chalcogenide alloy materials has been exploited for non-volatile memory. We present our recent studies on synthesis, characterization and switching of phase-change nanowires. A family of phase change chalcogenide nanowires including Ge-Sb-Te, Ge-Te, Sb-Te, In-Se, Ga-Se are synthesized via a vapor-liquid-solid growth mechanism. Their phase transformations are studied by transmission electron microscopy and electrical transport. The size dependent switching will be discussed.
11:45 AM - I11.7
Effect of Nitrogen Doping on Microstructure and Mechanical Behavior of Ge2Sb2Te5 Films.
Il-Mok Park 1 , Jung-kyu Jung 1 , Young-Chang Joo 1
1 , Seoul National University, Seoul Korea (the Republic of)
Show Abstract12:00 PM - I11.8
Time-resolved X-ray Diffraction Studies of Phase Change Ultra-thin Films and Nanoparticles.
Simone Raoux 1 , Jean Jordan-Sweet 2 , Charles Rettner 1
1 1IBM/Qimonda/Macronix PCRAM Joint Project, Almaden Research Center, IBM Research Division, San Jose, California, United States, 2 2IBM T. J. Watson Research Center, IBM Research Division, Yorktown Heights, New York, United States
Show AbstractPhase change materials (PCMs) hold great promise as the basis for future non-volatile memory devices. The scalability of phase change technology is a critical issue for its development. We have studied the scaling behavior of PCMs themselves, to determine the length scale that the crystallization properties, such as crystallization temperature and crystal structure, start to be influenced by scaling. We fabricated ultra-thin films of Ge2Sb2Te5 (GST), N-doped GST, Ge(15%)Sb(85%) (GeSb), Sb2Te (SbTe), and Ag and In-doped Sb2Te (AIST) with thicknesses between 1 and 50 nm using sputter deposition. The films were capped by thin Al2O3 layers to prevent oxidation. Ellipsometry of capped and uncapped samples before and after a UV-ozone treatment of the samples to force oxidation showed that 10nm of Al2O3 successfully protect the ultra-thin PCM films from oxidation. In addition to thin films, we also fabricated phase change nanoparticles over large areas (2mmx5mm) using electron-beam lithography. The sizes of the nanoparticles ranged from 20 to 80 nm with spacings between 80 and 100 nm. The crystallization behavior of thin films and nanoparticle arrays was studied using time-resolved X-ray diffraction at beamline X20C of the National Synchrotron Light Source at Brookhaven National Laboratory. The setup consisted of a high-throughput synthetic multilayer monochromator, a fast linear-diode-array detector, and a special chamber for controlling the sample ambient (purified He gas), equipped with a BN heater for rapid annealing. The intensity of the diffracted X-ray peaks was recorded over a 2-theta range of 15 degrees as a function of temperature during sample heating at a rate of 1C/s. It was found for all materials studied that the crystallization temperature increases for ultra-thin films when the film thickness is less than 10nm. This increase is quite substantial and reaches 80-100 C for most materials. We also observed changes in the crystalline texture for all materials. The thinnest films that showed clear crystallization peaks were 2nm for GST and N-GST, and 1.5nm for GeSb, SbTe, and AIST. The nanopatterns showed a much weaker size dependence over the range studied, and they crystallized at temperatures similar to or slightly lower than 50nm thick blanket films. All nanopatterns of all materials we studied showed clear signs of crystallization. This crystallization behavior of thin films and nanostructures indicates that PCM-based memory devices should be scalable to very small dimensions, consistent with the recent report of successful switching in devices having only 3nm thick PCM (published elsewhere, Chen et al., IEDM 2006).
12:15 PM - I11.9
Evolution of the Amorphous Structure in Ge2Sb2Te5 Thin Films Induced by High-energy Heavy Ions Irradiation and Laser Pulses.
Riccardo De Bastiani 1 , Alberto Piro 1 , Salvatore Lombardo 2 , Maria Grimaldi 1 , Emanuele Rimini 2 3
1 , MATIS CNR-INFM and Dipartimento di Fisica e Astronomia, Università di Catania, Catania Italy, 2 , IMM-CNR, Catania Italy, 3 , Dipartimento di Fisica e Astronomia, Università di Catania, Catania Italy
Show Abstract12:30 PM - I11.10
Phase-change current-voltage Characteristic of Ge2Sb2Te5 Nanoparticle-clusters Fabricated on Conducting Scanning Probes for Nano-scale Non-volatile Memories.
Hyeran Yoon 1 , Yoojin Oh 1 , William Jo 1
1 Department of Physics, Ewha Womans University, Seoul Korea (the Republic of)
Show Abstract12:45 PM - I11.11
Ge2Sb2Te5 Film Deposition and Properties.
Mengqi Ye 1 , Rong Tao 1 , Peijun Ding 1 , Abner Bello 1
1 Thin Films Group, Applied Materials, Inc., Santa Clara, California, United States
Show AbstractChalcogenide based phase change memory (PCM), considered the most promising alternative non-volatile memory (NVM) technology for the next decade, has demonstrated the best scalability among the few NVM candidates, and is being actively investigated by the industry. Ge2Sb2Te5 is the most widely used material for PCM, and has many unique properties, including strongly temperature-dependent film properties, low thermal conductivity, and high electrical resistivity. The unique film properties pose many challenges for deposition equipment, processes and film characterization. A magnetron sputtering chamber has been developed for Ge2Sb2Te5 film deposition. In order to fully understand the effects of deposition process parameters on the film properties, we studied the effects of various process parameters and characterized systematically the film properties including sheet resistance, thickness, resistivity, density, stress, composition, and microstructure. In particular, we studied the effects of in-situ heating on film properties. It has been found that maintaining in-situ wafer temperature is critical for achieving consistent film properties. Film sheet resistance and uniformity fluctuated when no wafer chucking was used, whereas good repeatability was achieved when an electrostatic chuck was used to maintain good chuck/wafer thermal coupling during the deposition process. XRD scans of the films, processed with chuck temperature set at 25°C but without actual chucking, varied from wafer to wafer, and many of the samples were crystalline as-deposited due to plasma heating. On the contrary, repeatable amorphous and crystalline phases can be obtained by chucking the wafers at 25°C and 235°C, respectively. The effects of chuck temperature on film properties were further studied. The film resistivity decreased from 76 mΩ cm to 9 mΩ cm when the chuck temperature increased from 120°C to 235°C. The film stress shows an interesting evolution with chuck temperature: it was tensile when deposited at 25°C, but changed to compressive and reached maximum magnitude at around 120°C, then decreased in magnitude with increasing temperature, and then changed back to tensile at around 190°C and above. The film density increased by about 3.4% when chuck temperature increased from 100°C to 120°C, which can be attributed to the film phase change from amorphous to crystalline state, as verified by XRD scans. Further experimental study of the effects of various process parameters, such as wafer bias and sputtering pressure, on film properties is in progress and will be reported. A number of analytical techniques were employed in our study of the various Ge2Sb2Te5 film properties. The advantages and limitations of these techniques (XRR, XRF, RBS/PIXE, SIMS, XPS, etc.) on GST film characterization will be presented along with the analytical results.
I12: Phase Change Non-volatile Memories III
Session Chairs
Yi Cui
Yoshihisa Fujisaki
Friday PM, April 13, 2007
Room 2003 (Moscone West)
2:30 PM - **I12.1
Novel Cell Concept for Phase Change Random Access Memory.
Karen Attenborough 1
1 , Research, NXP Semiconductors, Leuven Belgium
Show Abstract3:00 PM - I12.2
Preparation of Ge2Sb2Te5 Thin Film for Phase Change Random Access Memory by Magnetron Sputtering on Small Hole Patterns.
Shin Kikuchi 1 , Yutaka Nishioka 1 , Isao Kimura 1 , Takehito Jimbo 1 , Masahisa Ueda 1 , Yutaka Kokaze 1 , Koukou Suu 1
1 , ULVAC, Inc., Susono, Shizuoka Japan
Show AbstractPhase Change Random Access Memory [PRAM] is one of the candidates for next generation memory due to its non-volatility, high speed, high density and compatibility with Si-based semiconductor process. Ge2Sb2Te5 [GST] thin film, an active layer in this device, is utilized because it has the well-known property of rapid crystallization without phase separation in erasable compact discs industry. In order to integrate PRAM to beyond 512Mbit, a high writing current and degradation of cell transition at small cell size become a problem. To resolve these problem, Confined Cell structure PRAM was suggested.[1] However, it was difficult to fill GST layer in a small hole with a conventional sputtering tool because a big overhang occurred.In this work, we prepared GST films on the small hole patterned wafer by a new concept sputtering tool which designed developed a new concept sputtering tool. The structure of GST film was observed with cross section SEM and the film composition was measured with XRF. It was observed an overhang was suppressed and a GST film was filled in a small hole with a new concept tool. In addition, the uniformity of the GST film composition was good at less than 3% in 200mm φ substrate.[1]S.L.Cho., et al, 2005 Symposium on VLSI Technology Digest of Technical Papers,6B-1.
3:15 PM - I12.3
Nano-patterning of GST Thin Films by Self-assembled Di-block Copolymers Lithography.
Pietro La Fata 1 3 , Salvatore Lombardo 1 , Emanuele Rimini 1 3 , Stefania Privitera 2 , Rosaria Puglisi 1
1 , CNR-IMM, Catania Italy, 3 , Università di Catania, Catania Italy, 2 R&D, STMicroelectronics, Catania Italy
Show AbstractChalcogenide-based Phase Change Random Access Memories (PCRAM) are promising candidates for next generation non-volatile memory devices because of their scalability potentially limited only by lithography and for the low fabrication costs. GeSbTe (GST) alloys may ensure non-volatility, endurance as well as multiple bit operation, and very fast switching speed of the cells. For these goals a detailed understanding of the structural properties of the materials is crucial, particularly at the nanoscale level. In this aspect, it would be highly desirable to have highly simplified structures, allowing access to the bits without the need of complete complex front-end and back-end processes. While the latter is obviously necessary, the basic problem of defining the best materials for PRAMs may undoubtedly gain from the availability of a very basic direct process which allows to test at the nanoscale level with large statistics.To this end we propose a technique based on di-block copolymers lithography to produce dense arrays of amorphous islands of a few nanometers (10-20 nm size) embedded in crystal, in order to test the electrical properties of many bits in parallel with a sensitivity at the level of a few PRAM cells. A SiO2 hard mask is first defined on a crystalline sputtered Ge2Sb2Te5 thin film by induced coupled plasma (ICP) etching, using a close packed hexagonal array obtained by di-block copolymers self assembling as a sacrificial layer. The amorphous pattern on the crystalline GST is then produced by ion implantation through the patterned SiO2 mask.The concept is shown and discussed and the patterned GST is studied as a function of different amorphization conditions.
3:30 PM - I12.4
Asymmetric Phase Change Random Access Memory
Hock Koon Lee 1 , Luping Shi 1 , Weijie Eng 1 , Hongxin Yang 1 , Rong Zhao 1 , Kian Guan Lim 1 , Xiangshui Miao 1 , Jianming Li 1 , Tow Chong Chong 1
1 Optical Materials & Systems Division, Data Storage Institute, A-Star, Singapore Singapore
Show AbstractPhase change random access memory (PCRAM) has almost ideal properties as a NVM: fast accessing time, low power consumption, low cost, high endurance and good data retention. It uses a phase change material which switches between crystalline and amorphous states on the application of electrical pulses. A PCRAM cell has its phase change material sandwiched between two electrodes which, in turn, are isolated by dielectric layers. Traditionally, upper and lower openings for the electrodes to make contact with the phase change layer are usually along the same vertical axis. Here we studied an asymmetric PCRAM structure with its upper electrode contact at an offset to its bottom electrode contact. This offset distance is measured between the axes of the upper and bottom contact openings. These contact openings are 1 um in diameter. With asymmetric structure, the effect of the offset distances on the temperature profile of the phase transition was studied and this allowed us to control the thermal distribution within the phase change layer. Simulation results showed that using the asymmetric structure, the maximum temperature at the phase transition region is much higher than that of a standard PCRAM cell on application of 50 ns of 0.8 V. This implied a lower operating voltage required for the asymmetric PCRAM cell. The maximum temperature is 740 °C when using the asymmetric PCRAM cell with an offset distance of 1 um while that of a standard PCRAM cell is only 586 °C. The temperature profiles for other offset distances were studied too. Asymmetric PCRAM cell of < 2 um offset has a smaller but hotter active region which meant that less energy is needed for the phase transitions.Experimental results showed that the asymmetric PCRAM cell of < 2 um offset has lower reset voltage (phase change from crystalline to amorphous states) compared to that of a standard PCRAM cell when the voltage pulse width is ranged from 10 ns to 80 ns. The reset voltage of asymmetric PCRAM cell of 1 um offset is 50% lower than that of a standard PCRAM cell. The ratio of the reset and set (phase change from amorphous to crystalline states) resistance is 100.The reset voltage starts to increase when the offset is less or more than 1 um. The higher reset voltage for the cells <1 um offset can be explained by the partial overlap of the upper electrode contact opening with the active region which allows heat diffusion. For the cells of >1 um offset, the current flow path would be longer and thus the response speed would be slower.
3:45 PM - I12.5
In situ SEM Observation of Grain Formation and Growth Induced by Electrical Pulses in Lateral Ge2Sb2Te5 Phase-change Memory.
You Yin 1 , Daisuke Niida 1 , Kazuhiro Ohta 2 , Akihira Miyachi 1 , Masahiro Asai 1 , Naoya Higano 1 , Hayato Sone 1 , Sumio Hosaka 1
1 Department of Nano-Material Systems, Gunma University, Kiryu, Gunma, Japan, 2 Department of Electronic Engineering, Gunma University, Kiryu, Gunma, Japan
Show Abstract4:00 PM - I12: PCRAM III
BREAK
4:30 PM - I12.6
Stress and Mechanical Constants Characterizations of Phase-change SbTe-alloys: Influence of the Film Thickness and Substrate.
Judit Lisoni 1 , Thomas Gille 1 2 , Ludovic Goux 1 , Romain Delhougne 3 , Karen Attenborough 3 , Dirk Wouters 1
1 SPDT Div., IMEC, Heverlee (Leuven) Belgium, 2 ESAT/INSYS, KU Leuven, Leuven Belgium, 3 Research, NXP Semiconductors, Leuven Belgium
Show Abstract4:45 PM - I12.7
Chalcogenide Ag-Bi-S Thin Films Prepared by Pulsed Laser Deposition
Chun-I Wu 1 , Joseph Wachter 2 , Mercouri Kanatzidis 3 , Tim Hogan 1
1 Electrical and Computer Engineering, Michigan State University, East Lansing, Michigan, United States, 2 Chemistry, Michigan State University, East Lansing, Michigan, United States, 3 Chemistry, Northwestern University, Evanston, Illinois, United States
Show AbstractChalocogenide films are promising materials for nonvolatile memory due to the reversible phase transition between amorphous and crystalline state. Certain dominant materials, such as GeSbTe (GST), have been broadly investigated. As to reduce the switching time and increase storage capacity, more materials are indispensable for further studies. Ag-Bi-S thin films were successfully fabricated on different substrates via a simple process of pulsed KrF laser deposition (PLD). Presented here are the fabricated conditions, properties, and images of the resulting thin film from Ag-Bi-S system. The products are characterized by scanning electron microscopy (SEM), Energy Dispersive X-Ray Spectroscopy, as well as X-Ray diffraction (XRD).
5:00 PM - I12.8
Transition Behavior of High Density Ordered Phase Change Nanostructure from Diblock Copolymer Template
Yuan Zhang 1 , Simone Raoux 2 , Jennifer Cha 2 , Leslie Krupp 2 , Charles Rettner 2 , Teya Topuria 2 , H.-S. Philip Wong 1
1 EE, Stanford University, Stanford, California, United States, 2 , IBM Almaden Research Center, San Jose, California, United States
Show AbstractPhase change memory (PCM) is one of the most promising candidates for non-volatile memory devices because of its good scalability, fast write/erase speed, and long endurance. Programming of this resistive memory device relies on the phase change transition between two states: reset state (amorphous phase) and set state (crystalline phase). Phase transition of PCM is achieved by Joule heating, which requires a high programming current. To reduce the programming current, various phase change materials have been studied, and innovative cell designs have been invented that minimize the current conduction cross-section to induce large Joule heating. This paper introduces a new method to fabricate high density, ordered nanopatterns of the phase change material GeSb, and compares the phase transition temperature of GeSb nanodots with blanket GeSb films. Self-assembling diblock copolymer, PS-b-P4VP (polystyrene-b-polyvinylpyridine), was used as the template for fabricating GeSb nanopatterns. After self-assembly of the PS-b-P4VP on the blanket GeSb film, the diblock copolymer template was first transformed to a silica nanodot pattern by TEOS (Tetraethylorthosilicate) and water vapor exposure leading to silica polymerization in the pyridine domains. The silica nanodot pattern was then etched (by ion milling) into the underlying GeSb layer to form high density GeSb nanodots. The size and spacing of individual dot depends on the P4VP block and PS chain, respectively. We obtained 15 nm diameter dots with 30nm spacing, which were smaller than similar patterns obtained from electron beam lithography. In addition, this method forms a large array of nanodots with high density (essential for XRD), which is very time consuming to obtain by e-beam lithography. Time-resolved XRD showed that the amorphous to hexagonal phase transition occurred at 235oC, which was about 20oC lower than blanket film. However, this temperature is still higher than that of the phase change material Ge2Sb2Te5 (GST), which demonstrates that GeSb has good scalability and temperature stability for smaller device fabrication.
5:15 PM - I12.9
Relationship between the Crystallization Speed and Nanoscale Structural Order in Ge2Sb2Te5 and AgInSbTe Phase Change Materials.
Bong-Sub Lee 1 2 , Stephanie Bogle 1 2 , Simone Raoux 3 , Charles Rettner 3 , Robert Shelby 3 , Geoffrey Burr 3 , Ying Xiao 1 2 , Stephen Bishop 2 4 , John Abelson 1 2
1 Department of Materials Science & Engineering, University of Illinois at Urbana-Champaign, Urbana, Illinois, United States, 2 Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, Illinois, United States, 3 , IBM Almaden Research Center, San Jose, California, United States, 4 Department of Electrical & Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, Illinois, United States
Show AbstractPhase change materials exhibit rapid and reversible amorphous-to-crystalline phase transformations that are the basis of rewritable CDs/DVDs and non-volatile phase change random access memories. The speed of these devices depends on the kinetics of phase transformation, especially crystallization. One long standing puzzle is that, for a fixed composition, different processing conditions afford amorphous states with significantly different crystallization rates. For example, crystallization from the melt-quenched (re-amorphized) amorphous state is one or more orders of magnitude faster than from the as-deposited amorphous state. However, these kinetically different states all appear amorphous and indistinguishable in diffraction experiments. Here, we show that the different crystallization speeds originate from the degree of structural order on the scale of a few nanometers in the amorphous state.To quantify the nanoscale structure, we utilize fluctuation electron microscopy, which employs statistical analyses of nanodiffraction data obtained by scanning transmission electron microscopy. This technique is directly sensitive to 3- and 4-atom correlations, i.e. structural order on the scale of 1-3 nm, which is not possible to determine using other techniques. We show that all amorphous states of phase change materials studied here have some degree of nanoscale order -- they are not continuous random network solids. Interestingly, the nanoscale order typically increases when an as-deposited sample is thermally annealed below the crystallization threshold. Higher nanoscale order corresponds to more or larger ordered regions, and we hypothesize that some of these regions act as nucleation centers for crystallization. We measured the crystallization speed of Ge2Sb2Te5 and AgInSbTe using dedicated pump-probe laser equipments, and found that the speed becomes higher after such annealing. The primary difference is a reduction in the incubation time for nucleation in the presence of higher nanoscale order. This effect is much greater in the case of AgInSbTe, where nucleation is relatively difficult compared to growth. The nucleation in Ge2Sb2Te5 is relatively easy even in the as-deposited state, so the effect of higher nanoscale order is less pronounced. Finally, we demonstrate that the laser melt-quenched amorphous state of Ge2Sb2Te5 has crystalline particles that are several nanometers in diameter, in addition to an amorphous matrix that has higher nanoscale order than the as-deposited state. These nanocrystallites act as supercritical nuclei, eliminate the incubation delay, and afford order(s) of magnitude higher crystallization speed. We will also present new results on the crystallization speed and nanostructure of GeSb, which crystallizes at higher temperatures and is of special interest for the ~ 90 °C environment of cache memories in microprocessors.
5:30 PM - I12.10
Electrical and Physical Characterization of Ge, Te, Se, and Sn-Containing Alloys for Single Layer and Multiple Layer Phase-Change Electronic Memory Applications.
Kris Campbell 1 2 , Morgan Davis 2 , Jeffrey Peloquin 3
1 Electrical and Computer Engineering, Boise State University, Boise, Idaho, United States, 2 Materials Science and Engineering, Boise State University, Boise, Idaho, United States, 3 Department of Chemistry, Boise State University, Boise, Idaho, United States
Show AbstractTwo-terminal electronic devices consisting of stacks of chalcogenide layers containing GeTe, Ge2Se3, SnTe, and SnSe have shown promise for application as electronic phase-change memories (Campbell, K.A. and Anderson, C.M., Microelectronics Journal, in press). We have been investigating the electrical and physical properties of these stacked materials in order to understand the mechanisms responsible for their successful operation as phase-change memories. We report the synthesis of several GexTeySnz and GexSeySnz alloys with compositions that may mimic the stacked layers in a fully chemically mixed state, and characterize the bulk and thin film electrical and physical properties of these materials. We present our characterization results along with a comparison of the electrical results from the stacked layer structures and the single layer alloy compositional-analog structures.