Symposium Organizers
Ting Y. Tsui Texas Instruments, Inc.
Young-Chang Joo Seoul National University
Alex A. Volinsky University of South Florida
Lynne Michaelson Vishay Electro-Films
Michael Lane IBM T.J. Watson Research Center
F1: Processing and Characterizations of Low-k Dielectrics
Session Chairs
Michael Lane
Joost Vlassak
Tuesday PM, April 18, 2006
Room 3009 (Moscone West)
9:30 AM - **F1.1
Development of Ultralow-k SiCOH Dielectrics with K Values Down to 1.80.
Alfred Grill 1 , Vishnubhai Patel 1 , Son Nguyen 1 , Deborah Neumayer 1 , Muthumanickam Sankarapandian 1 , Yuri Ostrovski 1 , Eric Liniger 1 , Eva Simonyi 1
1 , IBM - T.J. Watson Research Center, Yorktown Heights, New York, United States
Show Abstract10:00 AM - **F1.2
Impact of Pore Size and Morphology of Porous Organosilicate Glasses on Integrated Circuit Manufacturing.
Mark O'Neill 1 , Raymond Vrtis 1 , Brian Peterson 2 , Mary Haas 1 , Scott Weigel 1 , Dingjun Wu 1 , Mark Bitner 1 , Eugene Karwacki 1
1 Electronics Technology, Air Products and Chemicals, Inc., Allentown, Pennsylvania, United States, 2 Computational Modeling Center, Air Products and Chemicals, Inc., Allentown, Pennsylvania, United States
Show AbstractMaterials with increasingly lower dielectric constant values are needed for future generation ICs in order to continue to enhance signal propagation. Current state of the art IC production uses organosilicate glasses (OSGs) with dielectric constant (k) values on the order of 3.0. Dense OSG materials, however, are inherently limited to k values ≥ 2.7.{1,2} To achieve k values of < 2.5, alternative materials, processing, or a combination of both must be used. The introduction of porosity is one commonly used technique to reduce dielectric constant, where the degree of reduction depends largely upon the film porosity. While porous materials inherently suffer from inferior mechanical properties relative to their non-porous predecessors, post-treatment processes such as UV and e-beam can dramatically improve the integratibility of these materials.Porous organosilicate glasses produced by plasma enhanced chemical vapor deposition have arisen as the leading candidates for back-end-of-line dielectric insulators for 45nm generation IC manufacturing. The PDEMS® ILD process involves the co-deposition of an organosilicate glass network with an organic porogen.{3} The deposition is followed by a post-treatment to liberate the labile organic material and mechanically fortify the porous structure. One of the main considerations for use of porous materials in IC manufacturing is pore size and pore interconnectivity. It is preferred that the porosity be homogeneously distributed and discrete, with a narrow size distribution of nanometer-sized pores. Porous organosilicate glasses produced by PE-CVD from the combination of diethoxymethylsilane (DEMS® ILD precursor) and α-terpinene (ATRP) can produce films with k values < 2.0 with monodisperse porosity centered around 1.5-1.7 nm diameter.{4} Here we report that the type of porogen has the most significant impact upon the average pore size, as determined by Positron Annihilation Lifetime Spectroscopy (PALS). Experimental data supports a distinct relationship between pore size and pore interconnectivity, where materials with smaller pores tend to have a more interconnected pore morphology. In addition, we report geometric modeling of two-phase composite materials in order to define the theoretical morphological transition between 1) discretely dispersed pores within an OSG continuum (cf. Swiss cheese) and 2) a homogeneous, low-density OSG matrix (cf. steel wool).In this paper we examine how pore size and morphology are affected by the choice of chemical precursors and process conditions and the implications this has on subsequent process steps such as dry etching, wet stripping, and pore sealing.
10:30 AM - F1.3
Pore Engineering: Ultra Low k Porous SiCOH For 45nm And Beyond.
Sang Ahn 1 , Josephine Chang 1 , Thomas Nowak 1 , Nagarajan Rajagopalan 1 , Kangsub Yim 1 , Khaled Elsheref 1 , Alex Demos 1 , Sanjeev Jain 1 , Derek Witty 1 , Hichem MSaad 1
1 , Applied Materials, Inc., Santa Clara, California, United States
Show Abstract11:15 AM - **F1.4
Novel Polysilsesquioxane Systems for Ultralow-Dielectric Films with High Modulus, Low CTE, and Closed-Pore Morphology
Do Yoon 1 , Hyun Wook Ro 2 , Jie Hye Park 1 , Jae Hwan Shim 1 , Eun Su Park 1 , Jin-Kyu Lee 1 , Hee-Woo Rhee 3 , Hae-Jeong Lee 2 , Christopher Soles 2 , David Gidley 4
1 Department of Chemistry, Seoul National University, Seoul Korea (the Republic of), 2 Polymer Division, National Institute of Standards and Technology, Washington, District of Columbia, United States, 3 Department of Chemical Engineering, Sogang University, Seoul Korea (the Republic of), 4 Department of Physics, University of Michigan, Ann Arbor, Michigan, United States
Show AbstractNovel polysilsesquioxanes (PSSQs) have been developed which contain thermally degradable groups (porogens) grafted to the polymer backbone. Upon optimizing the backbone polymer structure and the grafted porogen, the fully cured films exhibit nanoporous structures with excellent mechanical properties significantly improved over those of conventional blended porogen systems, together with closed-pore morphology up to the porosity of 15 %. However, as the porosity increases over 20 %, the pores become highly interconnected although the average pore diameter remains smaller than ca. 2 nm as determined by the positronium annihilation lifetime spectroscopy (PALS). In order to overcome the pore interconnectivity, a dual porogen system containing another blended porogen polymer has been investigated. As a result, nanoporous films of ultralow-dielectric constant (<2.1), with the porosity greater than 30 %, have been obtained, which also exhibit excellent mechanical properties, including a high modulus (> 6 Gpa) and a low coefficient of thermal expansion (CTE) (< 10 ppm/K), with nearly closed-pore morphology.
11:45 AM - F1.5
Matrix Structure of Organo-Silicate Glasses and Thermo-Mechanical Properties of Thin Low-K Films.
Francesca Iacopi 1 , Gerald Beyer 1 , Kristof Houthoofd 2 , Peter Adriaensens 3 , Carlo Waldfried 4 , Steven Demuynck 1 , Youssef Travaly 1 , Salvador Eslava-Fernandez 1 2 , David Gage 5 , Simone Giangrandi 1 , M Rennau 6 , Knut Schulze 6 , Stefan Schulz 6 , Giovanni Carlotti 7 , Reinhold Dauskardt 5
1 , IMEC, Leuven Belgium, 2 Bio-Engineering Dept., Katholieke Universiteit Leuven, Leuven Belgium, 3 Chemistry Dept., Universiteit Hasselt, Diepenbeek Belgium, 4 , Axcelis technologies, Beverly, Massachusetts, United States, 5 Meterials Science and Engineering, Stanford University, Stanford, California, United States, 6 Center for Microelectronics, TU Chemnitz, Chemnitz Germany, 7 Physics Dept., University of Perugia, Chemnitz Italy
Show AbstractThe great majority of low dielectric constant materials currently proposed for use in interconnects belongs to the category of organosilicate glasses. Common denominator for all of these dielectrics is an amorphous matrix composed by a silica backbone to which a variable amount of C –based functional groups is attached. Nevertheless, the short and long –range matrix structure of such dielectrics can vary to a great extent depending on the precursors and deposition processes used for film deposition. As a consequence, the film properties show a large range of variability as well.The introduction of porosity in the films is required for lowering the dielectric constant, but has been shown to dramatically weaken most thermo-mechanical film properties. Therefore the understanding of how the glass structure is linked to film properties and how it can be optimized so to compensate as much as possible for the worsening due to porosity becomes of crucial importance. In this work we compare different organosilicate glasses, deposited either by Chemical Vapour Deposition or spin-on coating. Also, we use highly selective post-deposition treatments such as UV –curing to modify their structure in a controlled fashion. The glass short-range structure and bonding type are studied by means of solid state Nuclear Magnetic Resonance (29Si and 13C spectra) combined to Fourier Transform Infra-Red spectroscopy. Compositional analysis is performed with Elastic Recoil Detection. Elastic properties are retrieved through nanoindentation and acoustic techniques such as Surface Acoustic Waves and Brillouin Light Scattering. Fracture properties are evaluated in four-point bending and double cantilever beam geometries, and thermal conductivity is evaluated with the 3-omega method [1]. Thermal stability of the films is also compared.It is found that besides the already well-known dependence of most thermo-mechanical properties on mass density [2], for a given density also the degree of matrix connectivity [3] and the predominant type of silica bonds [4] have significant impact on such film properties. In terms of fracture it is also observed that a substantial increase in the elastic modulus of an organosilicate glass film does not necessarily correspond to an enhancement of its cohesive strength. Cohesive strength appears most sensitive to the changes in silica bond type. [1] D.G. Cahill and R.O. Pohl, Phys. Rev B 35 (1987) [2] M.F.Ashby, Proc.R.Soc.Lond. A 454, 1998.[3] A.Ross, K.K.Gleason, J.Appl.Phys. 97, 113707, 2005.[4] F.Iacopi et al., proceedings of the Advanced Metallization Conference, Sept. 27th-29th, Colorado Springs, Co., 2006.
12:00 PM - F1.6
Film Characterization of Ultra Low-k Dielectrics Modified by UV Curing with Different Wavelength Bands.
Masazumi Matsuura 1 , Kinya Goto 1 , Noriko Miura 1 , Shinobu Hashii 2 , Koyu Asai 1
1 , Renesas Technology Corp., Itami Japan, 2 , Renesas Semiconductor Engineering Corp., Itami Japan
Show AbstractRecent challenges to Ultra Low-k (ULK) integration for Cu interconnects reveal that degraded mechanical strength of ULK causes undesirable issues such as Low-k voiding, metal penetration and fatal delamination failure in CMP and packaging. UV curing is a promising approach to the hardening of ULK-SiOC (k=2.6, E=8GPa). The key to UV curing is the optimized UV wavelength band for ULK dielectrics. In this study, SiOC films modified by UV curing with different wavelength bands are characterized by Solid-state NMR spectroscopy and Raman spectroscopy. Two types of UV lamps (Lamp(I) and Lamp(II)) were used for UV curing. The wavelength band of Lamp(I) is lower than that of Lamp(II), that is, Lamp(I) generates higher photon energy. UV curing with Lamp(I) and Lamp(II) increase the elastic modulus of ULK-SiOC films to 14Gpa and 11GPa, respectively. 29Si Solid state magic angle spinning NMR spectroscopy is a powerful tool to analyze the change of the first-order molecule and network structure in SiOC films. From the first-order molecule structure analysis, Lamp(I) generates Si-H groups (TH,DH) which is undetectable in the pristine ULK-SiOC, while Lamp(II) enhances Si-O group (Q). These results indicate that Lamp(II) prefers to Lamp(I) in terms of enhanced Si-O crosslinking to ULK-SiOC. Relaxation time T1 for 29Si nucleus is available for the analysis of Si-O molecule motility in the Si-O network of UV modified SiOC films. UV curing with both lamps reduces T1, which indicates that UV curing increases Si-O molecule motility in Si-O network. This result is inconsistent with the first-order molecule structure analysis which shows enhanced Si-O crosslinking. Raman spectroscopy analysis was employed to characterize the change of chemical bonding structure in UV modified SiOC films. Raman spectra in the case of Lamp(I) show that UV curing with Lamp(I) increases Si-H bond, which is consistent with NMR spectroscopy analysis. In addition, UV curing with both lamps generates different chemical bonds corresponding to amorphous carbon structure. Long-time UV curing causes strong fluorescence which disturbs Raman spectroscopy measurement. These results indicate that UV curing generates aliphatic hydrocarbon groups. In conclusion, NMR spectroscopy analysis reveals that Lamp(II) is preferable for UV curing modification of ULK-SiOC in terms of enhanced Si-O crosslinking. In contrast, T1 for 29Si nucleus and Raman spectra show that UV curing increases Si-O molecule motility in Si-O network and generates amorphous carbon structure corresponding to aliphatic hydrocarbon groups. The further investigation will be needed to discuss the impact of UV curing modification on ULK integration issues, such as etch/ash plasma damage and wet damage.
12:15 PM - F1.7
Fracture Property Improvements of a Nanoporous Thin Film via Post Deposition UV Curing.
Jeannette Jacques 1 , Ting Tsui 1 , Andrew McKerrow 1 , Robert Kraft 1
1 Silicon Technology Development, Texas Instruments, Inc., Dallas, Texas, United States
Show AbstractOrganosilicate glass (OSG) materials have emerged as the predominant choice for intermetal dielectrics in advancing technology nodes of 90 nm and beyond. A potential failure mechanism for this class of low-k dielectric films during the manufacturing process is catastrophic fracture due to channel cracking. The driving force for channel cracking is dependent upon several film properties, including the plane strain modulus, volumetric density, and residual stress. To improve the mechanical strength and stability of these silicon-based materials, the use of post-deposition curing processes is under evaluation. Within this work, the effects of UV curing upon the structure and mechanical properties of OSG films were characterized. Data are reported for a set process temperature of 400oC and UV exposure times ranging from 0 minutes to 7 minutes. OSG thin films were deposited on bare (100) silicon wafers at a thickness of 1.3 μm and k value of ~ 2.6 via plasma enhanced chemical vapor deposition. Nano-indentation measurements were conducted at a depth of 68.5 nm, representing less than 10% of the total film thickness and therefore minimizing any potential substrate effects. After UV curing, film hardness and elastic modulus are improved according to power law functions, with no measurable increase in the residual tensile film stress. For a UV exposure time of 5 minutes, the film hardness increased by approximately 26% and the resultant elastic modulus increased by 47%. The average film density, as determined by Rutherford Backscattering analysis, was observed to increase linearly as a function of UV exposure time. The average volumetric film density rose by 5% in specimens cured for 5 minutes, correlating well with measured film shrinkage data. Channel crack propagation velocities were observed to decrease as a power law function of UV exposure time. The UV cure process facilitates a 2.5 order of magnitude decrease in channel cracking rates, as compared to as-deposited OSG films. Crack susceptibility is only improved by a factor of 4X when the UV exposure time is increased from 3 minutes to 7 minutes. FTIR spectral analysis was used to characterize structural molecular film changes as a result of the UV cure process. The Si-O-Si bond population was observed to increase as a function of UV exposure time, however, the ratio of individual bond types within the spectral band was not altered. The area of the Si-O-Si band increased by 9% after UV curing for 7 minutes, as compared to uncured films. No measurable changes in the Si-H or Si-(CH3)X bond populations resulted from UV curing. The improvements in the mechanical properties of these OSG thin films are believed to correlate with the increasing Si-O-Si bond population. Si-O bonds are the most robust structures comprising OSG materials and can have a significant impact on mechanical stability. Comparisons between post-deposition UV and Electron Beam curing processes are also provided.
12:30 PM - F1.8
Characterization of Chemical Bonding in Low-K Dielectric Materials for Interconnect Isolation: A XAS and EELS Study.
Patrick Hoffmann 1 , Dieter Schmeisser 1 , Ehrenfried Zschech 3 , Hans-Juergen Engelmann 3 , Franz Himpsel 2 , Heiko Stegmann 4 , Jonathan Denlinger 5
1 Applied Physics II, Brandenburg University of Technology Cottbus, Cottbus, Brandenburg, Germany, 3 , AMD Saxony LLC & Co KG, Dresden, Saxony, Germany, 2 , University of Wisconsin / Madison, Madison, Wisconsin, United States, 4 , Carl Zeiss NTS GmbH, Oberkochen Germany, 5 , Advanced Light Source, Berkeley, California, United States
Show AbstractThe use of low dielectric constant materials in the on-chip interconnect process reduces interconnect delay, power dissipation and crosstalk noise. To achieve the requirements of the ITRS for 2007-2009 minimal sidewall damage from etch, ash or cleans is required. In chemical vapor deposited (CVD) organo-silicate glass (OSG) which are used as intermetal dielectric (IMD) materials the substitution of oxygen in SiO2 by methyl groups (-CH3) reduces the permittivity significantly (from 4.0 in SiO2 to 2.6-3.3 in the OSG), since the electronic polarizability is lower for Si-C bonds than for Si-O bonds. However, plasma processing for resist stripping, trench etching and post-etch cleaning removes C and H containing molecular groups from the near-surface layer of OSG. Therefore, compositional analysis and chemical bonding characterization of structured IMD films with nanometer resolution is necessary for process optimization. OSG thin films as-deposited and after plasma treatment are studied using X-ray absorption spectroscopy (XAS) and electron energy loss spectroscopy (EELS). In both techniques, the fine structure near the C1s absorption or energy loss edge, respectively, allows to identify C-H, C-C, and C-O bonds. This gives the opportunity to differentiate between individual low-k materials and their modifications. The O1s signal is less selective to individual bonds. XAS spectra have been recorded for non-patterned films and EELS spectra for patterned structures. The chemical bonding is compared for as-deposited and plasma-treated low-k materials. The Fluorescence Yield (FY) and the Total Electron Yield (TEY) recorded while XAS measurement are compared. Examination of the C 1s near-edge structures reveal a modified bonding of the remaining C atoms in the plasma-treated sample regions.
12:45 PM - F1.9
Ultra Low-k Film Deposition by PEVCD Using a Novel Organosilane as a Precursor
Yonghua Xu 1 , Ikuyo Muramoto 1 , Masato Ishikawa 1 , Hideaki Machida 1
1 , Tri Chemical Laboratories Inc., Uenohara, Yamanashi Japan
Show Abstract The use of low dielectric constant (Low-k) or ultra low-k dielectrics are required in advanced ULSI with technology nodes of 65 nm and beyond, to reduce the RC time delay and cross-talk. Up to now, many kinds of low-k films prepared by PECVD or spin coating have been reported, but the most suitable candidate for future ULSI still has not been developed. In fact, films with the two opposite properties of low k (<2.4) and high mechanical strength (elastic modulus >8 GPa) have not been developed yet. These two properties are required in ULSI technology at the same time. At this report, we will investigate films prepared with three different precursors, and will discuss the influence of the functional groups in the precursors on k and mechanical strength. The three precursors used are dimethyldimethoxysilane (DMDMOS), diisopropyldimethoxysilane (DiPDMOS), and dicyclopentyldimethoxysilane (DcPDMSO), which have one, three, and five carbon atoms in the functional group, respectively. Films were prepared by PECVD at various experimental conditions. The lowest k for DMDMOS, DiPDMOS, and DcPDMOS films are 2.72, 2.65, and 2.22, respectively. This indicates that k decreases as the carbon atom number increases in the functional group. On the other hand, the elastic modulus for all of the films is larger than 8 GPa. FT-IR spectra show that CHx composition and the component of carbon atoms in C-C chains in the films increase with the increase of the carbon atom number. We consider that these facts contribute to the low permittivity of DcPDMOS films. Furthermore, the influences on k of each experimental parameter, such as precursor flux, plasma power, and chamber pressure are also discussed. In this research, we also studied the effect of UV cure. It is found that k is reduced about 13% after 90 s of UV irradiation, although no effect on the mechanical strength was observed.
F2: Reliability of Low-k Dielectrics
Session Chairs
Tuesday PM, April 18, 2006
Room 3009 (Moscone West)
2:30 PM - **F2.1
Reliability of Interconnect Dielectrics.
Gaddi Haase 1
1 SiTD, Texas Instruments, Dallas, Texas, United States
Show AbstractInterconnect systems in modern integrated circuits carry electrical signals in typically 5-8 levels of metal, with line-to-line spacing < 100 nm and with a total minimum-pitch line length > 100 m. The metal wiring is supported/surrounded by low dielectric constant (low-k) materials generally with relatively low electrical and mechanical strength. Also, numerous interfaces are introduced because of the various barrier and capping layers that are used during interconnect processing. Integrating these new materials and interfaces into a very reliable network is a challenge for the reliability engineer. Therefore, dielectric degradation mechanisms must be carefully evaluated when ensuring the expected lifetime for the entire interconnect system. This reliability assurance is further exacerbated by complications that often arise from the difficulties in accurate testing and measurements because of the high variability in critical dimensions and material composition introduced by the various process steps. Much of the existing literature cites the cause of interconnect dielectrics failures as due to Cu extrusion or Cu-ion drift. However, often, from post time-dependent dielectric breakdown (TDDB) failure-analysis, it is very difficult to extract whether the free Cu (unconfined Cu due to a disruption in barrier and/or capping layer) was the cause or an effect of the dielectric breakdown process. Generally, the dielectric failure is very destructive because of the high voltages required to test interconnect dielectrics. In this presentation, we will discuss various models and avenues for interconnect dielectric breakdown. We will present a methodology for overcoming many of the line-to-line spacing variations that routinely interfere with interconnect dielectric-breakdown accelerated testing.The characteristics of line-to-line dielectric breakdown for a good interconnect system, with no loose copper, will be compared to a system with an intentionally leaky Ta-based barrier. We will show the effect of baking in a case of a leaky barrier, and how no loose Cu results in a very little to no temperature dependence for the dielectric breakdown parameters. Finally, the effect of dielectric liners and trap-charging on the possible spatial distribution of the electric field between metal-lines, and its effect on the dielectric degradation, will be discussed.
3:00 PM - F2.2
Detection of Copper and Water in low-k dielectrics by Triangular Voltage Sweep measurements.
Ivan Ciofi 1 , Zsolt Tokei 1 , Marco Saglimbeni 1 , Marleen Van Hove 1
1 , IMEC, Leuven Belgium
Show AbstractIn the attempt to further reduce the interconnect RC delay, porous low-k dielectrics are being actively tested in combination with Cu for advanced interconnect schemes. It is known that the use of porous materials presents a few process challenges. In particular, pores make the material prone to water absorption, which affects both performance and reliability of back end-of-line (BEOL) structures. Time Dependent Dielectric Breakdown (TDDB) tests are commonly used to predict the lifetime of interconnect schemes at user conditions: the time-to-failure is extrapolated from those obtained under different Bias Temperature Stress (BTS) conditions. However, the failure mechanisms associated with Cu and water are not yet fully understood. Besides, in TDDB tests it is often necessary to overstress the investigated structures in order to make them fail in a reasonable time. In this case the applied electric fields may be much higher than those expected at user conditions, which makes the validity of the related predictions questionable. In this work, we evaluated the Triangular Voltage Sweep (TVS) method as a possible low electric field technique for addressing degradation mechanisms that occur in Cu/low-k structures. A set of dedicated MIS (Metal-Insulator-Semiconductor) planar capacitors were fabricated in order to investigate the effects of Cu and water in low-k materials. The low-k dielectric was an OSG material (porosity=7%, k=3.0) on top of which Cu was directly sputtered. Wet etch was then performed for defining the gate electrodes. The deposition of any Cu or water barrier for the dielectric was intentionally omitted in order to induce Cu contamination and water absorption and systematically study the associated effects. Al gate samples were fabricated as a reference. On the Cu samples, Cu ions were indeed detected after BTS at 1MV/cm and 190°C. However, on both Cu and Al samples we also detected another ionic specie, which we were able to relate with the presence of water. Our experiments show that water absorbed in low-k materials behaves as a source of ions. The experimental evidences we collected lead us to conclude that these are protons generated by the electrical decomposition of water, induced by the applied electric field. Correlation with the CV method is demonstrated. Furthermore, we were able to resolve distinctive features in the TVS traces related to Cu+ and protons, respectively. We demonstrate that these features can be used to distinguish the two ionic species. As a result, we provide a methodology that can be used to detect and distinguish Cu and water in porous dielectrics. The methodology was also used to compare the effect of different plasma treatments on the same OSG material with respect to material permeability and resistance to copper penetration. TDDB measurements were performed on the same samples and an excellent correlation with TVS results was found.
3:15 PM - F2.3
Suppression of Moisture-induced Electrical Instabilities in Mesoporous Silica Films Through Molecular Capping.
Amit Singh 1 , Darshan Gandhi 1 , Victor Pushpraj 1 , G. Ramanath 1
1 Materials Science & Engineering, Rensselaer Polytechnic Institute, Troy, New York, United States
Show AbstractIntroducing porosity into insulating materials is a promising strategy to decrease the dielectric permittivity to minimize resistance-capacitance (RC) delays in microdevice wiring. However, the resultant high surface area and high pore fraction in meso-porous silica (MPS) bring with them a high susceptibility to moisture uptake. Thus, it is essential to understand the mechanisms of, and obviate, such deleterious effects through control over pore-surface chemistry.Here, we first reveal the mechanisms of moisture-uptake-induced electrical property degradation, followed by a solution to suppress degradation. Capacitance voltage (C-V) characteristics of Al/MPS/Si(001) capacitors exposed to temperatures below 200 °C reveal flat-band shifts, hysteresis, increased leakage and permittivity. Infrared spectroscopy measurements indicate that these changes are due to interaction of moisture with the pore surfaces. Kinetics analyses reveal two thermally activated processes: proton generation through fissure of silanol bonds (activation energy Ea1 = 0.42 ± 0.04 eV) and proton-induced depassivation of dangling bond traps (Ea2=0.54 ± 0.05 eV) at the MPS/Si interface. Incorporation of organosilane molecular layers into MPS completely suppresses the afore-described electrical property signatures and chemical changes. X-ray photoelectron spectroscopy, ellipsometry, and contact angle analyses of the silylated MPS films reveal that the increased stability is due to the hydrophobicity of the silylated surfaces in MPS that provide resilience to water attack. Our findings will be important considerations in designing processes for integrating MPS films into microdevices.
3:30 PM - F2.4
Morphological and Structural Evolution of an Ultra-low-k Dielectric During the Porogen Removal.
Diane Rebiscoul 1 , Helene Trouve 2 , Bruno Remiat 1 , Laurence Clerc 3 , Didier Louis 1 , Gerard Passemard 1
1 DRT/LETI/D2NT/Laboratoire Back End, CEA, Grenoble France, 2 LETI, Rohm and Haas Electronic Materials LLC, Grenoble France, 3 DRT/LETI/DPTS/SDOT , CEA, Grenoble France
Show AbstractReducing the RC delay is becoming an important challenge for high performance interconnects for sub 45nm technologies. It will require the use of low capacitance and low resistance materials such as porous ultra-low-k materials. Because of the porosity, integration of these materials can lead to mechanical polishing and barrier layer diffusion problems. In order to avoid these issues, a hybrid dense material containing a silsesqioxane matrix and a porogen, i.e. Solid First™ ILD approach proposed by Calvert and Gallagher, can be used as the integration scheme. The porogen is then removed after the metallization and CMP steps by a thermal, UV or supercritical CO2 cure in order to remove the porogen and create a porous ILD.Standard processes used during the integration can be performed at temperatures above350°C, consequently the material morphology and structure could be modified. In this investigation, we have studied the impact of the temperature and the duration of the thermal cure on a hybrid spin-on methylisesquioxane (MSQ) material. Initially we characterized the hybrid material’s morphology and structural evolution by ellipsometry, X-ray reflectometry and infra-red spectroscopy after different thermal cures. The shrinkage, weight loss, porogen loss and matrix crosslinking were assessed as a function of time and temperature of the cure. Regardless of the cure duration shrinkage, porogen loss, and weight loss are less than 10% when the cure temperature is less than 350°C. Moreover, the X-ray reflectivity of these samples shows a decrease in roughness and/or density gradient thickness at the material-substrate interface after a cure at 370°C.Secondly, in order to assess the porogen distribution and the structure of the layer as a function of the depth, the material was etched in a 0.05% HF solution during 2 or 5 min and then characterized by FTIR and ellipsometry. This operation was repeated until the etching stop. According to the temperature and time cure, the etch-rate varies as a function of the material depth. It appears that the etch-rate decreases as the matrix crosslinking and the porogen content increases.
4:15 PM - **F2.5
Effect of Water Diffusion in Organosilicate Glass Film Stacks on Adhesion
Youbo Lin 1 , Ting Tsui 2 , Joost Vlassak 1
1 Division of Engineering & Applied Sciences, Harvard University, Cambridge, Massachusetts, United States, 2 Silicon Technology Development, Texas Instruments, Dallas, Texas, United States
Show AbstractOrganosilicate glass (OSG) is utilized as an interlayer dielectric (ILD) in advanced integrated circuits. Previous studies have shown that this material is very susceptible to fracture in the presence of water molecules. We have developed a novel technique to study the diffusion of water in OSG film stacks based on fracture mechanical measurements. It is found that the fracture toughness of a film stack degrades with time exposed to water prior to fracture. This degradation is the result of water diffusion and is present even if measurements are made in an inert environment. A quantitative model is presented to predict adhesion degradation as a function of exposure time by coupling the results of independent subcritical crack growth measurements with Fick’s law. The model makes it possible to quantitatively determine the diffusion coefficient of water in the film stack. We will present data for various barrier/OSG systems and for various interface treatments.
4:45 PM - F2.6
Moisture Induced Degradation of Porous Low-k Materials.
Mikhail Baklanov 1 , David O'Dwyer 1 , Adam Urbanowicz 1 , Quoc Toan Le 1 , Steven Demuynck 1
1 SPDT, IMEC, Leuven Belgium
Show AbstractReduction of dielectric constant of silica-based films is provided by introduction of porosity and hydrophobic properties. The hydrophobicity is important because even a small amount of adsorbed water significantly increases the dielectric constant. Moisture also affects cohesive and fracture properties of low-k dielectrics. Therefore, the interaction with water is extremely important for integration of low-k films. In this paper, reaction kinetics of water vapor with porous low-k films has been evaluated using in situ ellipsometric setup that allows gradually change the water pressure from 10-3 Torr to saturated ones. The amount of the adsorbed water is calculated from the change of refractive index measured during the adsorption. The low-k materials considered for the study have porosity ranging from 30 to 50 %. Pristine low-k films reversibly adsorb 2-5% of water. This amount reflects the presence of constitutive hydrophilic centers that fairly correlate with the carbon concentration in the films. Plasma and thermal treatments increase the number of hydrophilic centers. Once the amount of these centers has reached a certain critical value sufficient to form a continuous film, bulk water condensation is observed. Our study resulted in the following observations:1.The change of the film properties during the water adsorption/desorption cycle for damaged low-k films is not completely reversible. Each additional adsorption/desorption cycle increases dielectric function of the film. The increase of dielectric function is related to a decrease of porosity, increase of the skeleton density and decrease the film thickness.2. The relative pressure corresponding to the bulk condensation allows us to calculate internal contact angle of damaged low-k materials. We will show that the internal contact angle reflects the degree of damage of the low-k films and in certain cases (high temperature and O2-containing plasma treatment) the internal contact angle becomes close to zero.3. The moisture - induced degradation has autocatalytic character. The water molecules adsorbed on separate OH groups play the role of catalyst that hydrolyses the siloxane bridges initially present on hydrophobic surface. For this reason, even slightly damaged low-k films with internal contact angle close to 90 degrees may become completely hydrophilic after few adsorption/desorption cycles. It is important that the water diffusion is not the rate limiting step. Shrinkage, densification and hydrophilisation of low-k materials that occurred as a result of interaction with moisture degrade the effective dielectric constant and mechanical properties of integrated structures.
5:00 PM - F2.7
Methodology To Determine The Toughness Of A Brittle Thin Film By Nanoindentation.
Helene Brillet-Rouxel 1 2 , Marc Verdier 2 , Muriel Braccini 2 , Michel Dupeux 2 , Stephane Orain 3
1 Mechanical and Thermal Simulations , STMicroelectronics, Crolles France, 2 , LTPCM (CNRS/INPG/UJF), Grenoble France, 3 , PHILIPS semiconductors , Crolles France
Show AbstractNanoindentation is the most convenient method to determine the mechanical properties of thin films. This approach is applied to bulk silicon and dielectric thin films (porous and non-porous) on silicon substrate. After determining Young’s moduli and hardness for the materials of interest with a Berkovitch indentor, we generate reproducible stable cracks from the edges of a cube corner indentor. The shape of the crack fronts has been explored with help of Focused Ion Beam (FIB) cross-sections on bulk silicon as a reference material. The validity of theoretical models [1] used to estimate the toughness from crack lengths has been verified on these reference cases.To calculate the toughness of thin film on silicon substrate, we first established the loading range in which the cracks only affect the thin film without substrate damage. Thanks to cross-section views obtained by FIB, we note that the surface radial cracks shape presents two regimes according to the applied load (i) the cracks have a half-penny semi-circular shape as long as their visible length on film surface is smaller than twice the film thickness. (ii) when the crack length is larger than twice the film thickness, their shape tends to a semi-elliptic contour, limited by the film/substrate interface. Several corrective terms have been introduced to the classical toughness estimation formula to take into account these various crack shapes, the proximity of the film/substrate interface and the residual stress pre-existing in the film. Results obtained as well for bulk silicon as for dielectric thin film are in good agreement with literature.[1] BR Lawn, TR Wilshaw. J Mater Sci 1975;10:1049
5:15 PM - F2.8
Supercritical Carbon Dioxide Process to Improve Dielectric and Mechanical Properties of Porous ULK Thin Films.
Julien Beynet 1 , Vincent Jousseaume 2 , Alain Madec 1 , Bruno Remiat 2 , Regis Mercier 3 , N. Dominique Alberola 3 , Gerard Passemard 4
1 , AIR LIQUIDE, Jouy-en-Josas France, 2 , CEA/LETI, Grenoble France, 3 , LMOPS, Le Bourget du Lac France, 4 , STMicroelectronics, Crolles France
Show AbstractSpin-on glass organosilicate films are promising Ultra Low K (ULK) candidates in which porosity can be created by incorporating thermally labile porogens. The as deposited film (a.k.a., hybrid film) consists of a methylsilsesquioxane (MSQ) matrix and an organic porogen. However, thermal annealing at 450°C does not completely remove the sacrificial phase; consequently, the polymeric residue that remains is highly detrimental to the film’s dielectric constant. In order to remove the residue, a supercritical carbon dioxide (scCO2) processing step was added after the film deposition and before the thermal anneal. This additional process step led to complete removal of the polymeric residues as determined by Fourier Transform Infrared Spectroscopy (FTIR). As expected, the dielectric constant was improved from 2.5 without the scCO2 step to 2.1 with the scCO2 step. Furthermore, the breakdown voltage was greatly enhanced (4.6 MV/cm instead of 3.4 MV/cm) and leakage current was strongly decreased. The film’s mechanical properties were also improved after scCO2 processing as determined by nano-indentation and by noting an increase in the abundance of Si-O-Si bonds in the FTIR spectra. The pore size distribution of films obtained with or without the scCO2 step was compared by Ellipsometric Porosimetry (EP) analysis. Even though a two step process can successfully produce a ULK film, it is preferred to have a single processing step. So, scCO2 was studied in a single-step process for removing the porogens from hybrid films. Selective porogen extraction by scCO2 was established using FTIR analysis of the chemical bonds in the films. Porosity generation was assessed by spectroscopic ellipsometry and pores structure was studied by EP. The impact of process parameters are currently under investigation (pressure, temperature, additives, CO2/additive ratio, duration of exposure, mass flow…) and will be discussed. The impact of material characteristics (thickness, porogen type, porogen loading) will be explored to study matrix behaviour and fluid penetration into the hybrid film. In depth work is on-going to understand extraction mechanisms.
5:30 PM - F2.9
Mechanics and Fracture of Low-k Organosilicate Thin Films: Effects of UV Curing.
David Gage 1 , Eric Guyer 1 , Reinhold Dauskardt 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States
Show AbstractUltra-violet (UV) radiation curing has emerged as a promising technique for enhancing the glass network structure and mechanical properties of organosilicate thin films, while simultaneously preserving their low dielectric constant (k) value. In the present work, we examine the effects of UV curing on the adhesive and cohesive fracture properties of carbon-doped oxide (CDO) low-k thin films. Detailed NMR studies were employed to characterize the effects of UV cure on glass structure. The UV curing process is demonstrated to significantly improve interfacial fracture energies, as measured by the four-point bend technique. The interfacial fracture energies of UV treated films were found to be as much as 45% higher than those of untreated films. However, an interesting finding is that UV curing does not lead to similar improvements in the films’ cohesive strength or their resistance to environmentally-assisted cracking in humid environments, as measured by the double cantilever beam method. For example, while fracture energies on both sides of the CDO layer were found to increase, no change in the cohesive fracture resistance was observed for k = 3.0 and k = 2.5 films after UV cure. This unexpected behavior poses a challenge to the efficacy of the UV curing process in reducing the propensity for cracking in a given environment. Possible mechanisms responsible for the observed behavior are proposed and discussed.
5:45 PM - F2.10
Critical and Sub-critical Debonding in Nano-clustering Porous Low-k Films.
Ryan Smith 1 , Chihiro Uchibori 2 , Paul Ho 1
1 Laboratory for Interconnect and Packaging, The University of Texas, Austin, Texas, United States, 2 , Fujitsu Laboratories of America, Inc., Sunnyvale, California, United States
Show AbstractVery few porous low-k dielectric materials meet the basic requirements for integration into the back end of the line (BEOL) metallization. According to the International Technology Roadmap for Semiconductors, 2005, candidates for the 45 nm node need a k<2.2 and a minimum adhesion strength of 5 J/m^2. Recently, a low-k dieclectric material was developed, called nano-clustered silica (NCS). It is a spin-on glass with k<2.3. Unlike many CVD films that use template poragens, NCS is constitutively porous, with a micro- and mesopore size of ~2.8 nm. The first reported adhesion strength of this material was 10+ J/m^2. The large adhesive strength could be attributed to molecular structure or mechanical stablity. In this work, we investigated the nature of the adhesive strength of NCS by critical and sub-critical fracture and FTIR. The four-point bend technique and a mixed-mode double cantilever beam technique were employed. The sub-critical crack growth studies were performed in humid environments and ambient temperatures. Different post-treatments were used on NCS to achieve different molecular structure, as measured with FTIR. A correlation between FTIR spectra or molecular structure and critical adhesion energy was found. Atomistic parameters were calculated from the sub-critical crack growth data. A dependency of fracture behavior on post-treatment and, therefore, structure was observed.
F3: Poster Session I
Session Chairs
Gaddi Haase
Mark O'Neill
Joost Vlassak
Wednesday AM, April 19, 2006
Salons 8-15 (Marriott)
9:00 PM - F3.1
Modelling of Thermal Conduction Mechanisms in Amorphous Inter-layer Dielectrics (ILDs).
Manu Shamsa 1 , Patrick Morrow 1 , Shriram Ramanathan 1
1 Components Research, Intel, Hillsboro, Oregon, United States
Show AbstractPorous dielectrics are presently being intensively researched for integration into interconnect architectures in high-performance nano-electronic devices. The thermal conductivity of such dielectrics tend to be lower than that of a-SiO2 thereby leading to higher temperatures in the embedded metal interconnect lines for the same current density. Such a temperature rise can lead to undesirable reliability issues in the interconnect layers. Thus, an understanding of thermal transport in such materials is important in the selection of suitable dielectrics and also the interconnect design rules. It is also interesting to study thermal properties of amorphous dielectrics owing to their disordered structures and understand basic mechanisms involved in heat conduction from a scientific point of view. In this paper, phonon transport in amorphous dielectrics has been investigated theoretically to model thermal conductivity as a function of temperature. The modeling results have been compared with reported experimental data for various amorphous materials and also with the Cahill-Pohl thermal conductivity model. We have adopted the phonon hopping model developed by Braginsky et.al. [1] and modified it suitably to account for nano-structures typically found in these dielectrics. A network of hopping resistances has been envisaged for the disordered materials and heat conduction problem is treated as the hopping of localized short-wavelength phonon states. The model shows good agreement with experimental data published in literature for wide variety of amorphous materials including SiO2, and other glasses. A value for the hopping integral has also been extracted using this model which was found to be nearly constant for almost all the dielectrics we have investigated. We have also calculated thermal conductivity of porous dielectrics using this approach and compared with experimentally determined values. The model indicates that hopping of localized phonons is a dominant transport mechanism for heat. The model has also been applied to predict the effect of porosity on thermal conductivity. References: 1. L. Braginsky et al. Phys. Rev. B, 70, 134201, 2004.
9:00 PM - F3.10
Synthesis and Characterization of Nanoporous Ultralow Dielectric Films by Dual Porogen Approach
Jae Hwan Sim 1 , Hyun Wook Ro 2 , Hee-Woo Rhee 3 , David W. Gidely 4 , Do Yeung Yoon 1
1 Department of Chemistry, Seoul National University, Seoul Korea (the Republic of), 2 Polymer Division, National Institute of Standards and Technology, Gaithersburg, Maryland, United States, 3 Department of Chemical Engineering, Sogang University, Seoul Korea (the Republic of), 4 Department of Physics, University of Michigan, Ann Arbor, Michigan, United States
Show AbstractA new method for obtaining ultralow-k (k<~2.1) films was developed in order to overcome numerous issues. At high porosities above 20 %, it is difficult to obtain isolated nanopore structure by the conventional porogen blending approach. We employed two kinds of porogens to obtain the interconnection-free nanopore structure induced by their mutual repulsion. One was chemically bonded to the matrix material by copolymerization. The other was incorporated by the blending method. As a result, ultralow-k films showed a bimodal distribution of pore sizes caused by two separate pore generation process, without interconnection between the two types of pores even at high porosities greater than 30%.
9:00 PM - F3.11
Mechanical Properties of Organosilicate Glass Coatings
Youbo Lin 1 , Ting Tsui 2 , Joost Vlassak 1
1 Division of Engineering & Applied Sciences, Harvard University, Cambridge, Massachusetts, United States, 2 Silicon Technology Development, Texas Instruments, Dallas, Texas, United States
Show AbstractOrganosilicate glass (OSG) coatings of different composition were deposited in a PECVD process using octamethylcyclotetrasiloxane (OMCTS) as a precursor. The composition and structure of the films were characterized as a function of OMCTS flow rate by means of RBS, FRES and FTIR spectroscopy. With increasing flow rate, the carbon and hydrogen content of the coatings increases, while the oxygen concentration decreases. Addition of carbon and hydrogen atoms increases the number of organic groups in the siloxane network and lowers the density of the coatings. It is evident that as more carbon and hydrogen atoms are incorporated into the coatings, the siloxane network is more frequently interrupted by terminal methyl (CH3-) and hydrogen (H-) groups. These structural changes impact the fracture toughness and stiffness of the films so that both are much lower than for amorphous silica. We quantitatively correlate the fracture toughness and stiffness of the OSG to the structure of the films. A mean connectivity number based on bond coordination is defined and used to describe the relationship between the stiffness and structure evolutions. The fracture toughness has been found well correlated to the terminal/networking bond ratios.
9:00 PM - F3.12
Ordered Hydrophoic Mesorpous Furionated Silica Thin Film
Mingming Du 1 , Denis Mueller 2 , Phil Matz 3 , Smith Casey 1 , Pawan Nerusu 1 , Richard Reidy 1
1 Materials Science and Engineering, University of North Texas, Denton, Texas, United States, 2 Physics Department, University of North Texas , Denton, Texas, United States, 3 Silicon Technology Development, Texas Instruments Inc, Dallas, Texas, United States
Show AbstractNovel well ordered fluorinated mesoporous silica thin films derived from triethoxyfluorosilane (TEFS ) have been developed using a one step spin-on process. The mesoporous structure was created by the addition of triblock polymers. After heat treatments to remove the porogen and supercritical carbon dioxide silylation processing, these films exhibit improved mechanical properties, ultra-low dielectric constant, hydrophobicity, and unusual microstructure. Fourier transform infrared spectrophotometry and XPS indicates the presence of some fluorine in the silica structure. Nanoindentation studies show high elastic moduli and hardnesses. The ordered mesoporous structure is verified by transmission electron microcopy and the nitrogen adsorption analysis. The electronic measurements show low dielectric constants well below 2.5. The effects of processing, pH value, solvent choice on film properties are discussed. Furthermore, the ordered porosity, corresponding dielectric properties and mechanic properties, can be controlled by adjusting the porogen amount. The pore diameter can also be controlled in some degree. It is the goal of this research to optimize these properties of mesoporous fluorinated silica thin films through tailoring the fluorinated silica matrix and the porogen-induced porosity. To determine the impact of fluorine in the silica matrix development, mesoporous tetraethoxysilane (TEOS)-based films have been synthesized. These films have been characterized using FTIR, differential thermal analysis, ellipsometry, HRTEM, dynamic secondary ion mass spectrometry (DSIMS) and X-ray photoelectron spectroscopy(XPS).
9:00 PM - F3.13
Effects of Solution Chemistry on Fracture of Nanoporous Low-k Thin-Films.
Nathan Stein 1 , Reinhold Dauskardt 1
1 Materials Science and Engineering , Stanford University, Stanford, California, United States
Show AbstractThe reliable fabrication of interconnect structures containing nanoporous low-k thin-films has been limited due to their fragile nature and susceptibility to stress corrosion cracking in reactive processing environments, such as chemical mechanical planarization (CMP). Here we demonstrate the effect of aqueous solution chemistries on crack velocity in methylsilsesquioxane (MSSQ) thin-films. In general, crack growth is inhibited by acidic solutions and enhanced by basic solutions as characterized using fracture mechanics based test configurations. We describe the interaction and underlying reaction kinetic processes that dictate the effect of solution chemistries on the characteristics of crack growth. We also demonstrate that the process of channel cracking may be significantly compromised by the test environment. For example, systematic trends are often not observed with respect to solution pH in buffered or non-buffered solutions. We show that since channel cracking is dependent on the stress state and elastic properties of the film, significant changes in the crack velocity may result from uncertainties in the crack driving force. These may be associated with diffusion of the solution into the MSSQ film, which can alter the film stress state. These effects together with the fundamental chemical interaction of the environment and low-k film are used to elucidate the factors that control the reliable processing of thin-film structures containing Cu and low-k materials.
9:00 PM - F3.14
Cu Via Filling Behavior and Electrical Characteristics of the 3D Cu Interconnects for Chip Stack Package
Kwang-Yong Lee 1 , Teck-Su Oh 1 , Tae-Sung Oh 1
1 Materials Science and Engineering, Hongik University, Seoul Korea (the Republic of)
Show AbstractRecently, chip stack package where Si chips are stacked in a single package has drawn much attention as a new electronic packaging technology to fulfill the ever-increasing demands for smaller, lighter and thinner electronic products. Besides significant size and weight reductions, chip stack package has advantages such as higher electrical performance, more device functions per unit area of board, and reduced processing cost. Chip stack package has been processed by assembling Si chips in stack and wire-bonding the I/O pads of each Si chip to substrate pads. However, wire-bonding in such package may deteriorate high frequency characteristics and hinder further size reduction. To overcome such limitations caused by wire-bonding in chip stack package, 3D interconnection between stacked Si chips has been proposed with Cu filling of via holes formed through Si chips. In this study, 3D Cu interconnection structures for chip stack package were fabricated by Cu metallization, Cu via filling, and Cu bump formation with electrodeposition process. Cu filling behavior into via holes in Si chip was evaluated with variations of electrodeposition parameters such as electroplating current mode, density, and additives. Microstructure and electrical properties of the 3D Cu interconnects were characterized. Using specimens of daisy chain structure, resistance for a Cu via of 75μm diameter and 90μm height was evaluated as 2.3 mΩ.
9:00 PM - F3.15
Low-Temperature Wafer Bonding of PETEOS-to-PETEOS Using Ti as Intermediate.
Jian Yu 1 , Richard Moore 2 , Hui-Feng Li 1 , Sang-Hwui Lee 1 , J. McMahon 1 , Jian-Qiang Lu 1 , Ronald Gutmann 1
1 , Rensselaer Polytechnic Institute, Troy, New York, United States, 2 , University at Albany-SUNY, Albany, New York, United States
Show AbstractWafer-level monolithic three-dimensional (3D)interconnection holds great promise to enhance performance and functionality while reducing form-factor and manufacturing cost for future generation integrated circuits. Bonding of pre-processed device wafers at back-end-of-the-line (BEOL) compatible temperatures is an attractive approach to implement such 3D interconnection. Among various technologies being evaluated, bonding of low-temperature chemical-vapor deposition (CVD) oxide is of great interest, as post-metallization Si device wafers are often encapsulated in a stack of nitride and oxide (e.g., plasma-enhanced tetraethylorthosilicate (PETEOS)). In this paper, we demonstrated PETEOS-to-PETEOS wafer bonding at T≤450°C, using a thin layer of titanium (Ti) as bonding intermediate. The bonding strength was evaluated qualitatively using a series of mechanical integrity tests (razor blade insertion, backside thinning and dicing test), while the bonding interface was examined by Auger electron spectroscopy (AES). The strong adhesion achieved is attributed to a reduction reaction at the Ti/SiO2 interface. Potential issues such as oxygen redistribution into Ti interlayer as a result of the interfacial reaction will be discussed.
9:00 PM - F3.2
Structures and Properties of an Ultra-Low-k Material: Classical Molecular Dynamics and First-Principles Calculations.
Jiro Ushio 1 , Tomoyuki Hamada 2 , Takahisa Ohno 1 2 , Shin-Ichi Nakao 3 , Manabu Kato 3 , Katsumi Yoneda 3 , Nobuyoshi Kobayashi 3
1 Computational Materials Science Center, National Institute for Materials Science, Tsukuba, Ibaraki, Japan, 2 Collabolative Research Center of Frontier Simulation Software for Industrial Science, Institute of Industrial Science, University of Tokyo, Meguro-ku, Tokyo, Japan, 3 , Semiconductor Leading Edge Technologies, Inc., Tsukuba, Ibaraki, Japan
Show AbstractAn use of low-k dielectric materials with Cu interconnects has been required for manufacturing high-performance SoC (System on Chip) LSI. To meet the demands, a trade-off between lower dielectric constant and better mechanical property must be resolved. The aim of this study is to make material design of low-k dielectrics possible by clarifying a relation between structure and property of low-k dielectrics. In the present computer simulation, we obtained for the first time the atomistic structure of an ultra-low-k material called porous carbon-doped oxide (p-SiOC; k=2.55), which has been intensively developed for SoC applications. Using the structure, a mechanism of mechanical improvement in p-SiOC film by ultraviolet (UV) irradiation was investigated. Three-dimensional periodic structure of p-SiOC was assumed to perform classical molecular dynamics (MD) calculation. We considered p-SiOC to be formed by connecting three kinds of components (Si sites); SiO3CH3, SiO3H, and SiO4 to each other with Si-O-Si bonds between the Si atoms. Assuming a several mixing ratios of Si sites so as to reproduce the elemental composition of p-SiOC, the candidate structures were generated by constant pressure MD calculations. The number of atoms in a unit cell was around 70. Among the candidate structures, we selected the most probable structure which satisfies three conditions: (1) the density is close to the experimental value, (2) the Young’s modulus is close to the experimental value, (3) the difference between the maximum and minimum of Si-O bond lengths in the unit cell is around 0.05 Å. Thus we got only two structures, both consisting from 10 SiO3CH3 sites and 3 SiO4 sites.As already known, the lattice contribution to the dielectric constant is important to understand the behavior of dielectric constant of p-SiOC due to UV irradiation (UV cure). The first-principles calculation, which can quantitatively evaluate lattice dielectric constant, is essential for dielectric constant analysis of low-k materials. We calculated dielectric constants of the two selected structures with density functional theory (DFT) and obtained results corresponding well to the experimental values. For investigation of effect of UV cure on p-SiOC properties, the p-SiOC structures modified by replacing CH3 groups with H atoms were generated by MD calculation. This UV cure model can explain the experimental results of an increase in density, Young’s modulus, and dielectric constant after UV cure.
9:00 PM - F3.3
Modeling the Impact of Layout Variation on Process Stress in Cu/Low k Interconnects.
Xiaopeng Xu 1 , Dipu Pramanik 1 , Greg Rollins 1
1 TCAD, Synopsys, Inc., Mountain View, California, United States
Show AbstractIt is well known that high stresses in local regions can result in yield or field failures ranging from dielectric cracking, metal voiding, to interface de-bonding and layer de-laminations. The stress related failures have become even more significant with the adoption of low k dielectrics materials, which have very low mechanical strength and large thermal expansion. Recent measurements reveal that the margin between average film stresses from process and dielectric material strengths has become increasingly small. So it is very important to consider the layout variation impact on process stress modulation at the early stages of layout and process design. There are two main process stress sources in metal/dielectric interconnects, the thermal mechanical stress and the intrinsic stress. The thermal mechanical stress originates from thermal expansion mismatches between various materials in an interconnect structure while the intrinsic stress is generated as a consequence of the material formation process. The actual stress profile in an interconnect structure results from the re-distribution of these stress sources satisfying the stress equilibrium conditions under local geometrical constraints. The magnitude of the stress distribution depends strongly on the local geometries that are defined by the mask layout patterns. The ubiquitous layout variations lead to very non-uniform stress distributions in the interconnect structures. However, the local layout related geometry variations have not been considered in the conventional modeling of process stress evolution. In the conventional unit cell approach for modeling of interconnect process stress, the geometrical model typically contains only one dual damascene structure consisting of a bottom dielectric layer, an M1-V1-M2 unit, and a top dielectric layer. Although some geometric effects such as line width can be studied, it is difficult to include layout variation effects using this single via chain structure. In our study, the geometrical model is expanded to include layout variations and the stress models include contributions from both the thermal mechanical stress and the intrinsic grain growth stress. Using our new methodology for layout analysis, potential high stress regions from a full chip mask layout are quickly identified using a new screening process. Geometrical models that represent the local layout variations are then automatically analyzed using full three dimensional stress analyses. In the full paper examples of representative three dimensional structures are analyzed and the process stress modulations due to the layout variations are examined. The numerical results are then compared to the observed failure modes and the implications on layout design rules are discussed.
9:00 PM - F3.4
Low-k Dielectric Obtained by Noble Gas Implantation in Silicon Oxide.
Hanan Assaf 1 , Esidore Ntsoenzok 1 2 , Marie Odile Ruault 3 , S. Ashok 4
1 , CERI-CNRS, Orleans France, 2 , LESI, University of orleans, Chartres France, 3 , CSNSM, CNRS-IN2P3, Orsay France, 4 departement of Engineering Science, Pennsylvania state university, Pennsylvania , Pennsylvania, United States
Show AbstractThermally grown SiO2 was implanted at room temperature with the heavy noble gases Ar, Kr and Xe in order to create bubbles/cavities in the oxide. The implantation energies were chosen in order to have the same implant depth for the three ions (~120nm). Our results show that these ions indeed induce bubbles/cavities in SiO2, though the cavity distribution and size are ion mass dependent. It is very important to note that bubbles/cavities formation in amorphous SiO2 has been never reported yet. Capacitance measurements show a strong decrease in the dielectric constant of the implanted SiO2 whatever the implanted ion. This technique provides k with value as low as 1.50 for as implanted samples. We are now studying the thermal evolution of k for temperatures up to 400°C.
9:00 PM - F3.5
Channel Cracking Technique For Toughness Measurement Of Sioch Low-K Films.
Helene Brillet-Rouxel 1 2 , Michel Dupeux 2 , Muriel Braccini 2 , Stephane Orain 3
1 Mechanical and Thermal Simulations , STMicroelectronics, Crolles France, 2 , LTPCM (CNRS/INPG/UJF), Grenoble France, 3 , PHILIPS semiconductors, crolles France
Show AbstractSiOCH low-k films cause reliability problems in integrated circuits due to their weak mechanical properties and brittleness. The technique of channel cracking [1] is used to study the crack growth of these materials. Different film thicknesses are produced using consecutive PECVD deposits on silicon substrates in order to determine the critical thickness for which spontaneous cracks appear. After determining mechanical properties and residual stresses of these films, samples are diced by cleavage, and subjected to a four points bending test. During the loading in ambient environment, cracks propagate from defects due to cleavage or indents confined in the film. Propagation of these cracks is observed in situ in order to correlate crack growth velocities to film thickness and stresses developed in the film due to the loading taking into account the residual stress in film. These results allow plotting crack growth rate versus stress intensity factor for a velocity varying from 10-9 to 10-4 m/s for a stress intensity in order of 0,1 MPa.m1/2. These curves can be extrapolated to sonic speed in order to estimate the film toughness. A 0,15 MPa.m1/2 toughness is thus obtained, giving a lower limit for the toughness of dielectric films tested here in an ambient environment.[1] KW McElhaney, Q Ma. Acta Mater 2004;52:3621
9:00 PM - F3.6
Thermal and Dielectric Stability of Parylene X.
Jay Senkevich 1 , Brad Carrow 1 , Pei-I Wang 2
1 , Brewer Science Inc., Rolla, Missouri, United States, 2 , Rensselaer Polytechnic Institute, Troy, New York, United States
Show Abstract9:00 PM - F3.8
Zeolite Film Properties Dependence on Particle Size.
Salvador Eslava-Fernandez 1 , M.R. Baklanov 1 , F. Iacopi 1 , S.H. Brongersma 1 , C. Kirschhock 2 , K. Maex 1
1 , IMEC, Leuven Belgium, 2 Centrum voor Oppervlaktechemie en Katalyse, K. U. Leuven, Leuven Belgium
Show Abstract9:00 PM - F3.9
The Electrical and Chemical Properties of Ultra Low-k SiOCH Film Deposited by PECVD using decamethyl-cyclopentasiloxane and cyclohexane as the Precursors.
Jaeyoung Yang 1 , Sungwoo Lee 1 , Heeyeop Chae 2 , Donggeun Jung 1
1 Physics, Sungkyunkwan University, Suwon, Kyunggi, Korea (the Republic of), 2 Chemical Engineering, Sungkyunkwan University, Suwon, Kyunggi, Korea (the Republic of)
Show Abstract
Symposium Organizers
Ting Y. Tsui Texas Instruments, Inc.
Young-Chang Joo Seoul National University
Alex A. Volinsky University of South Florida
Lynne Michaelson Vishay Electro-Films
Michael Lane IBM T.J. Watson Research Center
F4: Low-k Dielectrics: Processing and Integration Issues
Session Chairs
Francesca Iacopi
Alex Volinsky
Wednesday AM, April 19, 2006
Room 3009 (Moscone West)
9:30 AM - **F4.1
Chemical, Mechanical and Electrical Properties of Non-Thermally Cured CVD Low-k Films for a 65nm Technology.
Kurt Junker 1 , Gregory Imbert 2 , Aurelie Humbert 3 , Laurent-Luc Chapelon 2 , Yannick Le-Friec 2 , Julien Vitiello 4 , Anissa Lagha 5 , Michael Turner 1 , Michelle Rasco 1 , Cindy Goldberg 5 , Narayanan Ramani 1
1 , Freescale Semiconductor, Austin, Texas, United States, 2 , STMicroelectronics, Crolles France, 3 , Philips Research Leuven, Leuven Belgium, 4 , Philips Semiconductor, Crolles France, 5 , Freescale Semiconductor, Crolles France
Show Abstract10:00 AM - F4.2
Challenges of Ultra Low-k Dielectric Measurement and Plasma Damage Assessment.
Thomas Abell 1 , Jeffery Lee 2 , Mansour Moinpour 1
1 , Intel Corp., Santa Clara, California, United States, 2 , Intel at IMEC, Leuven Belgium
Show AbstractThe implementation of porous low-k and ultra-low k dielectrics to reduce RC delay in integrated circuit interconnect wiring has been fraught with numerous challenges. The obvious challenges of materials design and preservation of the desired electrical and mechanical properties upon subsequent processing have been significant. One problem encountered has been the damage caused to films from plasma etching and resist strip processes used to create patterned structures. Plasma damage has been implicated in the increase of effective k-values, degradation of current leakage and decreased dielectric breakdown lifetimes. Another less obvious challenge has been the metrology capability to extract useful information about the thin film structures before and after processing. It has been shown elsewhere that ionic bombardment can damage organosilicate films resulting in densification (and can induce surface sealing depending on the initial microstructure). UV-curing and e-beam treatments have also been shown to modify organosilicate bonding structures, improving mechanical properties by increasing O-Si-O crosslinking. Unfortunately, these same physical principles are the basis of many trusted metrology techniques such as Auger, SEM and TEM (both ion mill for sample prep and imaging) and thus have the possibility of damaging the films before or as they are being measured. TOFSIMS has been utilized successfully for surface analysis but challenges persist in collection of information regarding etched sidewalls where low-k properties are most desired. Some traditional non-destructive techniques, such as FTIR, have become primary methods for chemical structure analysis. Other non-damaging techniques have been employed to extract information regarding film density, thickness and porosity. X-rays are one of the favored alternate principles but others utilize non-traditional principles such as positronium annihilation and the capillary diffusion of organic solvents. Even more exotic nuclear techniques such as MAS NMR and XAFS have been investigated for low k structure analysis. The authors propose to review the challenges associated with destructive and non-destructive measurement of low k dielectric films with respect to underlying physical principles of the metrology. The vulnerability of these films to damage from fast ion and radiation damage will also be discussed in the context of post-deposition processing (including low-k cure and plasma processing). Metrology techniques, assumed to be non-destructive based on experience with dense silicon dioxide, will be discussed with regards to newer and more fragile low-k dielectric films.
10:15 AM - F4.3
The Effect of Plasma Damage on the Material Composition and Electrical Performance of Two Generations of SiOCH Low k Films.
Aurelie Humbert 1 , D Ernur 1 , R.J.O.M Hoofman 1
1 , Philips Research Leuven, Leuven Belgium
Show Abstract10:30 AM - F4.4
Tailored Repair of low-k Dielectrics Using Mono- and Di- Functional Silanes Dissolved in Supercritical CO2.
Casey Smith 1 , Richard Reidy 1 , Dennis Mueller 2 , Phil Matz 3
1 Materials Science, University of North Texas, Denton, Texas, United States, 2 Physics, University of North Texas, Denton, Texas, United States, 3 Silicon Technology Development , Texas Instruments Inc., Dallas, Texas, United States
Show AbstractContinued scaling of semiconductor devices as outlined in the ITRS roadmap requires maturation of materials with low dielectric constants. Many recent efforts have focused on the use of porous silica-based films such as methylsilsesquioxane (MSQ) and organo-silicate glass (OSG) to meet these demands. Unfortunately, exposure to oxidizing atmospheres during the ash process results in the conversion of Si-CH3 and Si-H to Si-OH damaged surface layers. The presence of these silanol moieties dramatically increases water adsorbtion and surface group polarizability which increase the film dielectric constant. Silylation reactions carried out in a supercritical carbon dioxide (SCCO2) environment have proven an effective means of replacing ash-stripped methyl groups and removing adsorbed water, thus restoring film hydrophobicity and dielectric constant, and preventing metal and organometallic precursor intrusion. Plasma chemistry and exposure time determine the silanol species distribution consisting of isolated, vicinal, and geminal sites. Recent studies have indicated that the extent of repair and surface coverage after silylation in SCCO2 is dictated by the number, type, and accessibility of silanol sites and their reactivity with the chosen silylating agent. As ash conditions evolve to accommodate more sensitive features and materials, the changing chemical and kinetic damage mechanisms will result in a variety of silanol distributions. Hence, to maintain the efficacy of SCCO2 repair processes, it is crucial to target the specific silanol species associated with a given ash process.Mono- and di-functional silylating agents in supercritical CO2 were utilized to repair O2 ash damaged low-k MSQ and OSG films. Single, stepwise and co-silylation reactions were used to replace ash-stripped methyl groups and restore hydrophobicity and dielectric constant. Silanol distribution resulting from different ash conditions was explored and provided a metric for tailoring silylating chemistries to achieve the greatest degree of surface coverage and dielectric repair. The films were characterized with Fourier transform infrared (FTIR) spectroscopy, ellipsometry, contact angle, electrical measurements, dynamic secondary ion mass spectrometry (DSIMS), and x-ray photoelectron spectroscopy (XPS).
11:15 AM - F4.5
Evaluation of Damages and Pore-sealing Capabilities of Oxidizing and Reducing Etch Plasmas for Single and Dual Damascene Patterning of Porous Ultra-low-k Materials.
Emmanuel Ollier 1 , Mathieu Clain 2 , Robert Fox 2 , Philippe Brun 3 , Stephane Jullian 1
1 Crolles2Alliance, Philips Semiconductors Crolles R&D, Crolles France, 2 Crolles2Alliance, Freescale Semiconductors, Crolles France, 3 Crolles2Alliance, CEA-Leti, Crolles France
Show AbstractThis paper presents the evaluation of oxidizing and reducing plasmas for dry stripping and pore-sealing during patterning of interconnections in a porous Ultra low-k material. Various plasma conditions have been evaluated at M1 (single-damascene) and Mx (dual-damascene). The dual-damascene integration scheme is a TFHM (Trench First Hard Mask) architecture performed without resist plug. The following conditions have been tested: oxidizing RF plasmas at different pressures in two kinds of etch equipments, O2 microwave plasma, NH3 RF plasma. They are compared to a reference with no plasma treatment. Morphological characterization (SEM and TEM-EELS) and electrical results (capacitance, resistance, leakages, parametrical yield) are presented. M1 results show that oxidizing plasmas create a sidewall damage increasing the capacitance. Damages are localized in a thin layer when RF plasma is performed after etch, on the contrary to O2 microwave which is impacting the low-k much deeper. The modified layer induced by RF plasma treatments improves leakages. NH3 provides the best RC product mainly thanks to a low capacitance. Among all conditions, NH3 presents the best compromise in terms of capacitance, resistance and leakages.Mx results show that the RC delay is only slightly increased by O2 RF plasmas because capacitance is increased but line CDs are also slightly increased, resulting in low resistance. NH3 provides the lowest capacitance and RC product when used after dual-damascene etch. Its position in the waferflow can be optimized as best results are obtained when pore-sealing with NH3 is done after cleaning the etch polymers.
11:30 AM - F4.6
PECVD Versus Spin-on to Perform Porous ULK for Advanced Interconnects: Chemical Composition, Porosity and Mechanical Behavior.
Vincent Jousseaume 1 , Charles Le Cornec 1 , Frederic Ciaramella 1 , Laurent Favennec 2 , Aziz Zenasni 1 , Gurvan Simon 1 , Jean Paul Simon 3 , Guillaume Gerbaud 4 , Gerard Passemard 2
1 , CEA-LETI-D2NT, Grenoble France, 2 , STMicroelectronics, Grenoble France, 3 , CNRS-LTPCM, St Martin d'Heres France, 4 , CEA-DRFMC, Grenoble France
Show AbstractA new challenge for semiconductor industry is to reach the low permittivity (k<2.4) required for advanced interconnects by ITRS for the sub-65nm technology nodes. Porosity introduction in an a-SiOCH matrix is the main research field investigated. However, different issues are at the origin of the difficulty to integrate these porous materials using a conventional integration scheme. For example, due to an open and interconnected porosity, reactive gases and chemistry can easily penetrate in the porous structure and damage the porous bulk material (the most degrading processes being patterning and metal deposition). Moreover, the introduction of nanopores drastically decreases the film mechanical properties which consitutes a potential issue for Chemical Mechanical Polishing and packaging. Two techniques are used to deposit these dielectric thin films: spin-on or Plasma Enhanced Chemical Vapor Deposition (PECVD). On one hand, the supporters of PECVD low k materials claim that such films exhibit better mechanical properties than the spin-on deposited films. On the other hand, spin-on dielectrics such as nanoclusters are presented to have closed pore cells which allows to avoid metallic precursor diffusion during CVD or ALD barrier deposition.In this work, different porous a-SiOCH thin films (k close to 2.2 – 2.3) were investigated. Several synthesis ways were used to deposit these a-SiOCH layers: by porogen approach, self assembling or nanoclustering techniques for spin-on, and using a porogen approach for PECVD. The compositions of all studied films were similar, the carbon content being close to 20%. Impact of deposition process and curing on material crosslinking were investigated using FTIR analysis, solid NMR and spectroscopic ellipsometry. It is shown that, whatever the deposition technique, the ULK films skeleton is mainly made of Si-O-Si bonds with methyl groups linked to silicon. The films elastic properties determined by using nanoindentation can be correlated to the Si-O-Si concentration in the porous film. This means that, for a given density, the material crosslinking mainly governs the film elastic properties independently of the deposition technique used. Porosity was measured using ellipsometric porosimetry (EP) and Grazed Incidence Small Angle X-ray Scattering (GISAXS). PECVD films prepared using a porogen approach reveal pore diameters lower than those observed for porous films deposited by spin-coating (lower than 2 nm). Finally, all porous ULK present an open pore structure (even nanoclusters). However, Rutherford Back Scattering (RBS) analysis on CVD metallic barrier deposited on the porous dielectrics show that diffusion is less pronounced in case of small pore size such as those obtained by PECVD.
11:45 AM - F4.7
Fracture Properties of Porous MSSQ Films: Impact of Porogen Loading and Burnout.
Markus Ong 1 , Vincent Jousseaume 2 , Sylvain Maitrejean 2 , Reinhold Dauskardt 1
1 Materials Science and Engineering, Stanford University, Stanford, California, United States, 2 , CEA-LETI, Grenoble France
Show AbstractCracking of nanoporous low and ultra-low-k materials presents a significant challenge for their integration. Interfacial delamination is a common mode of failure and is sensitive to interfacial bonding and chemistry. The addition of a nanotemplating porogen can alter the interfacial chemistry and consequently change the fracture energy of the interface. This work investigates the effect of porogen loading on the fracture properties of methylsilsesquioxane (MSSQ) both before and after the porogen burnout process. The fracture behavior of the hybrid porogen/matrix materials differed significantly from that of the post-burnout materials. The most notable differences were alternative fracture paths and a trend of increasing fracture energy with increasing porogen loading. The increase in fracture energies is particularly counterintuitive since other mechanical properties such as the elastic modulus and hardness measured by nanoindentation both decrease with increasing porogen content. Characterization of the fracture surfaces indicate increasing amounts of carbon at the fracture interface corresponding to the increases in fracture energy and suggest bridging porogen molecules may be responsible for this increase in adhesion. Toughening of interfaces by porogen molecules or remnants is an attractive strategy since it can be incorporated naturally with the pore creation process without requiring additional depositions or treatments.
12:00 PM - F4.8
New Spin-On Oxycarbosilane Low-K Dielectric Materials With Exceptional Mechanical Properties.
Geraud Dubois 1 , Robert Miller 1 , Willi Volksen 1 , Teddie Magbitang 1
1 Advanced Organic Materials, IBM, San Jose, California, United States
Show AbstractAmong the potential candidates as low-k insulators for copper-back-end-of-the-line (BEOL)[1], organosilicates constitute a promising class of materials which may be deposited either by CVD or by solution spinning processes. Ultra-low-k (k<2.2) nanoporous films can be obtained using a sacrificial porogen approach [2-3]. It’s now well established that the introduction of porosity into organosilicates thin films, negatively impacts the mechanical properties of these materials, manifested by a reduction of the Young’s modulus values and an increase of the crack propagation rate in water. These issues have been addressed with limited success by variation in resin and porogen structures, control of porous morphologies and post porosity treatment using UV or e-beam exposure. Although improvements in modulii of 25-50% are often achieved upon post porosity treatment, this requires a separate processing step and chemical changes are produced in the materials, which can degrade the electrical properties.In an effort to improve the mechanical properties of low-k materials without using post porosity treatment methods, we have investigated the templated sol-gel polymerization of bridged oxycarbosilane monomer precursors [4]. The measured Young’s modulus numbers for the as-synthesized thin films wihout any post porosity toughening are the highest by far of any that we have observed for porous films generated using the sacrificial porogen route. For a given dielectric constant, the Young’s modulus of these oxycarbosilane films are 4-5 times higher than available organosilicates and at least 2 times higher than UV treated organosilicate materials. As a result of the interesting properties of these oxycarbosilane materials, we believe that these oxycarbosilane materials are promising new candidates for dielectric applications at k = 2.3 and beyond.[1] R. D. Miller, Science 1999, 286, 421 and supplementary material.[2] W. Volksen et al, M. Kiene Springer Ser. in Advanced Microelectronics, Springer, Berlin, 2002, Chapt 6.[3] Hedrick, J. L. et al, Chemistry-a European Journal. 2002, 8, 3308. [4] D. A. Loy, K. J. Shea, Chem. Rev. 1995, 95, 1431.
12:15 PM - F4.9
Generation of Porosity in Spin-on Oxycarbosilane Ultra low-κ Dielectric Films.
Marcus Worsley 1 , Geraud Dubois 2 , Stacey Bent 1 , Teddie Magbitang 2 , Robert Miller 2 , Willi Volksen 2 , Mark Sherwood 2
1 Chemical Engineering, Stanford University, Stanford, California, United States, 2 Almaden Research Center, IBM, San Jose, California, United States
Show AbstractThe addition of porosity to novel low dielectric constant (low-κ) materials is required to achieve target κ values less than 2.8. As the target dielectric constant approaches 2.0 (ultra low-κ), previous studies have shown that the mechanical properties of porous organosilicate glass (OSG) materials become extremely poor (e.g. Young’s Modulus measured by SAWS < 2 GPa), making integration of these ultra low-κ materials very difficult without post-porosity enhancement. A possible alternative to OSG films are oxycarbosilane (OCS) films for which we measured exceptional mechanical properties for a κ < 2.0: 4-5 times (Young’s Modulus > 5 GPa) better than those measured in OSG films and as high as post-porosity treated CVD materials at a dielectric constant of 2.3-2.4. A fundamental understanding of pore generation in OCS films is necessary to optimize this material’s potential as a low-κ candidate. Therefore a study of two different pore generation schemes (templating and nucleation & growth), each previously used in OSG films was conducted on OCS films. Relevant film properties were examined, including density, dielectric constant, Young’s modulus, chemical structure, thickness, and refractive index. A pore generating process different from nucleation & growth and templating was observed and will be discussed along with the other relevant results.
12:30 PM - F4.10
Effects of Dielectric Thermal Expansion and Elastic Modulus on the Stress and Deformation Fields in Copper Interconnects.
Yu-Lin Shen 1
1 Mechanical Engineering, University of New Mexico, Albuquerque, New Mexico, United States
Show AbstractPolymer-based low-k dielectric materials typically have very high coefficients of thermal expansion (CTE) and very low elastic modulus, compared to other materials used in the interconnect structure. This study aims at assessing the role played by the individual properties (CTE and modulus) of low-k dielectric in affecting the stress and deformation fields in copper interconnects. Parametric finite element analyses are conducted, varying one parameter at a time, for gaining fundamental understanding of the effect of individual properties. The analyses are based on a three dimensional model containing two levels of metal lines connected by a via. It is found that both the high CTE and low modulus values of the polymer-based dielectric contribute to the evolution of stress/strain fields in the metal structure. The low-k CTE plays a more significant role. Within certain limits, decreasing the low-k CTE and/or increasing the low-k modulus can help alleviate the plastic deformation, and thus the propensity of damage initiation, in the metal. Reducing the low-k CTE will be a more efficient and safer approach.
12:45 PM - F4.11
Comparison of the Fracture Behavior of Brittle ILD Films used in the BEOL in Dry and Wet Environment using Nanoindentation.
Eva Simonyi 1 , Michael Lane 1 , Erick Liniger 1 , Alfred Grill 1
1 , IBM, Yorktown Heights, New York, United States
Show AbstractIn the BEOL during the manufacturing process the low-k brittle ILD films are exposed to wet environments. These environment could and do effect the films fracture toughness, the so called critical film thickness, above which spontaneous cracking occurs. Nanoindentation combined with AFM imaging methods allow to study these phenomena.Typical examples will be presented.
F5: Barrier Metals and Copper Plating
Session Chairs
Romano Hoofman
Lynne Michaelson
Wednesday PM, April 19, 2006
Room 3009 (Moscone West)
2:30 PM - **F5.1
Cu Alloy Metallization for Self-Forming Barrier Process
Junichi Koike 1
1 Dept. of Materials Science, Tohoku University, Sendai Japan
Show AbstractFuture technology node requires the formation of a thin conformal barrier layer. Conventional PVD process has eoncoutnered difficulties in reducing the barrier thickness to less than 10 nm. New ALD approach also suffers from poor adhesion and reliability. Self-forming barrier process has been investigated extensively but without much success. We revisited this challenging issue by carefully considering necessary conditions for alloying elements. Based on our selected conditions, several Cu alloys were investigated as possible candidates. Among them, Cu-Mn alloy was found to be an excellent material to realize the self-forming barrier layer. Formation kinetics followed a logarismic law from 250 to 450 oC, allowing us to chose the barrier thickness from 2- 7 nm. Electric properties and SM and EM reliability were found to be excellent in a dual damascene test structure of 90 nm node. In the presentation, the results of the Cu-Mn alloy will be compared with other Cu alloys to discuss major reasons for the successful barrier formation with the Cu-Mn alloy.
3:00 PM - F5.2
In-situ Plasma-enhanced Atomic Layer Deposition of Tantalum Nitride Liner and Ruthenium Seed Materials for Copper Interconnect Applications.
Oscar van der Straten 1 , Stephen Rossnagel 1 , Ken Rodbell 1
1 T.J. Watson Research Center, IBM Research, Yorktown Heights, New York, United States
Show AbstractIt is anticipated that the sputtered tantalum-based bilayer liner and sputtered copper seed layer currently employed in copper interconnect metallization may need to be replaced within the next few technology generations. Concerns about the ability of physical vapor deposition (e.g., sputtering) to yield continuous and conformal deposition of liner and seed materials on aggressive structures are driving the need for evaluating techniques which are inherently more conformal. In this respect, atomic layer deposition (ALD) appears to be one of the most promising deposition technologies for liner/seed applications, and the enhancement of ALD processes by the use of plasma’s (PEALD) may provide significant benefits.In this study, an in-situ approach was employed for the deposition of liner/seed materials by PEALD. Both tantalum nitride liners and ruthenium seed layers were grown using metal-organic source chemistries, and a remote plasma reduction step. Tantalum nitride was deposited by metal-organic PEALD at a substrate temperature of 250°C using alternate exposures of pentakis(dimethylamino)tantalum (PDMAT) and a remote hydrogen plasma. Ruthenium was grown by employing alternate exposures of 2,4-dimethylpentadienylruthenium (DMRu) and a remote nitrogen plasma, at a substrate temperature of 325°C. Both PEALD processes were conducted in a high vacuum (~1 mTorr) environment, without the use of inert gas purges. Each PEALD cycle thus consisted of metal-organic source exposure, reactor evacuation, remote plasma exposure, and reactor evacuation.The benefit of employing plasma enhancement is e.g. shown in the TaN resistivity which was observed to be as low as 350 µΩcm. Four-point resistivity probe measurements were carried out on ultrathin TaN-Ru bilayers to evaluate the low resistivity that can be obtained for these liner/seed materials by employing an in-situ PEALD approach. Furthermore, the density of TaN-Ru bilayers was addressed by X-ray reflectivity (XRR) characterization in conjunction with film thickness measurements performed by transmission electron microscopy (TEM) and Rutherford backscattering spectrometry (RBS), revealing the high density attainable by PEALD. The conformality and continuity of both PEALD TaN and PEALD TaN-Ru bilayers on high-aspect ratio trench and via structures was also addressed. PEALD yields continuous TaN and Ru deposition across 65nm-wide trench and via structures at an aspect ratio of 6, at reduced (~70%) sidewall coverage compared to field and bottom coverage, which is likely due to the directional nature of the plasma species in PEALD.
3:15 PM - F5.3
Thin, Continuous and Highly Conformal Copper Films by Reduction of ALD Copper Nitride.
Zhengwen Li 1 , Roy Gordon 1
1 Chemistry and Chemical Biology, Harvard University, Cambridge, Massachusetts, United States
Show Abstract3:30 PM - F5.4
Evaluation of Integrity and Barrier Performance of Ultra Thin ALD-diffusion Barriers on PECVD SiO2 and SiOCH low-k Dielectrics for Cu Metallization.
Ki-Su Kim 1 , Moon-Sang Lee 1 , Sung-Soo Yim 1 , Ki-Bum Kim 1 , Hyung-Sang Park 2
1 School of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of), 2 , ASM Genitech, Inc., Daejeon Korea (the Republic of)
Show Abstract4:15 PM - F5.5
Characteristics of cobalt and cobalt silicide film deposited by Remote Plasma ALD method
Keunjun Kim 1 , Keunwoo Lee 1 , Sejin Han 1 , Wooho Jeong 1 , Hyeongtag Jeon 1
1 , Hanyang Univ., Seoul Korea (the Republic of)
Show Abstract Metal silicides have been widely used in Si integrated circuits as contacts, gate electrodes and interconnect materials. Among the metal silicides, cobalt disilicide (CoSi2) has been greatly investigated due to its low resistivity(10~20μΩcm), high thermal stability and close lattice mismatch(~1.2%) with Si(100). CoSi2 is typically formed by sputtering of cobalt followed by annealing. However, sputtering method exhibits poor step coverage and ion-induced substrate damage. Thus, chemical vapor deposition (CVD) method has been employed to solve above problems. In this respect, we introduced remote plasma atomic layer deposition (RPALD) technique to deposit cobalt thin film. Compared to CVD, RPALD is a promising technique to produce high quality and conformal films at low growth temperatures. We studied the process for the deposition of cobalt from cyclopentadienyl cobalt dicarbonyl, Co(C5H5)(CO)2, and dicobalt octacarbonyl, Co2(CO)8. The process parameters were identified as precursor flow, plasma gas flow, substrate temperature. The cobalt thin film was deposited at 150°C for Co(C5H5)(CO)2 and 100°C for Co2(CO)8. The carbon concentration of the film was confirmed as 7~8% for Co(C5H5)(CO)2 and ~15% for Co2(CO)8. In addition, the impurity concentration in the films decreased with increasing plasma power. The as-deposited cobalt film showed a very smooth surface. But, the surface roughness was significantly increased as RTA temperature was increased. CoSi2 was formed at ~600°C with Co(C5H5)(CO)2 precursor and ~700°C with Co2(CO)8 precursor, respectively. Slightly high impurity concentration of cobalt film with Co2(CO)8 precursor was considered to retard silicide transition.
4:45 PM - F5.7
Real Time Study of Cu Diffusion through Ru Thin Film byPhotoemission Electron Microscopy (PEEM)
Wei Wei 1 , Xiong Gang 2 , Y.-M. Sun 1 , Alan Joly 2 , Kenneth Beck 2 , J. White 1 , Wayne Hess 2
1 Chemistry and Biochemistry, University of Texas at Austin, Austin, Texas, United States, 2 , Pacific Northwest National Laboratory, Richland, Washington, United States
Show AbstractHere we demonstrate the efficacy of the Photoemission Electron Microscopy (PEEM) as a tool to detect metal diffusion process at micron spatial resolution in real time. Photoemission electron microscopy (PEEM) is a variant of electron microscopy that images low energy photoelectrons generated by UV lamp or laser sources. Images can be captured at video rates over micron-scale image fields. Since the imaging contrast depends upon microscopic structure and work function, different elements and the reaction kinetics of adsorbed molecules (atoms) can be imaged as a function of surface structure and temperature. The capability to take images in real time as a function of temperature is an advantage of PEEM over other scanning probe techniques.Our PEEM images, which can be played as a movie, were captured in real time at the rate of one image/2 sec as the temperature was increased from room temperature to 600 °C. The sample was prepared in a separate chamber, where a 1.1nm thick (determined by X-ray Photoemission Spectroscopy, XPS) Ru film was deposited by PVD on an 800 nm Cu film over a Si(100) substrate. Copper diffusion through the 1.1 nm ruthenium film started at approximately 320°C, as indicated by the change in photoelectron yield (intensity of image). The entire surface became fully covered by copper when the temperature was raised to ~ 400°C. The increasing ratio of Cu/Ru detected by XPS verified that the diffused copper reached the top of the film. In addition, PEEM revealed that the diffused copper formed clusters on the scale of hundreds of nanometers locally. This observation was corroborated by Scanning Electron Microscopy (SEM). Under our experimental conditions, copper initially diffused through various defects; as the temperature continued to increase, Cu also diffused uniformly through the grain boundaries in the Ru thin film.In summary, we have, for the first time, used PEEM to observe real-time copper diffusion through a vapor-deposited Ru thin film as a function of temperature. The sharp change in work function, and hence large increase in photoelectron yield, appears in the images as bright areas, clearly showing the arrival of copper on top of the Ru film. The PEEM images also provide information on the structure formed by the diffused copper.
5:00 PM - F5.8
Copper Electroplating on Zero-Thickness ALD Platinum for Nanoscale Computer Chip Interconnects.
Alain Kaloyeros 1 , Yu Zhu 1 , Kathleen Dunn 1 , Chris Miller 1 , Michael Breslin 1
1 college of nanoscale science and engineering, the university at albany-suny, albany, New York, United States
Show AbstractThe implementation of copper interconnects in sub-65nm integrated circuitry is projected to be hindered by the well-documented problems associated with physical vapor deposition (PVD), particularly in terms of non-conformal deposition profiles of PVD liner and seed layer. Atomic layer deposition (ALD) provides a viable alternative, particularly because of its excellent conformality, uniformity, and precise film thickness control. Although it would have been desirable to use an ALD Cu seed layer for electroplating, attempts to do so have not been successful to date. Instead, work by the present investigators has focused on platinum due to its high chemical inertness, elevated thermal stability, and acceptable electrical properties. Accordingly, this report presents pertinent findings from Cu electroplating on Pt seed layers grown using an ALD process that was developed and optimized under a separate investigation. PVD Cu seed layers were employed for baseline comparison. The plating electrolyte consisted of 75g/l CuSO4.5H2O, 190 g/l H2SO4, and 70 mg/l HCl. The wetting angle between the electrolyte and each of the seed layers was analyzed using sessile-drop contact-angle analysis prior to plating. DC current was applied to electroplate Cu on blanket seed layers for 0.5, 1.0 and 2.0 minutes, while the current density was kept at 20mA/cm2. Scanning electron microscope (SEM) revealed that Cu nucleation density on the ALD Pt surface is lower than on its PVD Cu counterpart. Nevertheless, Cu nuclei were observed after only 1.0 minute plating on ALD Pt surfaces, and continuous Cu films were achieved for longer plating times. To fill trench structures coated with ALD Pt/TaN, a pulse reverse current (PRC) was applied using the same organic-additive-free electrolyte. Initial results suggest that these seed layers were adequate for ECD fill of trenches with 200 nm feature size and aspect ratio 7. However voids were observed for smaller feature size trenches, suggesting organic additives are needed for super fill smaller topographies Structural analysis using X-ray diffraction (XRD) showed that blanket ECD Cu on ALD Pt had (200) as the preferred orientation, whereas ECD Cu on PVD Cu had a (111) preferred orientation. Additionally, differences in composition and microstructure between the two sets of Cu films were detected by Auger electron spectroscopy (AES) and cross-sectional transmission electron microscopy (TEM).
5:15 PM - F5.9
Thermal Oxidation of Ni and Co Alloys Formed by Electroless Plating.
Jeff Gambino 1 , Igor Ivanov 2 , Ed Adams 1 , Scott Hazel 1 , Dave Meatyard 1 , Phil Pokrinchak 1 , Fen Chen 1 , Pat DeHaven 3
1 , IBM, Essex Junction, Vermont, United States, 2 , Blue29, Inc., Sunnyvale, California, United States, 3 , IBM, Hopewell Junction, New York, United States
Show Abstract5:30 PM - F5.10
Electroless CoWP as a Catalyst of Self-Aligned CNT Growth for Future CMOS Interconnect Via Applications
Tzu-Chun Tseng 1 , Tri-Rung Yew 1
1 Department of Materials Science and Engineering, National Tsing Hua University, Hsinchu Taiwan
Show AbstractThis paper presents self-aligned carbon nanotubes (CNT) grown on CoWP for future CMOS interconnect applications as via material. Electroless deposited CoWP have been proposed recently as an effective diffusion barrier and encapsulation layer for Cu wiring. On the other hand, carbon nanotube has been proved to be an excellent substitution for present Cu via due to its capability of conducting high current density (1000 times of Cu), which become more and more important as the via size continues scaling. Self-aligned CNT via structure formed by growing CNTs on CoWP on the bottom of via holes will be investigated in this work. The CoWP acts as both a catalyst for CNT growth and a barrier to block the under-layer Cu diffusion, while CNTs grown in via holes for high-density current conducting. A preliminary result shows that the CNTs were successfully grown on CoWP catalyst. This work will focus on optimizing the CNT growth process in via holes in terms of alignment and density (1010/cm2), so as to reduce via-resistance for future CMOS interconnect requirements. This paper will also present the results of scanning electron microscopy (SEM), high-resolution transmission electron microscopy (HR-TEM), Raman spectrum, and electrical measurement on three-mask-layer metal/via/metal test structures, which are used to characterize the physical and electrical properties of the self-aligned CNT via using CoWP as a catalyst.
5:45 PM - F5.11
Thin and Smooth Cu Seed Layer Deposition using the Reduction of Low Temperature Deposited Cu2O.
Hoon Kim 1 , Yasuhiko Kojima 2 , Hiroshi Sato 2 , Naoki Yoshii 2 , Shigetoshi Hosaka 2 , Yukihiro Shimogaki 1
1 the materials engineering, The Univ. of Tokyo, Bunkyo ku, Tokyo, Japan, 2 Technology Development Center, Tokyo Electron AT Limited, 650 Mitsuzawa, Hosaka-cho, Nirasaki-city, Yamanashi, Japan
Show AbstractAs damascene interconnect feature size shrink, the deposition of Cu seed layer for electroplating should be changed from sputtering to conformal deposition methods such as MOCVD, ALD and SCFD (Supercritical Fluid Deposition). Among these methods, MOCVD is the most promising deposition method due to its high producibility and well known process. Unfortunately, integration of CVD Cu seed layer from fluorine-containing precursors has been problematic for several reasons, such as nucleation on, and adhesion to, Ta liners. Thus, the search for alternate liner materials was initiated. Ru was of particular interest due to noble transition metal with high melting point and low resistivity. The CVD Cu on Ru showed good adhesion property. Although the CVD Cu wettability and adhesion on Ru was much better than Ta/TaN, the surface morphology of CVD Cu on Ru is not acceptable level for future ULSI-interconnect. Thus, to introduce CVD as seed layer deposition method, the morphology of CVD Cu has to be improved. Additionally, the seed layer deposition also deposited below 250oC for ultra low-k application.In this study, we suggest new deposition concept of CVD Cu, which consists of Cu oxide deposition and reduction because Cu oxide has better morphology than pure Cu film. For ultra low-k application, this whole process was accomplished below 200oC with new chemistry. At first, Cu oxide was deposited with Cu(hfac)TMVS and oxidizing agent on Ru and TaN substrates at 130oC for 7 min. Cu precursor was carried from bubbler to chamber by 100sccm of hydrogen. Deposited Cu oxide films were Cu2O that was confirmed by XRD and XPS. Cu oxide films showed quite smooth and continuous morphology, the thickness of films was 35 nm on both Ru and TaN substrate that was confirmed by SEM. To reduce Cu oxide at lower temperature, formic acid which has strong reducing capability was used as reducing agent. Formic acid was delivered from bubbler to chamber with Ar 50 sccm. Cu oxide film on Ru was reduced at 200oC for 5 min annealing. 35 nm of Cu oxide films were reduced to 25 nm of pure Cu film that was confirmed by XRD, XPS and SEM. The morphology of reduced Cu films showed different manner depending on substrates. The reduced Cu film on Ru showed good surface morphology. However, that on TaN had poor morphology by agglomeration of Cu film during reduction. Good Cu adhesion property of Ru may suppress the agglomeration of Cu during reduction annealing. This oxide deposition and reduction method can be a promising candidate of seed layer deposition method due to its lower process temperature and extremely good morphology.
Symposium Organizers
Ting Y. Tsui Texas Instruments, Inc.
Young-Chang Joo Seoul National University
Alex A. Volinsky University of South Florida
Lynne Michaelson Vishay Electro-Films
Michael Lane IBM T.J. Watson Research Center
F6: Copper Interconnects Relibility
Session Chairs
Gaddi Haase
Young-Chang Joo
Thursday AM, April 20, 2006
Room 3009 (Moscone West)
9:30 AM - **F6.1
Scaling of Statistical and Physical Electromigration Characteristics in Cu Interconnects
Martin Gall 1 , Meike Hauschildt 1 , Patrick Justison 1 , Koneru Ramakrishna 1 , Richard Hernandez 1 , Matthew Herrick 1 , Lynne Michaelson 2 , Hisao Kawasaki 2
1 CMOS Platform Device Development, Freescale Semiconductor Inc., Austin, Texas, United States, 2 Advanced Products Research and Development Laboratory, Freescale Semiconductor Inc., Austin, Texas, United States
Show AbstractEven after the successful introduction of Cu-based metallization, the electromigration (EM) failure risk has remained one of the important reliability concerns for most advanced process technologies. Ever increasing operating current densities and the introduction of low-k materials in the backend process scheme are some of the issues that threaten reliable, long-term operation at elevated temperatures. The main factors requiring attention and careful control are the activation energy related to the dominating diffusion mechanism, the resulting median lifetimes, and the lognormal standard deviation of experimentally acquired failure time distributions. Whereas the origin of the EM activation energy and the behavior of median lifetimes with continuing device scaling are relatively well understood, detailed models explaining the origin and scaling behavior of the lognormal standard deviation have only been reported recently [1, 2]. The statistical behavior of EM-induced void sizes and resulting lifetime distributions appear to be explainable by geometrical variations of the void shapes and the consideration of kinetic aspects of the EM process. Using these models, expected lifetime distributions for future technology nodes can be simulated from current, experimentally obtained void size and lifetime distributions. These simulations have to include geometrical factors of the EM test structures and actual, on-chip interconnects, as well as kinetic aspects of the mass transport process, such as differences in interface diffusivity between the lines. By extrapolating the expected lifetime distributions for future technology nodes from current EM data, it is possible to predict when insertion of new process schemes, such as Cu-alloys and/or metallic coating of the Cu/passivation interface is required.[1] M. Hauschildt et al., AIP Conf. Proc. of Stress Induced Phenomena in Metallization: 7th Int. Workshop, 741, 112-123, (2004).[2] J. He et al., Appl. Phys. Lett. 85 (20), 4639-4641, (2004).
10:00 AM - F6.2
Resistivity of Fine Cu Interconnects at Low Temperatures: Understanding of the Origin of the Size Effect.
Wenqi Zhang 1 2 , Sywert Brongersma 1 , zhen Li 1 , dagang Li 2 , Olivier Richard 1 , gerald beyer 1 , karen maex 1 2
1 , IMEC, leuven Belgium, 2 E.E. Dept., K.U.Leuven, leuven Belgium
Show Abstract10:15 AM - F6.3
In-Situ Characterizarion Of Interfaces Induced Resistivity In Nanometric Dimensions.
Hagay Marom 1 , Moshe Eizenberg 1
1 , Technion - Israel Institute of Technology, Haifa Israel
Show AbstractSince the main speed limitation today of integrated circuits derives from the time delay of the electrical signals passing through the interconnects, it is highly important to control and minimize the resistivity of these interconnects. However, as their dimensions approach the mean free path of the electrons (about 40 nanometers for copper at room temperature), a substantial rise in resistivity occurs, mainly due to additional electron scatterings from the material’s grain boundaries and from its interfaces with other materials. To investigate the role of interfaces, in-situ resistivity measurements were preformed inside a deposition chamber for thin copper films (down to 10 nanometers) on which different materials were deposited without air exposure. The resistivity was continuously monitored during the deposition, enabling a unique observation of the resistivity changes as a new top interface was created. Different interfaces were compared, among which Ta resulted in the highest resistivity increase. This fact is of special importance since this material and its nitride serve today as the common diffusion barrier for Cu metallization. Our approach enabled us to test the influence of diffusion barriers on the resistivity of interconnects, a new factor that will have to be considered in future technology nodes with continuously shrinking dimensions. The copper interface with Ti resulted in a smaller resistivity increase compared to Ta, but still higher than that of a free copper surface (in vacuum). Exposure of such a free surface to air increased its resistivity, demonstrating the importance of the applied experimental technique and raising doubt about the conclusions reported in literature, made on the basis of many measurements that were preformed after exposure to air. Complementary transmission electron microscopy studies were made to further understand the effects of the interfaces on resistivity. Electron transport models for resistivity increase in nanometric dimensions were used for quantitative analysis of the results.
10:30 AM - F6.4
In-situ Grain Growth Investigation of Copper Electrodeposits for ULSI.
Heung Nam Han 1 , Hyo-Jong Lee 1 , Do Hyun Kim 1 , Ui-hyoung Lee 1 , Pil-Ryung Cha 2 , Kyu Hwan Oh 1
1 Material Science and Engineering, Seoul National University, San 56-1, Shinrim-dong, Kwanak-gu, Seoul, Korea (the Republic of), 2 School of Advanced Materials Engineering, Kookmin University, 861-1, Chongnung-dong, Songbuk-gu, Seoul, Korea (the Republic of)
Show Abstract11:15 AM - **F6.5
Electromigration-Induced Plastic Deformation in Cu Damascene Interconnect Lines as Revealed by Synchrotron X-Ray Microdiffraction.
Arief Budiman 1 , N. Tamura 2 , B. Valek 2 , K. Gadre 3 , J. Maiz 3 , R. Spolenak 4 , J. Patel 1 2 , William Nix 1
1 Materials Science & Engineering, Stanford University, Stanford, California, United States, 2 Advanced Light Source (ALS), Lawrence Berkeley National Laboratory (LBNL), Berkeley, California, United States, 3 , Intel Corporation, Hillsboro, Oregon, United States, 4 , ETH Swiss Federal Institute of Technology Zurich, Zurich Switzerland
Show AbstractPlastic deformation was observed in damascene Cu interconnect test structures during an in-situ electromigration experiment and before the onset of visible microstructural damage (voiding, hillock formation). We show here, using a synchrotron technique of white beam X-ray microdiffraction, that the extent of this electromigration-induced plasticity is dependent on the line width. In wide lines, plastic deformation manifests itself as grain bending and the formation of subgrain structures, while only grain rotation is observed in the narrower lines. The deformation geometry leads us to conclude that dislocations introduced by plastic flow lie predominantly in the direction of electron flow and may provide additional easy paths for the transport of point defects. Furthermore, we observe that the rotation axis of this plastic deformation coincides with one of the <112> line directions of the known slip systems for the FCC crystal, and that it is always very close (within a few degrees) to the direction of the electron flow. This finding suggests a correlation of the proximity of certain <112> line directions to the direction of electron flow with the occurrence of plastic behavior. One important practical implication of this particular finding is that the grain texture of the line might play an important role in giving higher resistance towards early plastic response of the Cu line upon the electromigration loading.
11:45 AM - F6.6
Thermal and Electromigration-Induced Strains in Copper Conductor Lines: X-ray Microbeam Measurements and Analysis
Gan Wang 1 , Hongqing Zhang 1 , G. Cargill 1 , C. Hu 2 , W. Yang 3 , B. Larson 3 , G. Ice 3
1 Materials Science and Engineering, Lehigh University, Bethlehem, Pennsylvania, United States, 2 , IBM Research, Yorktown Heights, New York, United States, 3 , Oak Ridge National Lab., Oak Ridge, Tennessee, United States
Show AbstractWe have carried out x-ray microbeam measurements of electromigration-induced strains in copper conductor lines, at NSLS using white-beam energy dispersive x-ray diffraction averaging over many grains, and at APS using white-beam Laue x-ray diffraction from single grains. Strains developed in random texture damascene Cu 2μm-wide, 0.15 μm-thick conductor lines with TaN liners in low-k dielectric during electromigration at 350C are much smaller than electromigration-induced strains in (111) fiber texture Al-on-Si, 10μm-wide, SiO2 passivated conductor lines, which showed development of strain gradients, with perpendicular strains ranging from -0.0016 to +0.0008 (P.-C. Wang et al., Appl. Phys. Letters 72, 1296 (1998)). The reasons for these differences in electromigration behavior may involve the different roles of grain boundary and interface diffusion paths and the different passivation structures and materials for the two types of samples. These results and others will be analyzed and discussed in terms of current models for development and relaxation of electromigration-induced strains.
12:00 PM - F6.7
Effect of Cu Migration in a Field Induced Dielectric Failure.
Sang-Soo Hwang 1 , Sung-Yup Jung 1 , Young-Chang Joo 1
1 School of Materials Science & Enginnering, Seoul National University, Seoul Korea (the Republic of)
Show Abstract12:15 PM - F6.8
Electrical Resistance Anomalies During Electromigration Testing of Cu Conductor Lines: Examples of Local Melting?
H. Zhang 1 , G. Wang 1 , G. Cargill 1
1 Materials Science and Engineering, Lehigh University, Bethlehem, Pennsylvania, United States
Show AbstractWe have observed abrupt, reversible resistance changes during electromigration testing of 2-micron wide, 0.15-micron thick, 100-micron long Damascene Cu conductor lines with TaN liners and W vias. The tests were conducted at 300C and with 1.6 x 106 A/cm2 current density. The initial series resistance of three 100-micron long lines with interconnecting vias was 116 ohms. The resistance changes consisted of pairs of resistance spikes to ~280 ohms of one to two minutes duration, separated by periods of intermediate resistance, between 116 ohms and 280 ohms, for periods of from 0.3 hrs to 4 hrs. After each pair of resistance spikes, the line resistance returned to a value slightly smaller than that before the spikes, reduced from 130 ohms to 114 ohms in one case. We have considered whether these resistance anomalies may result from sudden, local Joule heating and melting of conductor line segments, the pairs of spikes corresponding to initial melting and to subsequent solidification, and the period of increased resistance between the spikes corresponding to the line actually being in the liquid state. Resistance data, microstructural observations and thermal calculations based on this hypothesis will be presented.
12:30 PM - F6.9
Influence of Grain Orientation on the Microstructural Characterization in Cu During (self)-anneal Using a Surface Acoustic Wave Technique.
Atsuko Sekiguchi 1 , Kris Vanstreels 2 , Steven Demuynck 1 , Laure Carbonell 1 , Jan D`Haen 2 , Karen Maex 1 , Sywert Brongersma 1
1 , IMEC, Leuven Belgium, 2 , IMOMEC, Diepenbeek Belgium
Show Abstract12:45 PM - F6.10
Barrier Formation and Thickness Effects on Electromigration Reliability of Cu/Low-k Interconnects.
Jung Woo Pyun 1 , Won-Chong Baek 1 , Paul Ho 1 , Larry Smith 2 , Kyle Neuman 2 , Klaus Pfeifer 2
1 , The University of Texas at Austin, Austin, Texas, United States, 2 , SEMATECH, Austin, Texas, United States
Show AbstractWith the implementation of porous low-k dielectric in Cu interconnects, Ta(N) barrier has become important in preventing Cu diffusion into low-k dielectrics and in providing thermomechanical confinement to the low-k structure to sustain the electromigration (EM) mass transport. Significant efforts have been expended to develop novel barrier materials and process technologies to satisfy these requirements. A barrier-first process has been proposed in place of a pre-clean first process, to improve barrier layer uniformity in the via and eliminate copper contamination otherwise present due to an argon sputter etch prior to barrier deposition. In this paper, a systematic study of the effect of a barrier-first process on EM in Cu/porous low-k interconnects is presented. Multi-linked statistical test structures have been designed to investigate the intrinsic failure mode and process-induced extrinsic failures. Test samples with two metal layers (M1/via/M2) were fabricated at SEMATECH using a dual damascene process on 300 mm wafers. Results from this study using an up-current (stressed M2 level) EM test revealed that, compared with a conventional pre-clean first process, no extrinsic early failure was found for the samples with the barrier-first process, indicating an improvement in EM reliability as a result of fewer defects at the via bottom. However, for down-current (stressed M1 level) EM test structures, their cumulative failure distribution (CDF) curves showed behavior similar to the pre-clean first process due to an identical setting for M1 integration. The effect of the barrier-first process on the confinement of Cu/low-k interconnects was also studied using multi-linked structures that enabled us to derive a critical current density and metal line length (jL)c product. Compared with the pre-clean first process, this process resulted in increased (jL)c product due to a thicker and more uniform barrier layer. The microstructure of Ta barrier morphology was analyzed by transmission electron microscopy (TEM). Cross-sectional focused ion beam (FIB) images revealed intrinsic EM-induced void formation at the interface between Cu and the capping layer.
F7: Advanced Metrology Techniques: Metallization
Session Chairs
Thursday PM, April 20, 2006
Room 3009 (Moscone West)
2:30 PM - **F7.1
New Characterization Metrology for low-k/Cu Interconnect Integration: Voltamometry and Its Applications
Choong-Un Kim 1 , DongMei Meng 1 , Nancy Michael 1 , Y.-J. Park 2 , Laura Matz 2 , Sri Satyanarayana 3
1 Materials Science and Engineering, The University of Texas at Arlington, Arlington, Texas, United States, 2 , Texas Instruments, Dallas, Texas, United States, 3 , Sematech, Austin, Texas, United States
Show AbstractThe reliable integration of the low-k/Cu interconnect structure is a key element in the success of future microelectronics, yet it faces increasingly difficult challenges. In addition to reduced material redundancy in the structure (barrier and interlevel dielectric (ILD)), the lack of efficient characterization metrology for defect/failure in the structure is creating significant delays in the technological progress. Developed mainly for conventional interconnects, the available metrologies lack the desired speed, and even worse, the accuracy, to characterize and detect defects/failure in the hidden, but large surface area, structures like the barrier and ILD. For the past few years, we have been developing a new characterization metrology that can characterize the integrity of the barrier and ILD with improved speed and accuracy. This new method uses a radically different approach. It takes advantage of the fact that the low-k layer is permeable to electrolyte. Utilizing a common interconnect test structure (such as a comb structure) as mating electrodes, an internal electrochemical cell is formed when electrolyte is infiltrated into the low-k. The method then monitors the electrochemical reaction specific to the defect in the barrier and ILD. For example, it detects defects in the barrier by monitoring the reactivity of Cu under specific bias potential. The end result of the barrier failure, regardless of its origin, is the exposure of Cu on barrier/low-k interface. Since the exposed Cu can undergo redox (reduction/oxidation) reactions, its presence and exposed area can be characterized by monitoring reaction current under cyclic potential. The working principle behind the detection of defects in the barrier and ILD and its effectiveness in real interconnects are discussed, along with its potential to meet other characterization needs. This work is supported by SRC and Texas/ATP grants.
3:00 PM - F7.2
Feasibility of Thermal Microscopy of Embedded Voids in Layered Geometries.
Sanjiv Sinha 1 , Shriram Ramanathan 2
1 Systems Technology Lab, Intel Corporation, Portland, Oregon, United States, 2 Components Research, Intel Corporation, Portland, Oregon, United States
Show Abstract3:15 PM - F7.3
Advanced X-ray Fluorescence: and Innovative Interconnect and Process Metrology Solution for 45 nm and Beyond.
Jean Paul Gueneau de Mussy 1 , Gerardo Bottiglieri 1 , Nancy Heylen 1 , Laure Carbonell 1 , Jeremy O Dell 2 , Dileep Agnihotri 2 , Alex Tokar 3 , Isaac Mazor 3
1 SPDT/ITS, IMEC, Leuven Belgium, 2 , Jordan Valley, Austin, Texas, United States, 3 , Jordan Valley, Migdal HaEmek Israel
Show Abstract3:30 PM - F7.4
A Study on the Stepwise Cross-sectional Crystalline Analyses of the Stress Induced Voiding in Cu Interconnect by Focused Ion Beam and Electron Backscattered Diffraction
Hyo-Jong Lee 1 , Kyu Hwan Oh 1 , Heung Nam Han 1 , Suk Hoon Kang 1 , Jeong-Yun Sun 1 , Sun-Jung Lee 2 , Hong-Jae Shin 2
1 Material Science and Engineering, Seoul National University, San 56-1, Shinrim-dong, Kwanak-gu, Seoul, Korea (the Republic of), 2 Advanced Process Development Team, System LSI Business, Samsung Electronics Co., Ltd., San 24, Nongseo-ri, Kiheung-eup, Youngin-city, Kyunggi-do, Korea (the Republic of)
Show Abstract Previous work has reported the cross-sectional crystallographical analyses on various trench patterns in the copper damascene interconnect by focused ion beam (FIB) and electron backscattered diffraction (EBSD) [1]. Similar analysis technique is applied for revealing the cause of stress induced voiding (SIV) during hot temperature storage (HTS) test as one of reliability tests in the copper interconnect. HTS test in the copper interconnect is to estimate electrically interconnection failures by heat treatment at about 150~300 oC for about 100~1000 hrs. By conventional failure analyses, it is convinced that a large void is generated at a position of wide pattern which a via contacts. Therefore, many researchers have reported that the cause of the SIV is stress concentration by upper via structure. Recently, Lee et al suggested a new insight of the SIV phenomenon [2]. They found many voids happened on a lower wide pattern after decapping the upper layers. The voids in the wide pattern were randomly generated and many of them were already generated before via etch process. Some voids seemed to be generated during etch stopping layer (ESL) and intermetallic dielectric (IMD) depositions. Therefore, an interconnection failure happens in the chain pattern of wide lines because stochastically one of thousands of vias may unfortunately land down on a void of a wide line. For crystallographically studying the SIV in the copper interconnect, the planar EBSD analysis shows that a void is initiated in the triple junction of grain boundaries, not of twin boundaries. Especially, the void grows preferably in one of the grains joining at the triple junction, and the preferably voided grain is convinced as stress concentration by stress calculation for the anisotropical crystalline structures of measurement data. The overall shape of voided grain is like a micron cucumber of 1.0μm length and 0.2μm width and the void happened at an end near the triple juction. In order to supplement the crystalline information of the void by planar EBSD analysis, it is necessary to investigate 3D crystalline structure of the void by cross-sectional EBSD analysis. The analysis is performed by stepwise sectioning from the unvoided region to the voided region in the voided grain. Conventionally the cross-sectional crystalline structure in thin film is columnar, and the partially unvoided region at an end of the voided grain is also columnar structure with narrow width of 0.2μm. Although only small portion below the void surface remained, the crystalline orientation of the voided area before voiding must be the same as the remaining crystalline structure at the voided region.Reference1. Hyo-Jong Lee , Dong Ik Kim, Jeong Hun Ahn and Dong Nyung Lee, Thin Solid Films 474, 250 (2005)2. Sun-Jung Lee, Soo-Geun Lee, Bong-Suk Suh, Hongjae Shin, Nae- In Lee, Ho-Kyu Kang and Gwangpyuk Suh, Proc. IEEE IITC (2005)
F8: Stress in Copper Interconnects
Session Chairs
Thursday PM, April 20, 2006
Room 3009 (Moscone West)
4:15 PM - **F8.1
The Effects of Interconnect Structures on Thermal Mechanical Stress of Cu lines and the Impact of Unstressed Lattice Spacing Determination.
Seung-Hyun Rhee 1 , I. C. Noyan 2 , Conal Murray 3 , Paul Besser 4
1 AMD Logic Technology Development, Advanced Micro Devices, ASTA (AMD/IBM/Sony/Toshiba) Alliance, Hopewell Junction, New York, United States, 2 Dept. of Applied Physics & Applied Mathematics, Columbia University, New York, New York, United States, 3 T J Watson Laboratory, IBM Research Division, Yorktown Heights, New York, United States, 4 Advanced Process Development, Technology Dev. Group, AMD, Sunnyvale, California, United States
Show AbstractNot Available at time of submission.
4:45 PM - F8.2
Plastic Deformation of Cu in Thin Films, Interconnect Lines and Other Confined Structures.
Joost Vlassak 1 , Y. Xiang 1
1 Division of Engineering and Applied Sciences, Harvard University, Cambridge, Massachusetts, United States
Show Abstract5:00 PM - F8.3
Kinetics of Void Drift in Copper Interconnects
Zung-Sun Choi 1 , Reiner Moenig 1 , Carl Thompson 1
1 Materials Science and Engineering, MIT, Cambridge, Massachusetts, United States
Show AbstractIt is now well established that electromigration can lead to the motion of voids in Cu interconnects. This has been observed for pre-existing stress voids as well as for voids that form as a result of electromigration-induced stresses. Drift and coalescence of voids can cause the formation or larger voids that cause failure, and drift of voids that are already large, but non-fatal, can cause their motion to locations where they become fatal. Therefore, understanding the dynamics of voids is critical for accurate reliability assessment. Void motion in passivated interconnects was investigated in top view using backscattered electrons in a scanning electron microscope (SEM) in real time. These in situ observations confirm that voids that had formed at various locations along the interconnect drifted towards the cathode. These observations also allow measurement of void drift rates over long multi-grain distances. Void drift does not require electromigration at the Cu/passivation interface, but can occur due to electromigraion at the void/Cu surface alone. Hence voids can drift through single grains, and do so at a rate governed by the void/Cu surface electromigration rate. To independently characterize surface electromigration, we have carried out in situ SEM and other high vacuum electromigration studies on unpassivated damascene Cu lines. Void volumes have been measured using both SEM and AFM imaging, allowing determination of the effective z*D for electromigration at free Cu surfaces. Combination of these measurements with observations of void dynamics in passivated lines indicates the relative importance of surface electromigration in defining the void migration rate. Measurement of the rate of void growth, for voids trapped at grain boundaries, then provides quantitative information about the relative rates of interfacial electromigration on the two sides of the trapping grain boundary.
5:15 PM - F8.4
Theoretical Analysis Of Current-Driven Interactions Between Voids In Metallic Interconnect Lines.
Jaeseol Cho 1 , M. Rauf Gungor 1 , Dimitrios Maroudas 1
1 Department of Chemical Engineering, University of Massachusetts, Amherst, Massachusetts, United States
Show AbstractElectromigration-induced void dynamics in metallic interconnect lines, especially void coalescence and break-up, have major effects on the reliability of microelectronic devices. This is because sudden changes in the morphological and size evolution of voids can cause interconnect failure and/or abrupt increases in the interconnect line resistance. In spite of detailed recent studies of current-driven motion and morphological evolution of single voids in metallic lines, the driven interactions of multiple voids under electromigration conditions remain largely unexplored. Additionally, electromigration-driven interactions between voids constitute an intriguing theoretical problem of complex nonlinear dynamics in solids under the action of external fields. Our analysis is based on self-consistent numerical simulation of current-induced migration and morphological evolution of void surfaces in metallic thin films, which accounts rigorously for surface curvature effects that can be particularly strong due to the strong anisotropy of adatom diffusion on metallic surfaces. The mass transport problem on the void surface is solved self-consistently coupled with the electric-field distribution in the conducting film that contains the morphologically evolving voids and captures the strong current-crowding effects around void surfaces. The analysis reveals the complex nature and extremely rich outcomes of void-void interactions in interconnect lines through perturbations in the electric-field distribution created by the evolving morphologies of multiple voids. It is demonstrated that, under certain conditions, smaller voids migrating behind larger voids and in the same direction with them do not always approach and coalesce with the larger voids. In addition, we find that larger voids migrating behind smaller voids and in the same direction with them, under certain conditions, may catch up and coalesce with the smaller voids. Furthermore, it is demonstrated that void coalescence and break-up can cause sudden fluctuations in the interconnect line electrical resistance, which can explain similar frequent observations in accelerated electromigration experiments. Moreover, our analysis shows that void morphological evolution can be influenced drastically by current-driven void-void interactions, which can trigger void morphological instabilities leading to detrimental effects on interconnect reliability.
F9: Poster Session II
Session Chairs
Junichi Koike
Michael Lane
Lynne Michaelson
Alex Volinsky
Friday AM, April 21, 2006
Salons 8-15 (Marriott)
9:00 PM - F9.1
Investigation of W-Ge-N Deposited on Ge as a Diffusion Barrier for Cu Metallization.
Seemant Rawal 1 , David Norton 1 , Tim Anderson 2 , Lisa McElwee White 3
1 Materials Science and Engineering, University of Florida, Gainesville, Florida, United States, 2 , Chemical Engineering, University of Florida, Gainesville, Florida, United States, 3 , Department of Chemistry, University of Florida, Gainesville, Florida, United States
Show AbstractThe properties of W-Ge-N thin films were investigated as a diffusion barrier material for Cu metallization. The W-Ge-N films were grown by reactive sputtering on a single crystal Ge substrate. This was followed by in-situ deposition of Cu. Diffusion barrier test was performed by annealing the film stack under Ar atmosphere. Phase identification and film crystallization were determined by X-ray diffraction. The deposited W-Ge-N films remained amorphous even after high temperature annealing. The Cu diffusion profile in the film was assessed by Auger electron spectroscopy and energy dispersive spectroscopy. The results indicate that Cu diffusion was minimal in W-Ge-N films even at high annealing temperatures. Interface reactions and properties were analyzed by cross-section transmission electron microscopy. The results suggests that W-Ge-N may be a superior diffusion barrier as compared to WNx for Cu metallization.
9:00 PM - F9.10
The Copper Corrosion and Sulfur Contamination Generated by a Three-step Copper Chemical-mechanical Polishing Process.
Chun-Ping Liu 1 , Y. S. Ho 2 , T. C. Hu 3 , Bae-Heng Tseng 1
1 Institute of Materials Science and Engineering, National Sun Yat-Sen University, Kaohsiung Taiwan, 2 Department of Electrical Engineering, National Kaohsiung University of Applied Science, Kaohsiung Taiwan, 3 Institute of Engineering Management, National Chen Kung University, Tainan Taiwan
Show Abstract9:00 PM - F9.11
Passive Film Growth and Removal during Copper post-CMP Cleaning.
Jun Liu 1 , Darryl Peters 1 , Mike Hughes 1 , Monica Hilgarth 1 , Mackenzie King 1
1 MLS R&D, ATMI, Inc., Danbury, Connecticut, United States
Show AbstractThe use of copper passivators for chemical mechanical planarization (CMP) is wide spread in the semiconductor industry. Benzotriazole (BTA) is a well known copper passivator to protect copper exposed to corrosive media. If BTA remains on copper films buried below barrier layers and dielectric, thermal cycling can result in delamination and device failure due to decomposition of the BTA or the BTA-Cu complex. Consequently, it is necessary to remove the BTA film prior to processing the device to the next level. We studied the kinetics for application and removal of BTA using a quartz crystal microbalance. Variation in the deposition parameters was observed to strongly influence the kinetics for deposition and the thickness of the films. The kinetics for removing BTA films were studied for several commercially available post-CMP cleaners under various conditions and significant differences were observed. We tested the QCM mass gain versus time for a copper electrode immersed in BTA solutions with different pH values. A pH 2 solution shows a slow, linear initial growth of the passive film followed by nearly exponential growth after 3 minutes. The BTA film formed after an additional 2 minutes was 580Å thick. This growth rate characteristic is consistent with a precipitated, physisorbed film. The BTA film growth rate for a pH 5 solution displayed a faster initial growth rate followed by a decrease in growth rate after 1 minute. After five minutes, the BTA film thickness was 70Å. A pH 12 solution produced the thinnest film, calculated at 40Å thick after 5 minutes. This implies that after 20 seconds of exposure in this solution, a monolayer of BTA formed on the copper. The film growth rate is nonlinear over the entire time range and had the fastest initial growth rate of the three different BTA solutions studied. It is necessary to remove BTA before processing the wafers to the next level to avoid adhesion problems and device failures due to delamination. One can remove BTA films with a surface preparation agent. We measured removal data for a BTA film deposited on copper at pH 5. The initial film thickness was 70Å thick. As shown in mass loss data for the electrode immersed in ATMI ESC-797 diluted 30:1 with DI water, the entire film was removed in 4 minutes. BTA removal data for ATMI LP-12 diluted 20:1 with DI water indicates that the entire film was removed in less than 1 minute. However, the BTA removal for a commercially available ammonium citrate solution diluted 10:1 required 4 minutes to remove the BTA film. As seen, both ESC-797 and LP-12 are more efficient at removing the BTA film. The copper surface remaining, after cleaning with either ESC-797 or LP-12, was stable and no copper corrosion was observed after several days in air. However, after treatment with the ammonium citrate solution, the copper surface readily corroded, indicating that this treatment left a reactive surface.
9:00 PM - F9.12
Slurry Chemistries for Chemical Mechanical Polishing of Gold.
Saurabh Agrawal 1 2 , Jay Jayashankar 1
1 Seagate Research, Seagate Technology, Pittsburgh, Pennsylvania, United States, 2 Materials Science and Engr., Rensselaer Polytechnic Institute, Troy, New York, United States
Show AbstractChemical mechanical polishing (CMP) of metals has assumed increasing importance in recent times especially after the invention of the damascene process. The high conductivity requirements led to the replacement of Al with Cu. Continuing with the same trend highly conducting metals like Au and Ag are likely candidates for future interconnect technology. There is therefore a need to develop CMP chemistries to controllably polish noble metals. Polishing of noble metals to obtain sub-nanometer finish with low defectivity poses serious challenges in view of their intrinsically inert nature.In this work we present details of slurry chemistries that can be used for Au CMP. Two different slurries have been studied – an I2/KI based chemistry, and a Potassium Ferricyanide based composition. Our results demonstrate that I2 and KI, when used in low enough concentrations, are suitable for Au CMP being operative near the rest potential. Dependence of removal rate and surface roughness of Au is studied with varying amounts of I2 and KI and a representative rate equation is proposed. Surface roughness as good as ~ 6 Å could be obtained with a removal rate ~ 400 nm per min. The work presents electrochemical and AFM evidence corroborating the effectiveness of the aforesaid chemistry. Removal rate and surface roughness were found to increase with increasing I2/KI concentrations indicating thereby that the chemistry used is inherently an etching chemistry which proceeds without the formation of a passivating film: a fact also illustrated in the electrochemical flat cell and impedance spectroscopy.Formation of a near ideal passivating film was observed on exposing Au to Potassium Ferricyanide based slurry. As a result, electro-chemical planarization efficiencies as high as 98 % could be obtained at a potential of 0.4 – 1.4 eV with respect to standard hydrogen electrode. This implies excellent topographic removal selectivity and the amenability to use the chemistry in conjunction with oxidizers. The passive film formed is also easy to remove as indicated by in-situ CMP electrochemical measurements conducted with and without abrasion. Electrochemical impedance spectroscopy shows a strongly capacitive behavior due to the formation of highly passivating film. Film chemistry studied using X-ray photoelectron spectroscopy (XPS) shows the oxidation of Au to higher oxidation states due to the formation of Au-Ferricyanide complexes
9:00 PM - F9.14
Electrochemical Characteristics of CMP Copper in a Low Abrasive Slurry.
Amanda Bozak 1 , Arthur Diaz 2 , Ashwani Rawat 1 , Hokkin Choi 1 , Mansour Moinpour 1
1 , Intel Corp., Santa Clara, California, United States, 2 Department of Chemical and Materials Engineering, San Jose State University, San Jose, California, United States
Show AbstractThe performance of a CMP process for a copper wafer in a commercially available slurry was measured using various electrochemical approaches to characterize the copper removal rate. It was found that the copper etching process in this slurry was chemically driven. The copper dissolution rate was high and a weak, permeable oxide layer was formed which did not effectively reduce the dissolution rate. This layer was readily removed by the polishing mechanical action. AFM inspection of the resulting copper surface showed low surface roughness for all cases. The optimum H2O2 concentrations in the slurry that achieved high removal rates and a planar copper surface for the process were determined to be for concentrations between 0.1% and 0.4% H2O2. Under these conditions, the open circuit potentials were more cathodic and the corrosion currents were higher during etching. These results indicate a faster reaction rate. The Tafel plot results indicate an active dissolution behavior, with no indication of passivation with the pH 6.5 slurries containing 0% to 3% H2O2. The changes in the OCP between the sequential etch and polish conditions indicate that a porous film was present on the copper surface. This layer became more porous with increasing H2O2 content in the slurry. The changes in anodic current between sequential etch and polish also confirm the formation of a porous layer on the copper surface. The technical details of this study will be presented.
9:00 PM - F9.15
Investigation of the Rate of Copper Deposition onto Silicon via Galvanic Displacement.
Calvin daRosa 1 , Enrique Iglesia 1 , Roya Maboudian 1
1 Chemical Engineering, University of California, Berkeley, California, United States
Show AbstractGalvanic displacement is a simple and selective method for the deposition of metal films on oxidizable substrates, such as silicon, without the need for prior activation of the surface. This technique holds promise for producing copper interconnects, catalysts, and other microstructured metal components. The design and synthesis of such structures requires a more complete understanding of the effects of growth conditions on deposition rates and film structure. Here, we report dynamic measurements of Cu deposition on Si by galvanic displacement using a rotating disk electrode to determine the relative importance of transport and of the kinetics of the chemical processes on deposition rates and film structure. In particular, the effects of CuSO4 concentration, HF concentration, and rotating speed are probed. Deposition rates are proportional to CuSO4 concentration after correcting for the effects of Cu film thickness and are nearly proportional to HF concentration for concentrations up to approximately 0.5 M HF. The latter dependence reflects the increasing rate of silicon oxide dissolution with increasing HF concentration. A deposition model has been developed which predicts the deposition rate by equating the rates of copper deposition and silicon dissolution. Results obtained with this model agree well with experimentally-determined deposition rates and indicate that diffusion of Si dissolution products through the porous Cu film limits the deposition rate for most conditions studied.
9:00 PM - F9.16
Design an Electroplated Frame Freestanding Specimen for Microtensile Testing of Submicron thin TaN and Cu Film.
Ming-Tzer Lin 1 2 , Chi-Jia Tong 1 , Chung-Hsun Chiang 1
1 Institute of Precision Engineering , National Chung Hsing University, Taichung Taiwan, 2 Center for Nano Science and Nanotechnology , National Chung Hsing University, Taichung Taiwan
Show Abstract9:00 PM - F9.17
Non-destructive Deep Embedded Copper Interconnection Defects Measurements Using Photoacoustic Microscope.
Lu Xu 1 , Donnacha Lowney 1 , Patrick McNally 1
1 School of Electronic Engineering, Dublin City University, Dublin Ireland
Show AbstractWith the ongoing downward scaling of on-chip interconnection, the physical failure analysis of copper line and via defects, such as voids, open and short paths, becomes ever more important. Conventional characterization methods include focused ion beam scanning electron microscopy (FIB-SEM), optical beam induced resistance change method (OBIRCH) and high energy electron beam probing. In contrast, photoacoustic microscopy is a non-contact, non-destructive technique, which has the capability to detect embedded structures as deep as several hundred micrometers without any sample preconditioning requirement. In this paper, we present a novel automated large area photoacoustic mapping system, based on the gas cell concept, which is specifically designed for semiconductor wafer applications. Multiple microphones, helium gas coupling, acoustic resonance and a high power laser light source (1.2 W) are used to increase the signal to noise ratio (SNR). Typical data acquisition time is 50 ms per point. We present data for an interconnection system comprising of different sets of copper lines, whose width vary from 0.15 um to 200 um, buried under 600nm of SiO2 or a low-k carbon-doped oxide (low-k). Deep embedded interconnection defects in Cu lines are detected. The mapped images are compared with SEM and synchrotron X-ray topography results. Finite element analysis has been used to model the phase and amplitude contrast of photoacoustic signal due to the embedded copper lines and extra thermal diffusion barriers arising from interconnection defects. Simulation results agree with experimental data.
9:00 PM - F9.18
Relationship Between Interfacial Adhesion and Dielectric Reliability of Cu Alloy Films.
Seol-Min Yi 1 , Kwang-Ho Jang 1 , Yong-Hak Huh 2 , Young-Bae Park 3 , Young-Chang Joo 1
1 School of Materials Science and Engineering, Seoul National University, Seoul Korea (the Republic of), 2 Strength Evaluation Group, Korea Research Institute of Standards and Science, Daejeon Korea (the Republic of), 3 School of Materials Science and Engineering, Andong National University, Andong Korea (the Republic of)
Show Abstract9:00 PM - F9.19
Effect Of Overburden Layer On Microstructure In Damascene Cu Lines.
Jong-Min Paik 1 , Young-Hoo Kim 1 , Jung-Kyu Jung 1 , Young-Chang Joo 1
1 School of Material Science & Engineering, Seoul National University, Seoul Korea (the Republic of)
Show AbstractIn spite of lower bulk-resistivity of Cu, the resistivity of Cu lines is expected to continue to increase as scaling down and be a limiting factor on device performance in the next generation technology node. Furthermore, it was reported that the microstructure has an influence on the electromigration reliability. The scaling effect of resistivity of damascene Cu lines is originated from the reduced grain size of lines with small dimension and extra grain boundary scattering as well as surface scattering. In this study, the effect of overburden layer on microstructure was investigated using three dimensional TEM analysis as well as numerical study. For this purpose, periodic line structures and via-line structures with various line width and spacing was fabricated by damascene process. The grain size of damascene Cu shows characteristic scaling effect such that it increases with increasing line width. Also, from the TEM images of the lines before CMP, it was found that most grains in the overburden is larger than those in the trenches and even extended into the inside of the trenches, while the grain growth in the inner trench is limited by line width. When the overburden thickness increases, the portion of the grains from the overburden layer increased so that the average grain size of the lines became larger. To clarify the overburden effect, a simple grain growth model was constructed considering the geometrical parameters such as overburden thickness, line width, and line spacing. The results of resistance measurement for the lines which have various geometries confirmed the compatibility of the model.
9:00 PM - F9.2
Comparison of Ru/Ta and Ru/TaN as Barrier Stack for Copper Metallization.
Xin-ping Qu 1 , Jing-Jing Tan 1 , Qi Xie 1 , Guo-Ping Ru 1 , Bing-zong Li 1
1 Department of microelectronics, Fudan University, Shanghai China
Show Abstract Copper direct electrodeposition on the diffusion barriers has become more and more appealing because it will lessen the technology complexity and the possibility of poor conformality caused by relatively thick sputtered copper seed layer. It has been reported recently that Ruthenium was a good diffusion barrier on which copper can be directly electroplated and the Ru layer adheres well with Cu. However, the Ru layer doesn’t have good adhesion on SiO2 and low K material. Furthermore, thin Ru film is not a very effective diffusion barrier. Therefore it would be better that combining Ru with a kind of good barrier material to act as the diffusion barrier to copper. In this paper, the properties for the Ruthenium (Ru)/ Ta and Ru/ TaN as copper diffusion barrier were studied by sheet resistance, X-ray diffraction (XRD), and transmission electron microscopy (TEM). Cu, Ru, Ta and TaN thin films were deposited by ion beam sputtering technique. The thickness of the Ru layer is about 5nm, and the thickness of the Ta or TaN layer is also 5nm. It is found that the thermal stability for the Cu/Ru/TaN/Si or Cu/Ru/Ta/Si structure is much improved than the Cu/Ru/Si structure at high annealing temperature. The Ru/TaN structure shows better barrier properties than the Ru/Ta one. TEM results show that annealing the Cu/Ru/TaN/Si at 400C for 30 min doesn’t cause microstructure change while the 400C annealing resulted in severe microstructure change in the Cu/Ru/Ta/Si structure. The structure change and microstructure evolution were discussed. The copper layers were further electroplated on the Ru/TaN and Ru/Ta samples. The morphology of the copper layer versus different processing condition was discussed. The results show that the Ru film, together with the TaN interlayer, can be a very promising diffusion barrier for electroplated Cu.
9:00 PM - F9.20
Novel Reducing Chemistry for Supercritical Fluid Deposition of Copper.
Takeshi Momose 1 , Tomohiro Ohkubo 1 , Masakazu Sugiyama 2 , Yukihiro Shimogaki 1
1 Materials Engineering, the University of Tokyo, Tokyo, Tokyo, Japan, 2 Electronic Engineering, the University of Tokyo, Tokyo Japan
Show AbstractSupercritical fluid deposition (SCFD), which is the reduction of metal organic compounds with hydrogen in supercritical carbon dioxide, may be a promising technology for ULSI Cu metallization. The use of scCO2 as a reaction medium acquires lots of advantages due to the superior properties of it. Gas-like diffusivity of scCO2 enables excellent gap filling, and liquid-like solubility of scCO2 enables high deposition rate and wide range of applicable precursor. In addition to these characteristics, optimal control of its chemistry has a potential to realize novel and desirable process performance. For example, SCFD generally employs H2 as a reducing agent and it may be a drawback of this process, but we may have a chance to use new liquid reducing agent to eliminate the risk of using high pressure H2. Thus, we started to develop novel reduction chemistry of Cu-SCFD process using our original in situ monitoring technique, and when acetone was used as a reducing agent, dipivaloylmethanato-copper (Cu(DPM)2) could deposit Cu film onto Ru coated Si substrate. This may be the first report of Cu deposition by using acetone as reducing agent. The use of dehydrate acetone deposited high purity Cu film without C, O contamination, whereas using acetone with a little amount of absorbed water, the deposited film contained 15% of O contamination. When acetone was added into H2 reducing chemistry, the solubility of precursor was enhanced approximately 50 % compared to without acetone. This may achieve the deposition with high precursor concentration, which enables to employ a precursor with insufficient solubility into scCO2, and is useful to develop the new chemistry of SCFD. In summary, control of acetone chemistry in SCFD has a potential to develop a novel Cu-SCFD process to various applications for ULSI metallization.
9:00 PM - F9.22
Computer Simulations of Grain Boundary Grooving and Cathode Voiding in Bamboo-like Metallic Interconnects by Surface Drift-diffusion under the Capillary and Electromigration Forces.
Tarik Ogurtani 1 , Oncu Akyildiz 1
1 Metallurgy&Materials Engineering, Middle East Technical University, Ankara Turkey
Show Abstract The process of grain boundary (GB) grooving and cathode voiding in sandwich type thin film bamboo lines are simulated by introducing a new mathematical model, which flows from the fundamental postulates of irreversible thermodynamics. In the absence of the electric field, the computer studies on the triple junction kinetics show that it obeys the first order reaction kinetics at early transient stage, which is followed by the familiar time law as , at the steady state regime. The applied electric field (EF) in constant current experiments modifies this time law drastically above the well-defined electron wind intensity (EWI) threshold, and puts an upper limit for the groove depth, which decreases monotonically with EWI. Below the threshold level, the capillary regime predominates, and EF has little effect on the general kinetics of GB grooving, other then the linear increase in total elapsed time with EWI. An analytical formula for the cathode failure time (CFT) in constant voltage test is obtained in terms of the system parameters, which are closely associated with the cathode voiding or grain thinning by surface drift-diffusion.The kinetics of cathode edge shrinkage and displacement (drift) coupled strongly with the grain boundary (GB) grooving is also investigated by the novel mathematical model developed by Ogurtani. The computer simulations are performed under the constant current and the switch-over constant voltage operations. The cathode drift velocity and the cathode failure time show the existence of two distinct phases, depending upon the normalized electron wind intensity parameter χ ; the capillary (χ≤ 0.2) and the electromigration (EM) dominating regimes (χ≥0.2 ), having current exponent n , equal 0 and -1, respectively. The analysis of the various experimental data on the cathode drift velocity results a consistent value for the surface drift-diffusion coefficient for copper interconnects exposed to some contaminations during the processing and testing stages . This is found to be an excellent agreement with the experimental values reported in the literature. The complete cathode failure time (CCFT) due to the cathode area shrinkage by voiding is also formulated by inverse scaling and normalization procedures, which show exactly the same capillary and EM dominating regimes. This formula can be used to predict very accurate CCFT for metallic lines with bamboo-like, near-bamboo, and even polycrystalline structures by proper calculation of the cathode-edge path length (CEPL) parameter, in terms of the actual line width, the thickness and the grain size.
9:00 PM - F9.23
Feasibility Study for Usage of Diluted Fluorine for Chamber Clean Etch Applications as an Environmental Friendly Replacement of NF3.
Ronald Hellriegel 2 , Bernd Hintze 2 , Matthias Albert 1 , Johann Bartha 1 , Michael Pittroff 3
2 , Infineon Technologies, Dresden Germany, 1 , TU-Dresden, Dresden Germany, 3 , Solvay Fluor GmbH, Hannover Germany
Show Abstract9:00 PM - F9.3
A Novel MO Precursor for Metal Tantalum and Tantalum Nitride Film.
Kenichi Sekimoto 1 2 , Taishi Furukawa 1 2 , Norikaki Oshima 2 1 , Ken-ichi Tada 1 , Tetsu Yamakawa 1
1 , Sagami Chemical Research Center, Ayase, Kanagawa, Japan, 2 Tokyo Research Center, Tosoh Corporation, Ayase, Kanagawa, Japan
Show Abstract9:00 PM - F9.4
Pulsed CVD of Thin Ru metal Films Using an Amidinate Precursor.
huazhi li 1 , Titta Aaltonen 1 , Roy Gordon 1
1 Chemistry, Harvard University, cambridge, Massachusetts, United States
Show AbstractRuthenium metal has gained increasing interest as a potential electrode material in transistors and capacitors. Also it has demonstrated potential as a seed layer, adhesion layer and diffusion barrier for copper metallization. Conformal and uniform Ru thin films are important for these applications. ALD and CVD processes could meet such restrictions. However previously reported ALD or CVD processes for Ru use oxidizing conditions and/or plasmas, which cause damage to substrates. We have synthesized a new ruthenium precursor, bis(N,N'-di-tert-butylacetamidinato)bis(carbonyl)ruthenium(II). X-ray diffraction shows that it has a monomeric structure with a distorted octahedral coordination of the Ru. Each of the 2 amidine ligands is attached to the Ru by 2 Ru-N bonds, forming a stable chelate structure. This compound is volatile enough for vapor deposition (130 °C at 50 mTorr) and leaves very low residue (0.1%) after thermogravimetric (TG) analysis. NMR shows that its solution in xylene is stable at 175 °C for at least 48 hrs. Pulsed CVD was done with this precursor at substrate temperatures ranging from 200 to 300 °C, resulting in electrically conductive Ru films. Film purity, nucleation density, surface morphology, conformality, adhesion strength and electrical conductivity will be reported.
9:00 PM - F9.5
Post Etch/Ash Cleaning Process Development and Integration into 65nm Cu/low-k Dual Damascene Process Flow using Metal Hard Mask
Miao Lin 1
1 Advanced Etching Dept., UMC, Tainan Science Park, Sinshih Township, Tainan County Taiwan
Show AbstractAs the industry develops processes for the 65 and 45 nm nodes, post etch/ash cleaning faces new challenges with far more stringent requirements on surface cleanliness and material loss. The introduction and integration of new materials, such as metal hard mask, creates additional requirements for wafer cleaning due to the occurrence of new defect modes related to metal hard mask. These include organometallic residue and metal fluorite compounds precipitating with time. We have developed a novel aqueous solution (AQ) based single wafer cleaning process to address these challenges. Physical characterization results, process integration electrical data and reliability data (TEM analysis) are presented in this paper. The main conclusions can be summarized as follows: (1) In the hard mask employed dual damascene Cu/low-k structure process flow used for this study, there are three typical residues after etch/ash: generic polymer residue, residue strongly bonded to metal hard mask, and time-dependent metal fluoride residue. (2) Generic polymer residue is very well characterized [1,2] and is usually easy to remove with solvent or aqueous solution [2,3]. (3) Residue strongly bonded to metal mask is characterized as organometallic residue. We developed an oxidizing chemistry to undercut the hard mask for the organometallic residue removal, which proved highly effective. (4) Metal hard mask related metal fluorite residue precipitates with time. This time-dependent metal fluoride reside makes queue time control after etch/ash very critical (<1 hour). We developed a fluorine based aqueous chemistry to address the metal fluoride residue, which proved highly effective. With this chemistry, queue time control is not required. (5) The post etch/ash cleaning for the Cu/low-k structure with metal hard mask typically employs the solvent/dry plasma ash/solvent three-step procedure [4]. The new process developed in this research reduced the solvent/dry plasma ash/solvent to one aqueous cleaning step with two different cleaning chemistries in sequence. (6) The integration electrical data shows that the new single step aqueous cleaning process performance is comparable to, or even better than that from the solvent/dry plasma ash/solvent cleaning process. (7) TEM analysis shows no Cu undercut, therefore higher reliability performance is expected.
9:00 PM - F9.6
A Ruthenium Seed Layer and Copper Deposited by Electrochemical Plating.
Hyung-Il Kim 1 , Kim Young-Soon 1 , Chul-Hee Jeon 1 , Young-Mo Kim 1 , Hyung-Kee Seo 1 , Choong-Un Kim 2 , Hyung-Shik Shin 1
1 School of Chemical Engineering, Chonbuk National University, Jeonju, Jellabuk-do, Korea (the Republic of), 2 Material Science and Engineering, University of Texas-Arlington, Arlington, Texas, United States
Show Abstract9:00 PM - F9.7
Cu Resistivity in Narrow lines: Dedicated Experiments for Model Optimization.
Sylvain Maitrejean 1 , Roland Gers 1 , Thierry Mourier 1 , Alain Toffoli 1 , Gerard Passemard 2
1 , CEA LETI, Grenoble France, 2 , STMicroelectronics, Crolles France
Show Abstract9:00 PM - F9.8
Low Temperature Plasma Etching of Copper for Minimizing Size Effects in sub-100 nm Features
Nagraj Kulkarni 1 , Dennis Hess 2 , Galit Levitin 2 , Prabhakar Tamirisa 2
1 Metals & Ceramics, Oak Ridge National Laboratory, Knoxville, Tennessee, United States, 2 School Of Chemical & Biomolecular Engineering, Georgia Institute of Technology, Atlanta, Georgia, United States
Show AbstractThe size effect phenomenon in copper interconnects may be minimized by using a reactive ion etching (RIE) process for copper metallization rather than the currently prevalent damascene process. Due to the fact that the texture and grain size in blanket Cu films used in RIE processed Cu structures can be controlled to minimize the grain boundary scattering contribution to the total resistivity, it is expected that a resistivity approaching the value projected in the ITRS roadmap (2.2 microohm-cm) for 45 nm features can be achieved. Preliminary experiments describing low temperature, plasma etching of Cu thin films using a two-step, sequential process proposed by the authors will be presented.
9:00 PM - F9.9
Improvement of Barrier Properties of TaN Film by Plasma Enhanced Atomic Layer Deposition
In Cheol Baek 1 , Han-choon Lee 1 , Jae-Won Han 1 , Kee-Ho Kim 1 , Soo Hyun Kim 2 , Sahng Kyoo Lee 2
1 Advanced Nano-tech Development, DongbuAnam Semiconductor, Eumseong-gun Korea (the Republic of), 2 Advanced Development Team, IPS Ltd., Pyeongtaek Korea (the Republic of)
Show AbstractA bilayer of TaN/Ta, deposited using PVD, is typically used as the Cu diffusion barrier. As the device dimension continues to shrink with technology development, PVD has the limitation to achieve conformal step coverage across the dual damascene structure. Atomic layer deposition (ALD) is being actively developed as a possible solution to deposition of TaN Cu barrier layer of 5nm thickness in the Cu/low k interconnects for 65nm technology node and beyond. In this work, the Plasma Enhanced ALD (PEALD) TaN were deposited on low-k dielectric film (SiCOH) with a k value of 3.0 at a deposition temperature 300degreeC by using pentakis (ethylmethylamino) tantalum (PEMAT) and various plasma gases. The film resistivity of TaN is about 1000 μΩcm by using H2 plasma with a power of 200 W and 400 KHz. The resistivity is significantly reduced to approximately 400 μΩcm by using H2+NH3 plasma with 300 W and 13.56 MHz. In addition, good uniformity is obtained by using H2+NH3 plasma gas and adding vacuum purge step. The film thickness/cycle at same condition was reduced from 0.8 Å/cycle to 0.6 Å/cycle. SEM images after 1 hour anneal at 350degreeC show that adhesion property of PEALD TaN with seed Cu is better than PVD TaN. TEM images in the dual damascene structure show that the step coverage of PEALD TaN with thickness of 5nm is an almost 100%. The PEALD TaN in this dual damascene structure has a contact resistance of ~1.8 Ω at a via size of 0.16um.
Symposium Organizers
Ting Y. Tsui Texas Instruments, Inc.
Young-Chang Joo Seoul National University
Alex A. Volinsky University of South Florida
Lynne Michaelson Vishay Electro-Films
Michael Lane IBM T.J. Watson Research Center
F10: Future Interconnects
Session Chairs
Friday AM, April 21, 2006
Room 2004 (Moscone West)
9:30 AM - **F10.1
Benefits and Trade-offs in Multi-Level Air Gap Integration.
Romano Hoofman 1 , Roel Daamen 1 , Viet Nguyenhoang 1 , Julien Michelon 1 , Laurent Gosset 2 , Vincent Arnal 3 , Jean de Pontcharra 4 , Phillippe Lyan 4 , Frederic Gaillard 4 , David Bouchu 4 , Rudy Caluwaerts 5 , Christophe Bruynseraede 5 , Gerald Beyer 5
1 , Philips Research Leuven, Leuven Belgium, 2 , Philips Semiconductors R&D, Crolles France, 3 , STMicroelectronics, Crolles France, 4 , CEA-LETI, Grenoble France, 5 , IMEC, Leuven Belgium
Show AbstractThe continuous push towards smaller device dimensions has directed interconnect technology towards the integration of porous low-k materials, in order to cope with the increasing interline capacitances. The integration of porous low-k materials into copper dual-damascene structures is accompanied with a tremendous number of challenges [1], delaying the introduction of these dielectrics as compared with the ITRS roadmap predictions. At the end of the roadmap, air gaps appear as ultimate ‘porous’ inter-metal dielectric (IMD). The question arises whether a faster introduction of air gaps lead to a new boost of the low-k roadmap or to a further delay.Different air gap integration approaches are known to fabricate multi-level interconnects. All approaches can be classified in the following categories: (i) partial or complete material-removal in-between metal-lines followed by non-conformal CVD deposition [2-3], and (ii) damascene integration of metal-lines in a sacrificial material, which can be selectively removed through a dielectric cap [4-5]. Each of these methods has its specific benefits and trade-offs. However, the biggest challenge with respect to multi-level air gap integration is thought to be the mechanical integrity and associated packaging and reliability-issues. Solutions might be found in the combination of performance modeling, design and technology. Performance modeling gives an indication of how many air gap levels are needed, while design determines the specific location and technology decide how they will be formed.In this paper, different air gap integration approaches will be discussed in detail. The benefits of air gaps in multilevel interconnects are well known, therefore the authors will concentrate on the challenges associated with the introduction of air gaps in future interconnects. It will be shown that interconnects containing air gaps do not suffer more from reliability challenges than interconnects with porous low-k dielectrics. Therefore, air gaps might be considered as a viable option for the 32nm node and beyond.References: 1. R.J.O.M. Hoofman et al. Microelectron. Eng. 80 (2005), p.337-344.2. V. Arnal et al. Proc. IITC (2001), p.298-300.3. J.P. de Mussy et al. Proc. IITC (2005), p.150-152. 4. R. Daamen et al. Proc. IITC (2005), p.240-242.5. L.G. Gosset et al. Microelectronic Engineering (2005) in press.
10:00 AM - F10.2
Routes to the Formation of Air Gap Structures Using PECVD.
Raymond Vrtis 1 , Dingjun Wu 1 , Mark O'Neill 1 , Mary Haas 1 , Scott Weigel 1 , Eugene Karwacki 1
1 Electronics, Air Products and Chemicals Inc., Allentown, Pennsylvania, United States
Show AbstractPorous organosilicate glasses (OSG) with dielectric constants as low as 2.0 can be deposited using PECVD and post-deposition curing processes. These extremely low dielectric constant materials generally incorporate about 25% porosity. It is anticipated that higher levels of porosity (> 35%) will be required to deposit porous OSG films with lower dielectric constants, however, at these levels of porosity the mechanical properties of the films may be unsuitable for film integration. An alternative route that many users are investigating is the use of air bridges which take advantage of the very low dielectric constant of air. To date the fabrication of air gaps has focused on three main avenues: (i) the use of extremely non-conformal SiO2 depositions that result in large key-hole structures as the air gaps but cannot be used in a damascene process. (ii) the use of thermally labile polymeric materials deposited by either spin-on processes or hot filament CVD. This approach requires etching into the capping layer to allow for the decomposition gases to escape. (iii) isotropic etching of air gaps either by reactive ion etching of an underlying film or via a wet etch using HF. Here a channel must be opened in the capping layer to allow for the etching material to reach the sacrificial layer. We will report on three alternative approaches for fabricating air gap structures. The first utilizes an organic sacrificial layer to create the air gap. This is an extension of the our patented PDEMS® approach we developed for making porous OSG films. In this approach the as-deposited sacrificial film is pure porogen. The sacrificial porogen film is capped with a porous OSG film that enables the porogen to be removed through the capping layer by a post-deposition cure without the need to open a “vent” for the porogen decomposition gases. A second approach, similar to the first, employs a porous capping layer that allow for diffusion of an etching gas through the capping layer to selectively etch the underlying sacrificial layer. The third method employs the use of a water soluble inorganic porogen to form both the sacrificial layer for the air gap and to act as the porogen for the formation of the porous capping layer. Here the water is used to both create the pores in the capping layer and remove the sacrificial layer in one step.
10:15 AM - F10.3
Growth of Individual Vertically Aligned Nanotubes for Interconnects.
Mohammad Kabir 1 , R. E. Morjan 2 , P Lundgren 1 , O. A. Nerushev 2 , S. bengtsson 1 , P. Enoksson 1 , E. E. B. Campbell 2
1 Microtechnology and Nanoscience, Chalmers University of Technology, Gothenburg Sweden, 2 Dept. of Experimental Physics, Gothenburg University and Chalmers University of Technology, Gothenburg, Gothenburg, Sweden
Show Abstract10:30 AM - F10.4
A Deep Silicon Tapered via Etch Process for Through-wafer Interconnects in Three Dimensional Integrated Circuits.
Nagarajan Ranganathan 1 , Krishnamachar Prasad 2 , Dayong Lee 2 , Narasimhan Balasubramanian 1
1 , Institute of Microelectronics, Singapore Singapore, 2 School of Electrical & Electronic Engineering, Nanyang Technological University, Singapore Singapore
Show AbstractVertical or three dimensional (3-D) circuit integration is one of the core approaches that can solve and improve the existing interconnect performance bottleneck. 3-D stacking of electronic or electro-mechanical circuits is possible using through-wafer vertical interconnects. Use of through-wafer interconnects leads to shorter chip-to-chip interconnection lengths, reduced parasitic wiring resistance and reduced lead inductance associated with wire-bonded packages for high frequency applications. A well-controlled etch process is essential for forming deep silicon via, which is one of the most critical technologies in the fabrication of through-silicon copper interconnection by electroplating process. It is preferable to have a sufficiently tapered via profile such that it facilitates conformal deposition of the isolation dielectric, copper diffusion barrier, copper seed layer for electroplating and finally the copper electroplating process itself. However, the development of a tapered via etch process is a challenge by itself. The traditional BOSCH etch process [1] has limitations in terms of throughput and controllability of sidewall profile of the deep silicon via. The etch rate decreases significantly when a sidewall polymer is employed to cause the profile to taper during the etch process. Also, the extent of taper is very small, typically a few degrees. The sidewall profile tends to straighten due to excessive ion bombardment as the etching process extends deeper. The excessive ion bombardment leads to rougher sidewall surface, resulting in increased inter-via electrical leakage current due to defects in the sidewall. In a recent study, it was shown that the BOSCH etch process leads to increased inter-via electrical leakage current due to sharp scallops in the top corners [2], thus posing a serious reliability issue under excessive electrical and thermal stress conditions. In the present work, a dual etch process has been developed in which the first step is a high etch rate BOSCH or a non-BOSCH process and the second step is a SF6 and O2 based isotropic plasma etch process. The first high-etch rate process provides vertical dimension control while the second etch step controls the slope, provides top corner rounding and heals the sidewall roughness of the silicon vias. This enables conformal dielectric and metal deposition for subsequent electroplating process and also offers excellent opportunity to control two inter-dependent output parameters like “high etch rate” and “good profile control” which cannot be achieved with one process only. References:1.J. Bhardwaj et al., Annual Meeting of the Electrochemical Society, Montreal, Quebec, Canada, May 4-9, 1997.2.N.Ranganathan et al., 55th Electronic Components and Technology Conference, Orlando, Florida, USA, May 31- June 3, 2005.
10:45 AM - F10.5
Deep Sub-Micron Wafer-to-Wafer Self-Alignment for Wafer-Level 3D ICs
Sang Hwui Lee 1 , Frank Niklaus 2 , Ravi Kumar 1 , Hui-feng Li 1 , J. Jay McMahon 1 , Jian Yu 1 , James Lu 1 , Timothy Cale 1 , Ronald Gutmann 1
1 CIE, RPI, Troy, New York, United States, 2 , KTH, Stockholm Sweden
Show AbstractWafer-to-wafer aligned bonding is used for fabrication of three-dimensional integrated circuits (3D ICs), advanced microelectromechanical systems (MEMS) and packaging applications. Specifically wafer-level 3D integration is an emerging technology to reduce the interconnect delays by shortening the wire lengths. Commercially available alignment equipment can repeatedly achieve wafer-to-wafer alignment of approximately one micron for 200mm diameter wafers that is suitable for many applications. However, precise wafer-to-wafer alignment accuracy (on the order of 100 nm) is desired for the more advanced 3D IC applications. In addition, wafers can shift relative to each other during the bonding process, specifically when intermediate bonding layers are used that flow during the wafer bonding process. In this paper, a mechanical interlocking mechanism using novel self-fine alignment structures is proposed. The self-alignment structures on the pre-aligned wafer pair slide into each other along the tapered planes during wafer bonding, so that significantly improvement of alignment accuracy can be achieved. The mechanically interlocked structures can also prevent wafers from shifting relative to each other and maintain their aligned position during the bonding process. With several fabrication processes and material sets being investigated, for this work a single mask with self-alignment structures, EVG SmartView wafer alignment marks and vernier structures is designed; a photoresist reflow technique is employed to pre-define the tapered plane of self-alignment structures on a PECVD oxide layer deposited on a glass wafer. A standard stepper projection lithography and reactive ion etching (RIE) are used to fabricate the structures. A 30-degree tapered plane of oxide layer to the glass wafer surface is obtained after RIE etch, followed by wafer alignment using an EVG SmartView aligner with a pre-bonding alignment accuracy of approximately one-micron. The two pre-bonding aligned wafers are clamped and bonded to facilitate the self-alignment and inspected through the glass using an optical microscope. Preliminary results indicate that these self-alignment structures at the wafer surfaces can adjust and improve the pre-bonding wafer-to-wafer alignment accuracy to well below one micron, approaching 100nm. Detailed fabrication procedure and full alignment results will be discussed in the manuscript and present in the conference. Impact on extremely high inter-wafer interconnectivity applications and self-alignment alternatives will also be discussed.
F11: Advanced Metrology Techniques: Dielectrics
Session Chairs
Friday PM, April 21, 2006
Room 2004 (Moscone West)
11:30 AM - F11.1
Elastic Properties Measurements of Porous ULK : a Comparison Between Nanoindentation and Brillouin Light Scattering.
Frederic Ciaramella 1 , Giovanni Carlotti 3 , Vincent Jousseaume 1 , Marc Verdier 2 , Gianni Socino 3 , Sylvain Maitrejean 1 , Aziz Zenasni 1 , Charles Le Cornec 1 , Gerard Passemard 4
1 D2NT/LBE, CEA-LETI, Grenoble France, 3 Dipartimento Di Fisica, INFM, Perugia Italy, 2 LTPCM, CNRS, Grenoble France, 4 , STMicroelectronics, Crolles France
Show Abstract The ITRS roadmap underlines the need of dielectric material for ILD with dielectric constant (k) lower than 3 for the 90 nm node and than 2.4 for the 45 nm node. The introduction of porosity in a dielectric matrix which is the main way used to perform ULK material is accompanied by a sharp decrease of the thin film mechanical properties. The measurement of elastic properties (Young's modulus and Poisson's ratio) of submicronic thin film deposited on silicon substrate constitutes a real challenge. Nanoindentation is one of the technique used for modulus determination but some works report systematic overestimation of the elastic properties in comparison to other techniques such as Brillouin light scattering (BLS) or Surface Acoustic Wave Spectroscopy (SAWS). Various ULK thin films of different controlled porosity are processed in this work. The films are deposited using a methylsilsesquioxane (MSQ) as matrix and organic nanoparticles as porogen. After deposition and baking, the composite is thermally cured to allow the porogens degradation and matrix crosslinking and then form the porous structure. Different k values (between 2 and 3) are obtained by varying the porogen loading in the composite. After careful calibration of the nanoindenter machine, the same method used for dense thin film to evaluate intrinsic film property is presented, making use of continuous stiffness measurements. Results are critically reviewed and the effect of densification discussed. The obtained values using this procedure are compared to BLS measurements. It is shown that elastic properties by nanoindentation are very close to BLS measurements for ULK materials with k value as low as 2.0 with a corresponding reduced modulus of 2 GPa. Different film thicknesses were tested to demonstrate the ability of instrumented indentation even for very thin films as currently produced on industrial processing line (500nm). In addition, BLS technique gives access and permits to determine the Poisson's ratio (n) evolution versus the porosity rates (between 0 % and 40 %). Mechanical properties (Young's modulus, Poisson's ratio, Hardness) are discussed along with the varying porosity.
11:45 AM - F11.2
Studies of the Coefficient of Thermal Expansion of Low-k ILD Materials by X-Ray Reflectivity.
George Antonelli 1 4 , Michael Goodner 2 , Mansour Moinpour 2 , Tran Phung 3 , Clay Mortensen 3 , David Johnson 3
1 Portland Technology Development, Intel Corporation, Hillsboro, Oregon, United States, 4 Physics Department, Brown University, Providence, Rhode Island, United States, 2 Fab Materials Operations, Intel Corporation, Hillsboro, Oregon, United States, 3 Materials Science Institute and Chemistry Department, University of Oregon, Eugene, Oregon, United States
Show AbstractThe electrical and mechanical properties of potential low-k dielectric materials inorganic and carbon-doped oxides as well as organic polymers have received a great deal of attention in recent years; however, studies of the thermal properties such as the thermal conductivity and the coefficient of thermal expansion have been largely neglected. The reason for the absence of data is due in part to the limited number of experimental techniques for making such measurements applicable to this class of materials at dimensions of relevance to current and future integrated processes. We present a method of using x-ray reflectivity to make measurements of the coefficient of thermal expansion for sub-micron thin films. In particular, we elucidate the thin film mechanics required to extract this parameter for a free-standing film as opposed to a supported film. Results for both PECVD and spin-on deposited thin films will be provided for both glass and polymer character materials.
12:00 PM - F11.3
Chemical Bonding, Permittivity and Elastic Properties in Locally Modified Organosilicate Glass
Ehrenfried Zschech 1 , Heiko Stegmann 2 , Patrick Hoffmann 3 , Dieter Schmeisser 3 , Pavel Potapov 1 , Hans-Juergen Engelmann 1 , Dmytro Chumakov 1 , Holm Geisler 1
1 Materials Analysis Department, AMD Saxony LLC & Co. KG, Dresden Germany, 2 , Carl Zeiss NTS GmbH, Oberkochen Germany, 3 Angewandte Physik - Sensorik, BTU Cottbus, Cottbus Germany
Show AbstractChanging local electronic polarizability and chemical bonding in organosilicate glass (OSG) in such a way that the effective permittivity, and consequently the electrical performance of the Cu/low-k structure, deteriorates only slightly and that adhesion and stiffness are improved significantly is an extremely challenging task. As the interconnect line spacings continue to shrink, optimization of the electrical and mechanical properties of the ILD material becomes increasingly important for Cu/low-k integration since the effect of thin regions, that have been modified by special treatments, on the effective material properties, e. g. keff, increases. Locally modified chemical composition and chemical bonding effect the materials properties significantly. As an example, plasma processing for resist stripping, trench etching and post-etch cleaning removes C and H containing molecular groups from the near-surface layer of OSG. Therefore, the effect of chemical bonding on permittivity and elastic modulus has to be studied for process optimization. Compositional analysis and chemical bonding characterization of structured ILD films with nanometer resolution is done with electron energy loss spectroscopy (EELS), complemented with X-ray absorption spectroscopy (XAS). The fine structure near the C-K electron energy loss edge or absorption edge, respectively, allows to differentiate between C-H, C-C, and C-O bonds, and consequently, between individual low-k materials and their modifications. The dielectric permittivity is determined based on EELS plasmon loss measurements using Kramers-Kronig analysis. The elastic modulus is determined with the modulus mapping technique implemented in a nanoindentation tool with in-situ scanning probe microscopy (SPM) imaging capability. This technique is capable to measure the elastic properties with a very high surface sensitivity due to penetration depths in the nanometer range. The spatial resolution can be further improved by using a special force-modulated atomic force microscopy (AFM) technique.
12:15 PM - F11.4
Determination of Poisson's Ratio of Thin low-k Films using Bidirectional Thermal Expansion Measurement.
Jiping Ye 1 , Satoshi Shimizu 1 , Shigeo Sato 1 , Nobuo Kojima 1 , Junnji Noro 1
1 Research Dept., NISSAN ARC Ltd., Yokosuka Japan
Show Abstract12:30 PM - F11.5
Non-contact Dielectric Constant Metrology for low-k Films on Semiconductor Production Wafers.
Vladimir Talanov 1 , Andre Scherz 1 , Andrew Schwartz 1
1 , Neocera, Inc., Beltsville, Maryland, United States
Show AbstractLow-k materials are very sensitive to the various damascene processing steps such as etch, cleans and chemical mechanical polishing (CMP). Each of them can substantially raise the effective/integrated dielectric constant of the interconnect stack. Hence, there is a need for an in-line metrology to characterize the dielectric constant of low-k materials on semiconductor production wafers. The primary requirement for such a metrology is that the probe sampling spot must be <50 micron in at least one dimension so it can address a typical test-key located within the 80-μm-wide scribe-line between the die. To the best of our knowledge, no technique able to perform such a measurement has been reported.We have developed a method capable of non-destructive measurement of bulk/effective dielectric constant of low-k films on production wafers utilizing a test key of less than 50x50 μm^2 in size. The test key consists of a low-k film/stack backed by a Cu grid with ≥50% metal pattern density and ≤0.25 μm pitch, which is fully compatible with existing interconnect technology.The method is based on an original near-field scanned microwave probe with ~10 micron sampling spot size. In a near-field approach the spatial resolution is governed by the probe geometry rather than the wavelength of the radiation utilized. Therefore, even at microwave frequencies with wavelengths on the order of centimeters, such a probe can achieve spatial resolution down to the sub-micron scale. Our probe is formed by a 4 GHz parallel strip transmission line resonator tapered down to ~10 micron tip size. An electrical near-field similar to the fringe field of a parallel plate capacitor is formed at the electrically open tip. When a dielectric sample is brought in close proximity to the tip, the tip fringe capacitance terminating the resonator increases, and consequently the probe resonant frequency decreases. The apparatus sensitivity to this capacitance is ~0.3 attoFarad, which allows for the small sampling area that is beyond the capabilities of traditional capacitance measurements.The measurement is non-contact, non-invasive, and non-contaminating (the probe is fabricated entirely from quartz and aluminum). It is real time and yields 0.3% precision and 2% accuracy for k-value. The proposed test key is already in use by other metrologies such as ellipsometry and OCD/scatterometry, allowing for film thickness, k-value, and CD measurements at the same location on the wafer. No electrical contact to or grounding of the wafer is required since both probing electrodes are located on the probe above the sample and capacitively coupled to it. Therefore, the test key can be employed at any level in the interconnect structure.
12:45 PM - F11.6
Characterization of the Structural Changes of a Porous SiOC During a Curing Process with Ellipsometric Porosimetry.
Adrien Darragon 1 , Jean Philippe Piel 1 , Yann Turcant 1 , Patrice Heinrich 1
1 , SOPRA, Bois-colombes France
Show AbstractEllipsometric porosimetry (EP) is an effective method for characterization of porosity, pore size distribution (PSD) of porous low K films. Spectroscopic ellipsometry is used to determine the amount of adsorptive, which is adsorbed in the film. The change in refractive index is used to calculate the quantity of adsorptive present in the film. EP gives accurately the porosity of the layer (both microporous and mesoporous volumes) and the distribution of pore size (both microporous and mesoporous). Changes in thickness of the ultra low K lead to the calculation of the Young modulus of the layer (figure 2). PECVD SiOC wafers are measured with EP before and after the curing process. Curing conditions vary for each wafer and structural changes are observed with the Ellipsometric Porosimeter. EP measures the following parameters for each wafer: thickness, refractive index, young modulus, porosity, and distribution of pore size. The initial thickness of the ultra low K is measured around 8000A with spectroscopic ellipsometer. After Curing the ULK shrinks to about 6000A. The change in porosity is also very significant: EP detects a change of more than 3% in mesoporous volume. The curing process has impacted the distribution of porous. A comparative study will be presented.EP can detect these parameters on 300mm wafers. The small probing surface allows an edge exclusion of less than 3mm.
F12: Chemical-Mechanical Planarization
Session Chairs
Friday PM, April 21, 2006
Room 2004 (Moscone West)
2:30 PM - F12.1
Single and Mixed Surfactant Systems for Post-CMP Cleaning.
Deenesh Bundi 1 , Yuzhuo Li 1 , Dedy Ng 2 , Hong Liang 2
1 Chemistry, Clarkson Univeristy, Potsdam, New York, United States, 2 Mechanical Engineering, Texas A & M University, College Station, Texas, United States
Show AbstractOne major concern in post-CMP cleaning is particle contamination on the polished wafer surface after the CMP process. These particles can be abrasive particles from the slurry, debris from pad material, and particles of film being polished. One of the most important chemical additives in a post CMP cleaning solution is a surface active compound or surfactant. The removal of these particles from substrate surface is often aided with the addition of surfactant molecules into the post CMP cleaning solution. The selection criteria for a surfactant includes hydrophobic-hydrophobic balance, critical micelle concentration, head group charge in relation to the particles to be removed and substrate surface, and tendency to leave residues on the substrate surface. In this study, in addition to a conventional single surfactant system, we investigated the use of a mixed surfactant systems as well. It is observed that the mode of interaction between particle surface or substrate surface and mixed surfactant system is significantly different than those single surfactant systems alone. Furthermore, for the first time, we used a tribological approach to study the effectiveness of such surfactant systems over various phase regimes, especially the surfactant concentration below and above cmc. The friction data was compared and correlated with dynamic NMR results which provided insight into the mode of molecular interaction between surfactant molecules and particles to be removed. Such insight may serve as a useful guideline on how surfactant should be selected and dosed in order to achieve effective particle removal.
2:45 PM - F12.2
Applications of Raman Spectroscopy in Cu CMP: In-situ Detection of Chemical Species in the Slurry
Siddartha Kondoju 1 , Pierre Lucas 1 , Srini Raghavan 1 , Paul Fischer 2 , Mansour Moinpour 3 , Andrea Oehler 4
1 Materials Science and Engineering, University of Arizona, Tucson , Arizona, United States, 2 Components Research, Intel Corp, Portland, Oregon, United States, 3 Fab Materials Operation, Intel Corp, Santa Clara, California, United States, 4 Fab Materials operation, Intel Corp, Portland, Oregon, United States
Show AbstractSlurries used for copper CMP are rich in chemistry, which may change during the course of polishing due to consumption and decomposition of ingredients. Various aspects, such as small layer thickness (<50 mm), continuous flow of the slurry, and dynamics of the film removal process pose great challenge to the monitoring of slurry components between the pad and the wafer. The slurry constituents such as oxidants and corrosion inhibitors have unique signatures that can be detected using spectroscopic techniques. In this paper, work carried out to explore the use of Raman spectroscopy to detect and quantitate chemical species such as hydroxylamine, benzotriazole and hydrogen peroxide in-situ will be presented. In the case of hydroxylamine, it is possible to determine the relative amounts of protonated amine and free amine in the slurry. An abrasion cell integrated with a Raman spectrometer was used to make the measurements.
3:00 PM - F12.3
The Role of Arginine as a Complexing Agent in Copper CMP.
Surya Sekhar Moganty 1 , Srinivasan Ramanathan 2
1 Chemical Engieering, Indian Institute of Technology Madras, Chennai, Tamil Nadu, India, 2 Chemical Engineering, Indian Institute of Technology Madras, Chennai, Tamil Nadu, India
Show Abstract3:15 PM - F12.4
Characterization of Post-CMP Cleaning of Advanced PDEMS® Dielectrics.
Dnyanesh Tamboli 1 , Mark O'Neill 1 , Madhukar Rao 1 , Thomas Wieder 1 , Scott Weigel 1 , Gautam Banerjee 1 , John Langan 1
1 , Air Products & Chemicals, Allentown, Pennsylvania, United States
Show AbstractThe development of robust integration processes for low dielectric constant materials is critical in order to meet the International Technology Roadmap for Semiconductors (ITRS) timeline for next generation materials. Organosilicate glass (OSG) materials with bulk dielectric constant between 2.7 and 3.0 have been successfully used in production of semiconductor devices for 90 nm interconnect node. For 45 nm and beyond the ITRS roadmap dictates use of an advanced dielectric material with a bulk dielectric constant below 2.5. The dielectric constant of OSG materials produced by plasma enhanced chemical vapor deposition (PECVD) processes can be reduced to less than 2.0 (R. Vrtis, MRS Series Vol. 766, pg. 259) through the introduction of porosity. Porous OSGs are considered poorly compatible with standard CMP and post-CMP cleaning processes because of their poor mechanical properties, hydrophobicity and chemical penetration into the pores. In this paper we compare the CMP and post-CMP cleaning compatibility of a novel ultra-low K material based on PDEMS® technology (US patent 6,846,515) with that of a dense OSG material based on trimethylsilane (Z3MS™). Wafers subjected to CMP and post-CMP cleaning processes were characterized both for defectivity and chemical degradation. The compatibility of these materials to post-CMP cleaning process and the impact of porosity will be shown by various techniques including dielectric constant measurement, X-ray scattering, spectroscopic ellipsometry, surface energy measurement, Scanning Electron Microscopy (SEM), Fourier Transformed Infrared Spectroscopy (FTIR), X-ray PhotoElectron Spectroscopy (XPS).
4:00 PM - F12.5
AFM Measurements of Adhesion between CMP Slurry Particles and Copper
Ruslan Burtovyy 1 , Yong Liu 1 , Bogdan Zdyrko 1 , Alex Tregub 2 , Mansour Moinpour 2 , Mark Buehler 3 , Igor Luzinov 1
1 School of Materials Science and Engineering, Clemson University, Clemson, South Carolina, United States, 2 CMO/FMO, Intel Corporation, Santa Clara, California, United States, 3 PTD, Intel Corporation, Hillsboro, Oregon, United States
Show AbstractAdhesion between abrasive particles and surfaces being polished plays an important role in chemical mechanical polishing (CMP) processes. The changes in particle - surface and particle – particle interactions can significantly influence the effectiveness of material removal and cleaning methods. To determine the adhesion between actual abrasive particles and different surfaces treated by CMP process a method employing atomic force microscopy (AFM) technique is being developed.The monolayer of silica abrasive nanoparticles was deposited on silicon wafer covered with polymer anchoring layer. High affinity of the thin polymer film to the particles and wafer ensures the stability of particles monolayer on the surface during measurements. AFM cantilever was modified with attachment of 20-40 microns hollow glass bead (representing a flat surface), which then was covered with copper using chemical vapor deposition technique. Force-distance curves were collected employing AFM force volume mode and used to calculate the adhesion value. The effect of different factors (such as pH, presence of surfactants) on adhesion between copper surface and silica slurry has been studied.
4:15 PM - F12.6
A Novel Optical Technique to Measure Pad-Wafer Contact Areain Chemical-Mechanical Polishing.
Carolina Elmufdi 1 , Gregory Muldowney 1
1 Pad Engineering Research Group, Rohm and Haas Electronic Materials CMP Technologies, Newark, Delaware, United States
Show AbstractReal contact area between a CMP polishing pad and wafer is a key factor in local contact pressure, friction, and pad wear, all of which play a role in material removal and defect formation. However, traditional solid contact measurements are difficult to apply to CMP due to the physical properties and low-pressure operating conditions of polishing pads. As a result, most treatments of CMP contact mechanics rely heavily on theoretical estimates of contact area with minimal experimental verification. We introduce a new optical method that circumvents these difficulties to quantify the real solid contact area during polishing. Confocal reflectance interference contrast microscopy (C-RICM) uses a single focal plane to image the pad-wafer contact interface within a thickness of up to a few nanometers. A sapphire cover slip is substituted for the wafer to provide optical transparency and to match the index of refraction of the pad material. Imaging the pad surface through the cover slip reveals areas of no reflection (intimate pad-cover slip contact), areas of reflection (non-contact), and interference fringes (areas within a few nanometers of contact). The C-RICM method was validated using micro-fabricated polishing pads having uniform arrays of cylindrical surface structures of known contact area. Experiments conducted on filled polyurethane polishing pads revealed that the real contact area is less than 10% of the total presented area. However Greenwood-Williamson (GW) theory, widely used in CMP material removal models, predicts a contact area at least a factor of ten smaller. The discrepancy was found to result at least in part because the individual contact zones are not elliptical as assumed in GW theory. In fact many contacting structures are crescent-shaped, occurring—unexpectedly—at the perimeter of individual pad surface pores. These findings underscore the need for accurate control of pore density and morphology in polishing pads, both in initial manufacture and surface conditioning during CMP. The C-RICM method allows non-destructive benchmarking of polishing performance in terms of pad-wafer contact, an essential measure for developing improved pad architectures that achieve lower CMP defect levels.
4:30 PM - F12.7
CMP-induced Peeling in Multi-level Ultra Low-k / Cu Interconnects.
Patrick Leduc 1 , Thierry Farjot 1 , Mylene Savoye 1 , Sylvain Maitrejean 1 , Gerard Passemard 2
1 D2NT, CEA-LETI, Grenoble France, 2 , STMicroelectronics, CROLLES France
Show AbstractIn copper interconnects, for 45nm nodes and beyond, porous ultra low-k (ULK) materials (k<2.2) are identified to reduce RC delay. Because of the low mechanical properties of these materials (elastic modulus, adhesion and fracture toughness), delamination and peeling can be observed during their integration, especially during Chemical Mechanical Polishing (CMP). It was previously shown [1] that, for a given stack, delamination is driven by the work done against the friction force whatever are pressures and platen speeds respectively from 1psi to 6psi and from 30rpm to 150rpm. A good correlation was found between adhesion of the weakest interface (SiC/ULK) and wafer peeling. During integration steps, such as deposition, thermal treatments and CMP, the stack undergoes numerous mechanical solicitations. This paper will study CMP-induced delamination when the number of dielectric layers is increasing. Experiments were performed using a multi-layer stack on 200mm wafers. Three levels of spin-on MSQ (methylsilsesquioxane) materials between SiC interlayer were deposited. The stack adhesions were tuned by applying plasma treatments. The stacks were metallized with TiN barrier and copper, and then annealed. They were finally polished by steps of 15s. During the CMP process, the wafer-pad friction was monitored, and the peeling percentage within wafer is measured after each polish step. The stress was measured after each deposition on the first, second and third dielectric sandwich. The critical energy release rates of each stack were measured by four points bending before and after polishing.Thanks to these experiments, a significant increase of wafer peeling when the number of dielectric layers increases is observed and quantified. In parallel, the critical energy release rate measured by bending is decreasing between 5% and 10% with the addition of a dielectric SiC/ULK/SiC sandwich on the stack, which correlates well with the CMP peeling test. An explanation is given by considering the effect of the residual stress of the deposition on the underlying interfaces. Effect of CMP process on SiC/ULK interface adhesion is also studied. Results are discussed with respect to peeling measurements during CMP.In this contribution, we present a correlation between adhesion, residual stress and delamination during CMP. The effect of CMP applied stress on interface adhesion is also discussed.References [1] P. Leduc et al., proceedings of IITC 2005
4:45 PM - F12.8
Asperity-Scale Fluid Flow and Heat Transfer in Chemical Mechanical Planarization.
Gregory Muldowney 1
1 , Rohm and Haas Electronic Materials CMP Technologies, Newark, Delaware, United States
Show Abstract5:00 PM - F12.9
Evaluation of Inhibitors for ECMP of Copper UsingElectrochemical Quartz Crystal Microbalance (EQCM) Technique
Ashok Muthukumaran 1 , Viral Lowalekar 1 , Srini Raghavan 1
1 Materials Science and Engineering, The University of Arizona, Tucson, Arizona, United States
Show AbstractChemical formulations for the electrochemical mechanical planarization (ECMP) of copper must contain constituents that are stable at anodic potentials. A key component of the formulation is a corrosion inhibitor, which is required to protect low lying areas while higher areas are selectively removed. Organic compounds, which adsorb on copper at low overpotentials and form a film by oxidation at higher overpotentials, may be particularly useful for ECMP. The objective of this work is to evaluate the effect of certain redox inhibitors on copper dissolution in oxalic acid based systems using an electrochemical quartz crystal microbalance (EQCM) technique. By recording current as well as mass changes during the application of potential to electrodeposited copper films, the extent and mechanism of inhibition of two thiol based inhibitors has been explored. The performance of these inhibitors during abrasion of galvanostatically held copper films with a pad has also been investigated.