Chairs

Jeffrey C. Gelpey Mehmet Öztürk
AST Elektronik USA, Inc. North Carolina State University

Randhir P.S. Thakur Anthony Fiory
Micron Technology, Inc. AT&T Bell Laboratories

Fred Roozeboom
Philips Research

Symposium Support

AG Associates
AST Elektronik
CVC Products, Inc.
Mattson Technology

*Invited Paper

SESSION N1: EVALUATION, MODELING &
TEMPERATURE CONTROL
Chair: Jeffrey C. Gelpey
Tuesday Afternoon, April 9
Sunset A

1:30 P.M. *N1.1
THE ROLE OF THERMAL RADIATIVE PROPERTIES OF SEMICONDUCTOR WAFERS IN RAPID THERMAL PROCESSING, P.J. Timans, AG Associates, San Jose, CA.

2:00 P.M. N1.2
SEMATECH'S EVALUATION OF APPLIED MATERIALS' RAPID THERMAL PROCESSOR FOR 0.25 um TECHNOLOGIES, Terrence J. Riley, Advanced Miceo Devices, Austin, TX; Arun K. Nanda, AT&T Bell Laboratories, Orlando, FL; Gary Miner, Applied Materials, Santa Clara, CA; and Lino A. Velo, CVC Products, Rochester, NY.

2:15 P.M. N1.3
MONITOR WAFER EVALUATION OF A RAPID THERMAL PROCESSOR USING SEMATECH METHODOLOGIES, Arun K. Nanda, AT&T Bell Laboratories, Orlando, FL; Terrence J. Riley, Advanced Micro Devices, Austin, TX; Lino A. Velo, CVC Products, Rochester, NY; and Gary Miner, Applied Materials, Santa Clara, CA.

2:30 P.M. N1.4
MINIMIZATION OF RTP PROCESS UNIFORMITY VARIANCE BY DESIGN OF EXPERIMENTS, K.L. Knutson and T.L. Cooper, AG Associates, San Jose, CA.

2:45 P.M. BREAK

3:15 P.M. N1.5
MONTE CARLO THERMAL MODEL OF AN INTEGRATING LIGHT PIPE FOR RAPID THERMAL PROCESSING, David P. DeWitt, Jason Thomas, Purdue University, School of Mechanical Engineering, West Lafayette, IN.

3:30 P.M. N1.6
THE EFFECT OF MULTILAYER PATTERNS ON THERMAL STRESS DURING RAPID THERMAL PROCESSING, J.P. Hebb, Massachusetts Institute of Technology, Department of Mechanical Engineering, Cambridge, MA; and K.F. Jensen, Massachusetts Institute of Technology, Cambridge, MA.

3:45 P.M. N1.7
NUMERICAL MODELING OF RADIATIVE PROPERTIES OF PATTERNED WAFERS WITH SUB-MICRON FEATURES, Peter Wong, Tufts University, Department of Mechanical Engineering, Medford, MA.

4:00 P.M. N1.8
NONLINEAR MODEL REDUCTION STRATEGIES FOR RAPID THERMAL PROCESSING SYSTEMS, S.K. Banerjee, J.V. Cole, K.F. Jensen, Massachusetts Institute of Technology, Department of Chemical Engineering, Cambridge, MA; and A. Emami-Naeini, Integrated Systems Inc., Santa Clara, CA.

4:15 P.M. N1.9
APPLICATION OF HOLOGRAPHIC INTERFEROMETRY TO FLOW PATTERN VISUALIZATION IN A RTCVD REACTOR, Jörg Pezoldt, TU Ilmenau, Institut für Festkörperelektronik, Ilmenau, Germany; and Yulya P. Rainova, Moscow State Institute of Electronic Engineering, Department of Physical Chemistry Fundamentals of Moscow, Moscow, Russia.

4:30 P.M. N1.10
STRATEGIES FOR THE REDUCTION OF PATTERN EFFECTS, A. Kersch, T. Schafbauer, Siemens AG, Corporate Research and Development, München, Germany; and L. Deutschmann, AST elektronik, Dornstadt, Germany.

SESSION N2: RAPID THERMAL ANNEALING:
DIFFUSION AND DEFECTS
Chair: Anthony Fiory
Wednesday Morning, April 10
Sunset A

8:30 A.M. *N2.1
HOW RAPID THERMAL PROCESSING CAN BE A DOMINANT SEMICONDUCTOR PROCESSING TECHNOLOGY IN THE 21ST CENTURY, R. Singh, R. Sharangpani, Y. Chen, D.M. Dawson, K.F. Poole, Clemson University, Department of Electrical and Computer Engineering, Clemson, SC; A. Rohatgi, Georgia Institute of Technology, School of Electrical Engineering, Atlanta, GA; S. Narayanan, Solarex Corporation, Frederick, MD; and R.P.S. Thakur, Micron Technology Inc., Boise, ID.

9:00 A.M. N2.2
THE EFFECT OF RAPID THERMAL ANNEALING ON LDD AND SOURCE/DRAIN DRIVE-IN OPERATIONS, B. Nguyenphu, AT&T Microelectronics, Orlando, FL; A. Nanda and S. Chittipeddi, SEMATECH, Austin, TX.

9:15 A.M. N2.3
EFFECTS OF A POST-EMITTER RTP ON BIPOLAR NPN HFE DEGRADATION LIFETIME FOR 1.0uM AND 0.8uM BiCMOS PROCESS, William Leitz, Gaurang Modi, Nitin Parekh, Edwin Sabin and R.V. Taylor, Silicon Systems Inc., Santa Cruz, CA.

9:30 A.M. N2.4
SIZE-DISTRIBUTION OF END-OF-RANGE DISLOCATION LOOPS IN SILICON-IMPLANTED SILICON, G.Z. Pan, K.N. Tu, University of California at Los Angeles, Department of Materials Science and Engineering, Los Angeles, CA; and S. Prussin, University of California at Los Angeles, Department of Electrical Engineering, Los Angeles, CA.

9:45 A.M. N2.5
SELF-INTERSTITIAL SUPERSATURATION DURING OSTWALD RIPENING OF END-OF-RANGE DEFECTS IN ION-IMPLANTED SILICON, M. Seibt, Universität Göttingen, Institution IV Physikalisches Institut der, Göttingen, Germany.

10:00 A.M. BREAK

10:30 A.M. N2.6
RTA PROCESSING OF W-POLYCIDE DUAL-GATE SUB-MICRON STRUCTURES FOR LOW-VOLTAGE CMOS TECHNOLOGY, J. Bevk, M. Furtsch, G. Georgiou, S.J. Hillenius, D. Schielein, T. Schiml, P.J. Silverman, AT&T Bell LAboratories, Murray Hill, NJ; and H.S. Luftman, AT&T Bell Laboratories, Breinigsville, PA.

10:45 A.M. N2.7
MEASUREMENT OF LATERAL DOPANT DIFFUSION IN RAPID THERMAL ANNEALED W-POLYCIDE GATE STRUCTURES, T. Schiml, J. Bevk, M. Furtsch, G. Georgiou, R. Cirelli, W. Mansfield, P.J. Silverman, AT&T Bell Laboratories, Murray Hill, NJ; and H.S. Luftman, AT&T Bell Laboratories, Breinigsville, PA.

11:00 A.M. N2.8
DEFECT ACTIVATION IN HYDROGEN PLASMA-TREATED Si: RTA EFFECTS, A. Tanabe, NEC Corporation, Microelectronics Research Laboratory, Kanagawa, Japan; S. Ashok, Pennsylvania State University, University Park, PA; D. Theodore, Motorola Inc., Mesa, AZ.

11:15 A.M. N2.9
SIMULTANEOUS DOPANTS DIFFUSION AND SURFACE PASSIVATION IN A SINGLE RAPID THERMAL CYCLE, A. Slaoui, A. Lachiq, L. Ventura and J.C. Muller, Laboratoire PHASE (UPR 292 CNRS), Strasbourg, France.

11:30 A.M. N2.10
MECHANISM OF ENHANCED DIFFUSION OF IMPURITIES FROM IMPLANTED SILICON LAYERS DUE TO RAPID THERMAL ANNEALING, V. Kozlovski, L. Zakharenkov, Technical University, Department Experimental Physics, St. Petersburg, Russia.

11:45 A.M. N2.11
GENERAL KINETIC RULES FOR RAPID THERMAL PROCESSING, Edmund G. Seebauer and Roderick Ditchfield, University of Illinois, Chemical Engineering Department, Urbana, IL.

SESSION N3: METALLIZATION
Chair: Randhir P.S. Thakur
Wednesday Afternoon, April 10
Sunset A

1:15 P.M. N3.1
EFFECT OF NITROGEN DIFFUSION IN Ti AND Ti/TiN FILMS FOR FUTURE DRAM BIT LINE INTERCONNECTS AND PLUGS, John Mark Drynan, Kuniaki Koyama, NEC Corporation, ULSI Device Development Laboratories, Kanagawa, Japan.

1:30 P.M. N3.2
POST METALLIZATION DAMAGE RECOVERY USING RAPID THERMAL PROCESSING (RTP), R.P.S. Thakur and F. Gonzalez, Micron Technology Inc., Boise, ID.

1:45 P.M. N3.3
ULTRATHIN COBALT SILICIDE FORMATION USING A RAPID THERMAL PROCESSOR OF UNIQUE DESIGN, Peter Rushbrook and Ashur Atanos, Mattson Technology Inc., Fremont, CA.

2:00 P.M. N3.4
STUDY OF COBALT SALICIDE FABRICATION ON SUBQUARTER MICRON POLYSILICON LINES, Wei-Ming Chen, AR Sitaram Advanced Products Research and Development Laboratory Motorola, Austin, TX; Scott Pozder, Young Limb, Semiconductor Technology Laboratory Motorola, Austin, TX.

2:15 P.M. N3.5
IMPROVEMENT IN PLATINUM SILICIDATION FOR 0.8 um BICMOS PROCESS, Suketu Parikh, Gaurang Modi and Samuel Nagalingam, Silicon Systems Inc., Santa Cruz, CA.

2:30 P.M. N3.6
MODELING OF DEVICE CHARACTERISTICS AS FUNCTION OF Ti SALICIDE RAPID THERMAL PROCESSING PARAMETERS FOR DEEP-SUB-MICRON CMOS TECHNOLOGIES, Jorge A. Kittl, Douglas A. Prinslow, George Misium and Michael F. Pas, Texas Instruments Inc., Dallas, TX.

2:45 P.M. BREAK

3:15 P.M. N3.7
A 200 MM. RTP TiSi2 PROCESS DEVELOPED USING GAS FLOW ENGINEERING CONCEPTS, Steven D. Marcus and Zsolt Nenyei, AST Electronik GmbH, Dornstadt, Germany.

3:30 P.M. N3.8
CORRELATION BETWEEN THE STANDARD DEVIATION OF SHEET RESISTANCE MEASUREMENTS AND THE TEMPERATURE OF RAPID THERMAL PROCESSING, X.W. Lin and D. Pramanik, VLSI Technology, Inc., San Jose, CA.

3:45 P.M. N3.9
IN SITU RAPID THERMAL HYDROGENATION PRETREATMENT OF Ti FOR SALICIDE RTA, K. Ando, T. Ishigami, Y. Matsubara, T. Horiuchi and S. Nishimoto, NEC Corporation, ULSI Device Development Labs, Kanagawa, Japan.

SESSION N4: NOVEL RT PROCESSES
Chair: Chuck Schietinger

4:00 P.M. *N4.1
UV PHOTOANNEALING AND RTP OF THIN SOL-GEL FILMS, R.E. Van de Leest, Philips Research Laboratories, Eindhoven, Netherlands.

4:30 P.M. N4.2
RAPID THERMAL PROCESSING: A NEW TECHNIQUE IN THIN FILM RECORDING HEAD PRODUCTION? Fred Roozeboom, Jaap Ruigrok, Philips Research, Eindhoven, Netherlands; Herbert Kegel, Manfred Falter and Heinrich Walk, AST Elektronik, Dornstadt, Germany.

4:45 P.M. N4.3
SiC PREPARATION IN THE PULSED SOURCE WITH EXPLOSIVE ION EMISSION, Sergey A. Koreney, Joint Institute for Nuclear Research, Dubna, Russia.

5:00 P.M. N4.4
PULSED HIGH CURRENT ION AND ELECTRON BEAM PROCESSING EQUIPMENT FOR RTP, Sergey A. Korenev, Joint Institute for Nuclear Research, Dubna, Russia; and Anthony J. Perry, ISM Technologies Inc., San Diego, CA.
SESSION N5: DIELECTRICS
Chair: Tony Speranza
Thursday Morning, April 11
Sunset A

8:30 A.M. N5.1
STUDIES OF THE EFFECT OF VARIOUS GAS SPECIES ON Si-SiO2 INTERFACE CHARGES AND SURFACE ROUGHNESS FOR RAPID THERMAL DEPOSITED GATE OXIDES, Amr M. Bayoumi and John R. Hauser, North Carolina State University, Department of Electrical Computer and Engineering, Raleigh, NC.
8:45 A.M. N5.2
INFLUENCE OF HCl ON RAPID THERMAL OXIDES, G.A. Hames, North Carolina State University, Department of Electrical Engineering, Raleigh, NC; S.E. Beck, Air Products and Chemical Inc., Allentown, PA; W.K. Henson and J.J. Wortman, North Carolina State University, Department of Electrical Engineering,, Raleigh, NC.

9:00 A.M. N5.3
THIN NITRIDE FILMS - PUSHING THE LIMITS USING RAPID THERMAL PROCESSING, Scott J. DeBoer and Randhir P.S. Thakur, Research and Development, Micron Technology, Inc., Boise, ID.

9:15 A.M. N5.4
BONDED-H IN NITRIDED GATE DIELECTRICS DEPOSITED BY PLASMA CVD AND SUBJECTED TO RAPID THERMAL ANNEALING, G. Lucovsky and H. Niimi, North Carolina State University, Department of Physics, Materials Science and Engineering and Electrical and Computer Engineering, Raleigh, NC.

9:30 A.M. N5.5
NITRIDED GATE DIELECTRICS AND CHARGE-TO-BREAKDOWN TEST, Sima Dimitrijev, Barry H. Harrison, Denis Sweatman and Philip Tanner, Griffith University, School of Microelectronics and Engineering, Brisbane, Australia.

9:45 A.M. BREAK

10:15 A.M. N5.6
CHARACTERISATION OF DIELECTRIC DAMAGE IN MOS CAPACITORS BY A NEW CURRENT TRANSIENT MEASUREMENT TECHNIQUE, Philip Tanner, Barry H. Harrison, Sima Dimitrijev, Griffith University, Microelectronics, Queensland, Australia; and Y.T. Yeow, University of Queensland, Department of Electrical Engineering, Brisbane, Australia.

10:30 A.M. N5.7
IN-LINE CORRELATION OF NO NITRIDED OXIDES GROWN IN A SINGLE REACTOR, I. Sagnes, D. Laviale, France Telecom, CNET-CNS, Meylan, France; F. Martin, CEA-LETI/DMEL, Grenoble, France; F. Glowacki and L. Deutschman, AST Elktronik Daimlerstrabe, Dornstadt, Germany.

10:45 A.M. N5.8
RAPID THERMAL OXIDATION OF SILICON IN MIXTURES OF OXYGEN AND NITROUS OXIDE, John M. Grant and Zia Karim, Sharp Microelectronics Technology, Department of Process Technology, Camas, WA.

11:00 A.M. N5.9
DEVELOPMENT OF A CLUSTER TOOL AND ANALYSIS OF DEPOSITION OF SILICON OXIDE BY TEOS/O2 PECVD, Nilton I. Morimoto, University of Sao Paulo, Department of Electronic Engineering, Sao Paulo, Brazil; and Jacobus W. Swart, University of Campinas, Department of Electrical Engineering, Sao Paulo, Brazil.

11:15 A.M. N5.10
LOW-TEMPERATURE-OXIDATION PROCESSING WITH HIGH-PURITY OZONE, Akira Kurokawa, Shingo Ichimura, Electrotechnical Laboratory, Tsukuba, Japan; Kang Hea Jae, Chungbuk National University, Department of Physics, Cheongju, Korea; and Moon Dae Won, Korea Research Institute of Standards and Science, Taejon, Korea.

11:30 A.M. N5.11
GOI IMPACT OF Cu, Ni AND Al ATOMS ON THE WAFER SURFACE PRIOR TO RTO AND FURNACE OXIDATIONS, Wolfgang Aderhold, Nitsh Shah, AG Associates, Process Technology Department, San Jose, CA; and Edmund P. Burte, Fraunhoffer Institute, Schottky, Germany.

SESSION N6: EVALUATION, MODELING &
TEMPERATURE CONTROL II
Chair: Fred Roozeboom
Thursday Afternoon, April 11
Sunset A

1:30 P.M. *N6.1
WAFER TEMPEATURE MEASUREMENT: STATUS UTILIZING OPTICAL FIBERS, Chuck Schietinger and Earl Jensen, Luxtron/Accufiber, Portland, OR.

2:00 P.M. *N6.2
EMISSIVITY INDEPENDANT TEMPERATURE CONTROL-A SIMPLE, LOW COST SOLUTION-HOTLINER, S. Marcus, AST Electronik USA, Tempe, AZ; Z. Nenyei, AST Electronik GmbH, Dornstadt, Germany; and R. Bremensdorfer, AST Electronik USA, Tempe, AZ.

2:30 P.M. N6.3
TEMPERATURE CONTROL MONITORING BY RIPPLE PYROMETRY IN RAPID THERMAL PROCESSING (RTP), Minseok Oh, AT&T Bell Laboratories, Murray Hill, NJ; Binh Nguyenphu, AT&T Microelectronics, Orlando, FL; Mark H. Hansen and Anthony T. Fiory, AT&T Bell Laboratories, Murray Hill, NJ.
2:45 P.M. N6.4
EFFECT OF BACKSIDE REFLECTION ON SILICON EMISSIVITY AND TEMPERATURE MEASUREMENTS, H. Xu and J.C. Stum, Princeton University, Department of Electrical Engineering, Princeton, NJ.

3:00 P.M. BREAK

3:30 P.M. N6.5
IN SITU TEMPERATURE MEASUREMENT AT RTP FACILITIES, Jirgen Wagner, Fraunhofer Institute for Integrated Circuits, Electronic Systems Department, Erlangen, Germany; and Friedrich G. Boebel, Siemens AG, Department of Semiconductors, Erlangen, Germany.

3:45 P.M. *N6.6
COMMERCIAL RTP - A SEMATECH PERSPECTIVE, Tony Speranza, IBM, Burlington, VT; Terry Riley, Advanced Micro Devices, Austin, TX; Kenneth Torres, Arun Nanda, AT&T Bell Laboratories, Orlando, FL; Franz Geyling, Burt Fowler, Motorola, Austin, TX; and Don Lindholm, SEMATECH, Austin, TX.

4:15 P.M. N6.7
EMISSIVITY INDEPENDENT PROCESS CONTROL IN A SHORT WAVELENGTH ARC LAMP RTP CHAMBER, Marcel E. Lefrancois, David M. Camm and Brendon J. Hickson, Vortek Industries Ltd., Vancouver, Canada.

4:30 P.M. N6.8
PATTERN RELATED NON-UNIFORMITIES DURING RAPID THERMAL PROCESSING, R. Bremensdorfer, AST Electronik USA, Tempe, AZ; Z. Nenyei, AST Electronik GmbH, Dornstadt, Germany; and S. Marcus, AST Electronik USA, Tempe, AZ.

4:45 P.M. N6.9
ESTIMATION OF EMISSIVITY OF A WAFER IN AN RTP CHAMBER BY A DYNAMIC OBSERVER, Sergey Belikov, New Jersey Institute of Technology, Department of Optoelectronics, Newark, NJ; Bernard Friedland, New Jersey Institute of Technology, Department of Electrical and Computer Engineering, Newark, NJ; and N.M. Ravindra, New Jersey Institute of Technology, Department of Physics, Newark, NJ.

SESSION N7: RTCVD OF Si and SiGe
Chair: Mehmet Öztürk
Friday Morning, April 12
Sunset A

8:30 A.M. N7.1
SUB-HALF MICRON ELEVATED SOURCE/DRAIN MOSFEETS BY LOW TEMPERATURE SELECTIVE EPITAXIAL DEPOSITION, J. Sun, R.F. Bartholomew, K. Bellur, P.A. O'Neil, A. Srivastava, K.E. Violette, M.C. Öztürk, C.M. Osburn, North Carolina State University, Department of Electrical and Computer Engineering, Raleigh, NC.

8:45 A.M. N7.2
SELECTIVE DEPOSITION OF SILICON AND SiGe ALLOYS BY RAPID THERMAL CHEMICAL VAPOR DEPOSITION, John M. Grant, Lynn R. Allen and Ming Ang, Sharp Microelectronics Technology, Department of Process Technology, Camas, WA.

9:00 A.M. N7.3
LOW TEMPERATURE SELECTIVE SILICON DEPOSITION USING Si2H6 AND Cl2 IN AN ULTRA HIGH VACUUM RAPID THERMAL CHEMICAL VAPOR DEPOSITION REACTOR: INVESTIGATIONS INTO SELECTIVITY ROBUSTNESS AND EPITAXIAL QUALITY, Patricia A. O'Neil, Katherine E. Violette and Mehmet C. Oztürk, North Carolina State University, Department of Electrical Engineering, Raleigh, NC.

9:15 A.M. N7.4
COMBINED PLASMA AND RAPID THERMAL PROCESSING FOR DEPOSITION OF DOPED POLY-CRYSTALLINE-Si ELECTRODES ON ULTRATHIN GATE IXIDES, D. Wolfe, K. Christensen, D.M. Maher and G. Lucovsky, North Carolina State University, Departments of Materials Science and Engineering, Physics and Electrical and Computer Engineering, Releigh, NC.

9:30 A.M. N7.5
SILICON HOMOEPITAXY BY RAPID THERMAL PROCESSING CHEMICAL VAPOR DEPOSITION AT ATMOSPHERIC-PRESSURE (RT-APCVD), R. Monna, A. Slaoui, D. Angermeier and J.C. Muller, Laboratoire PHASE (UPR 292 CNRS), Strasbourg, France.

9:45 A.M. BREAK

10:15 A.M. *N7.6
RAPID THERMAL CHEMICAL VAPOR DEPOSITION OF DOPED AND UNDOPED POLYSILICON FOR DEVICE APPLICATIONS, S.C. Sun, National Nano Device Laboratory, Hsinchu, Taiwan.

10:45 A.M. N7.7
ELECTRON CYCLOTRON RESONANCE IN STRAINED Si AND SiGe CHANNELS ON RELAXED SiGe BUFFERS GROWN BY RTCVD, C.W. Liu, National Chunghsing University, Department of Electrical Engineering, Taichun, Taiwan; and V. Venkataraman, Indian Institute of Science, Department of Physics, Bangalore, India.

11:00 A.M. N7.8
MEMORY EFFECT IN RTCVD EPITAXY OF SI AND SiGe, G. Ritter, B. Tillack and D. Wolansky, Institute of Semiconductor Physics, Frankfurt (Oder), Germany.


The following exhibitors have identified their products and services as directly related to your research:

Academic Press
American Institute of Physics
Continental Electronics Corp.
CVC Products, Inc.
Elsevier Science, Inc.
Heraeus Amersil, Inc.
IOP Publishing, Inc.
Kluwer Academic Publishers
LUXTRON Corporation
Philips Semiconductors/Materials Analysis Group
Voltaix, Inc.

See page 6 for a complete list of exhibitors.