Resistive switching RAM (RRAM) represents one of the most promising future emerging technologies for post-Flash high density memories [1] due to their low power, high speed and great scalability. However, many issues still remain to be solved, in particular in the low current regime, where variability of relevant parameters, such as high and low resistance states [2-4], and random telegraph noise (RTN) [4-8] constitute serious obstacles to the reliability of the technology.
In this paper we address variability with a novel Monte Carlo model. Based on a Poisson statistic [2-4], set and reset transitions are seen as an injection of ions, or defects, each of them facing different Coulomb barriers which facilitate or, instead, block their motion inside the oxide layer. In this way, high current compliances lead to low variability due to the fact that many defects are injected, thus the effect of the random barriers is averaged. On the contrary, low current compliances bring elevated variability due to the reduced number of injected defects, hence no average effect is present. The model allows for a description of the switching statistics of high-low resistance, reset current and voltage, thus providing an extensive physical vision of the phenomenon.
Another issue is RTN noise that affects the resistance states at low voltages. The origin resides in the random fluctuation of a trap between two states, e. g. neutral and negative charge. Two dependences can be found. One is the size-dependence of the fluctuation [5,9,10], in fact the relative resistance change is related to the conductive filament diameter. In fact, the trap partially or totally depletes from electrons the conductive filament, obtaining lower or higher RTN fluctuations. To capture this effect, a 3D finite element model has been implemented, which solves the carrier transport equations and gives a detailed vision of the RTN transition. The second dependence is instead related to the bias [3], namely, switching times from one resistance state to the other are thermally activated through the Joule heating produced by the flowing current, hence the transition rates increase at higher voltage, leading to an average between the two resistance states. To model the RTN kinetics, the model also solves the Fourier equation, giving the temperature in the trap's position and, thus, the transition rates.
[1] K. Prall, et al., Proc. IEEE IMW 1 (2012).
[2] S. Balatti, et al., IEEE Electron Device Lett. 34, 861 (2013).
[3] S. Ambrogio, et al., IEDM Tech. Dig., 31.5, (2013).
[4] A. Fantini, et al., Proc. IEEE IMW 30 (2013).
[5] D. Ielmini, et al., Appl. Phys. Lett. 96, 053503 (2010).
[6] Y.-W. Lian, et al., IEEE Electron Device Lett. 33, 973 (2012).
[7] F. M. Puglisi, et al., Solid-State Electronics 84, 160 (2013).
[8] P. Huang, et al., IEDM Tech. Dig. 2661 (2012).
[9] K. S. Ralls and R. A. Buhrman, Phys. Rev. B 44, 5800 (1991).
[10] R. Soni, et al., J. Appl. Phys. 107, 024517 (2010).

A Resistive RAM is a resistor with memory functionality: Its resistance can be electrically tuned and “stored” in a nonvolatile way. It can be very simply fabricated from a metal-insulator-metal structure. Despite large research efforts, resistive device applications are only at the emerging stage, and basic research is still needed. Though it is now accepted that resistance variation proceeds through defects creation in OxRAM, several hypothesis have been put forward to explain defects origin, such as redox reactions at electrodes or field-induced defect generation in the bulk.
We have previously discussed on a global model for the understanding and optimization of mechanisms at the origin of Set and Reset processes in HfO2 OxRAM [1]. We have shown that oxygen vacancies are mainly created by hot electron injection, with preferential injections through grain boundaries as proposed by Bersuker et al[2]. The bottom electrode work function as well as the built in potential of the device control the injection mechanisms and so the “filament” strength and the reset capability. Top electrode morphology and its affinity to oxygen impact the reset of the device (an oxygen reservoir effect with back-diffusion of oxygen ions). Most of these results were obtained thanks to the complementary study of MIM devices through I-V cycles and CVS (constant voltage stress measurements) [3-4].
We propose here to show how, by combining I-V cycles, CVS and CCS (constant current stress), one can obtain information on the nature of the conductive “filament”. This is illustrated by using several different metals as top and bottom electrodes. As an example, with silver as top electrode, the HfO2 MIM device behaves as a CBRAM while it is OxRAM with gold. For these two examples, absorption current following by SILC (stress induced leakage current) is observed in the CVS mode with gold while only the absorption current is observed with silver. With copper the memory presents a reduced forming voltage, also observed with Ti, which can help to decrease the high overshoot current and so improve the reliability of devices. Therefore impact of copper and the metallic ions diffusion or not through the oxide is discussed. Depending on the metallic electrode nature, I(t) curves obtained in the CVS mode may show a parabolic behaviour: the current is found to increase, to reach a maximum and then to decrease as a function of time. This effect is more pronounced for electrode with high thermal conductivity such as tungsten. Based on this result, impact of the thermal conductivity on reset is discussed. In the same manner, the constant current stress shows several different behaviours as a function of the metallic electrode.
[1] C. Mannequin et al, MRS Spring Meeting 2013
[2] G. Bersucker et al, J. Appl. Phys.110 (2011) 124518
[3] C. Mannequin et al, J. Appl. Phys.112 (2012) 074103
[4] P. Gonon et al, J. Appl. Phys.107 (2010) 074507

One of the major issues in RRAM technology, which may jeopardize its introduction as a viable non-volatile option for NAND replacement, is variability of device characteristics, both device-to-device and cycle-to-cycle in the same device. In order to mitigate excessive variability, we need to identify its sources, which may have both as-fabricated (initial structure) and operation-induced (associated with forming and set-reset processes) components. Variations in the conductivity of high and low resistive states are intrinsically linked to a physical mechanism governing RRAM transitions between these states. In this presentation, we discuss the RRAM dielectric structural features, which determine device operation processes and contribute to RRAM variability.

There is presently an extensive effort to develop non-volatile resistive random access memories (RRAM) based on metal oxides, particularly those made of high K oxides such as HfO2. The general storage processes have been described by Waser et al [1], DeGraeve [2], Bersuker [3], Shiraishi [4] and others. The experimental performance of the different oxides has been compared [5]. It is interesting to understand the detailed atomistic processes in order to understand the best material. The general mechanism is that a conductive filament of oxygen vacancies is formed across the film in a forming step; oxygen vacancies then migrate towards the tip of a partly formed filament, or disperse away from this tip into the oxide, in the SET and RESET processes. The filament in the ON state has a metallic conductivity with small positive temperature coefficient of resistance, but is strongly semiconducting in the OFF state. The partly formed filament acts as a metallic tip, with a high electric field at its tip. Charged oxygen vacancies migrate towards this tip. Inside the tip is metallic, with no electric field, so further increases in vacancy concentration are not needed. The high current density in the filament also creates O vacancy/ O interstitial Frenkel pairs.
The energy parameters of these various processes are calculated at the M/MOx oxygen chemical potential (O poor limit). The migration barriers in the different charge states, and the various 0/n+ transition levels with respect to the work functions of the metal electrodes are calculated, for the popular oxides, HfO2, TiO2, Ta2O5, Al2O3. Al2O3 has the largest migration barriers and defect formation energies. Ta2O5 the smallest migration barriers.
1. R Waser, et al, Adv Mats 21 2632 (2009)
2. R DeGraeve, et al, Tech Digest VLSI (2013)p8.1; Tech Digest VLSI (2012); S Clima et al, APL 100 133102 (2012); L Roux, et al, VLSI (2013) T12-1, S Clima, Microelec Eng (2013)
3. G Bersuker, et al, JAP 110 124518 (2011)
4. K Shiraishi et al, SSDM (2014) A7-1; K Kamiya et al, APL 100 073502 (2012); PRB 87 155201 (2013)
5. J J Yang et al, Nature Nanotechnol 3 429 (2008)

Oxygen vacancy motion and agglomeration into Magnéli phases are regularly associated with resistive switching in TiO2. However, correlations between resistivity states and defect distributions are poorly linked and require direct analysis. This study reports in situ electrical biasing of TiO2-based resistive switching devices inside the transmission electron microscope (TEM). Metal-Insulator-Metal (MIM) devices consist of W/TiO2/TiN layers fabricated by sputtering TiN on single-crystal rutile TiO2 substrates, extracting ~1.5 x 3 µm specimens and electron-beam depositing W inside a focused ion beam (FIB) system. The devices are extracted, thinned to electron transparency, and mounted to W probes inside the FIB. The in situ TEM experiments were performed using a nanomanipulated W probe to contact the device and apply electrical bias. TEM analysis coordinated with electrical biasing shows that electroformation induces Magnéli phase formation at the W/TiO2 interface that eventually leads to an abrupt resistivity drop. Further biasing extends the Magnéli phase region across the entire TiO2 layer towards the TiN interface. Selected area diffraction pattern analysis observed satellite reflections along <011> directions consistent with {011} shear structures and satellite reflection spacings consistent with oxygen deficient Magnéli phases that have metallic conductivity. Resistive switching behavior was observed in the current-voltage measurements during successive voltage sweeps. Resistivity states could also be associated with an observed ~50nm Magnéli phase free zone at the TiO2/TiN interface. Wadsley defects associated with oxygen vacancy accumulation were observed in this zone when the device was at a low resistance state and disappeared when the device was switched to the high resistance state. Further interpretation of these results is corroborated by finite element modeling of electric field and temperature distributions within the device during electrical biasing. Implications for device design and interpretation of defect influences on the acting resistive switching mechanism is discussed.

Thin film metal-insulator-metal (MIM) tunnel devices have experienced a renewal in interest for high speed applications such as optical rectennas for IR energy harvesting, IR detectors, hot electron transistors, and macroelectronics. For many of these applications, figures of merit include high asymmetry, strong nonlinearity, and fast responsivity of current vs. voltage (I-V) behavior at low voltages. The standard approach to achieving high speed rectification in an MIM device is based on Fowler-Nordheim tunneling (FNT) conduction, in conjunction with the use of asymmetric work function metal electrodes (where Phi;_M1 ne; Phi;_M2) to produce an asymmetric, polarity dependent electron tunneling barrier. The properties of single layer MIM diodes are dominated by the choice of insulator. We first report the conduction mechanism and performance of a variety of MIM devices fabricated on ultra-smooth amorphous metal bottom electrodes (ZrCuAlNi or TaN) using a variety of insulators deposited via atomic layer deposition (ALD Al₂O₃, Nb₂O₅, Ta₂O₅, HfO₂, SiO₂, and ZrO₂) and Al top electrodes. Al₂O₃, HfO₂, and SiO₂, were found to be dominated by Fowler-Nordheim conduction. In contrast, Ta₂O₅, Nb₂O₅, and ZrO₂ were found to be dominated by Schottky emission at low fields and Poole-Frenkel emission (PFE) at higher fields. The energy depth of the traps that dominate PFE in each material are estimated and are found to correspond with the energy depth of sputter induced oxygen-vacancies measured via reflection electron energy loss spectroscopy (REELS).¹ Narrow bandgap dielectrics such as Ta₂O₅ and Nb₂O₅ are attractive for MIM diodes because the small barrier heights allow for low turn-on voltages. However, because conduction is based on emission, rather than tunneling, these materials may not be suitable for high speed rectification. Recently, we showed that a nanolaminate pair of insulators (Al₂O₃/HfO₂) can be used to form MIIM diodes with enhanced performance over single layer MIM diodes and demonstrated that observed enhancements in low voltage asymmetry are due to "step tunneling," a situation in which an electron may tunnel through only the larger bandgap insulator instead of both.² Because MIIM diodes based on step tunneling require only one of the dielectrics to be dominated by tunneling, narrow bandgap dielectrics dominated by thermal emission may be combined with wider bandgap dielectrics dominated by tunneling to enable low turn-on voltage high asymmetry MIIM diodes. In this presentation, we will discuss the performance of a variety of bilayer MIIM diodes (Al₂O₃/Ta₂O₅, HfO₂/Ta₂O₅, ZrO₂/Ta₂O₅, Al₂O₃/ZrO₂, and HfO₂/ZrO₂). These results represent an additional way to engineer MIM diode operation and advance the understanding needed to manufacture high quality thin film tunnel devices for microelectronics applications.
1. S.W. King, B. French, and E. Mays, J. Appl. Phys. 113, 044109 (2013).
2. N. Alimardani and J.F. Conley, Jr., Appl. Phys. Lett. 102, 143501 (2013).

Electronic memory relying on charge trapping always faces a voltage-time dilemma: it requires a high-energy barrier for data retention (>10 years) under zero/low electrical stimuli, yet it incompatibly demands a low-energy barrier for fast programming (<100 ns) under a modest programming voltage. The dilemma may be avoided by using a high-temperature programming step, but such solution causes excessive power or damage. The dilemma thus poses a serious road block to stable yet ultrafast charge-trapping devices, such as resistive switching random access memory (RRAM).
Using a localized electron-phonon interaction as an atomic-level lever to readjust the barrier height, we have engineered a reconfigurable barrier and resolved the dilemma. We implemented this solution in nanometallic RRAM, which employs “flexible” amorphous materials with strong-electron-phonon-interaction sites where trapped electrons see a reconfigurable barrier— higher during storage and lower during programming. The interaction first converts a trapped-electron state from an unstable positive-U state to a stable negative-U state; later, its unraveling during re-programming leads to the demise of the trapped-electron state.
We present the first real-time evidence for such action using a single 10^-13 s mechanical impulse, which originates from the Lorentz force induced by an ~10^-13 s electron burst in SLAC National Accelerator Laboratory. It triggers bond distortion, reverses the stabilizing electron-phonon interaction, and causes switching from the trapped-electron state (high-resistance state) to the free-electron state (low-resistance state), without any voltage. The nanometallic RRAM can retain long-term memory and reprogram at a sub-picosecond speed, making it suitable for universal memory and possibly other applications.
References:
1. Nature Nanotechnology, 6, 237 (2011)
2. Advanced Materials, 23, 3847 (2011).
3. Advance Functional Materials, 22, 546 (2012).
4. Scientific Reports 2, 744 (2012)
5. ACS Nano 7, 2302 (2013)

Memristive devices (also known as RRAM when used for memory) are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage or current, which can be used to store and process information for computing systems beyond CMOS technologies. These devices have shown great scalability, switching speed, non-volatility, analogue resistance change, non-destructive reading, 3D stack-ability, CMOS compatibility and manufacturability. However, there are still a number of challenges facing memristive devices for real applications, including device variability and isolation in a crossbar array. This talk will discuss and address these challenges from the materials perspective.

Resistively switching devices have attracted great attention for potential use in future nonvolatile information storage. Their resistance can be changed by applying appropriate voltages. This resistive switching effect has been observed in a variety of oxide materials, e.g. SrTiO3, TiOx or TaOx. Prior to actual resistive switching of valence change memory cells an electroforming step is typically required. This initial electroforming step impacts device performance and switching variability. Thus, a thorough understanding of the physical processes involved in the electroforming process is fundamental for device optimization.
In this study, the electroforming process in strontium titanate (STO) single crystals is made visible. Transparent samples of Fe doped STO single crystal were put under temperature and longitudinal electrical stress and observed by means of high resolution transmission optical microcopy, whereby the voltage and current were being logged with time and the sample was continuously captured with a camera. For the experiment a custom sample enclosure was constructed.
In the electrocoloration process, color changes within the sample are caused by a valence change of the Fe ions, and accordingly by drift of oxygen vacancies. The colorful regions are growing and propagating towards the electrodes. At the anode Fe atoms are reduced and thus form a dark brown region, while at the cathode they are oxidized and the color turns to bright yellow. The redox reaction is therefore an indirect proof of the oxygen vacancy drift-diffusion in the bulk.
Time development and behavior of the color areas within the sample are influenced by multiple factors (voltage, current, temperature, dopant and defect concentration, ambient atmosphere, time, etc.). We study the influence of the particular parameters by capturing the progression of electrocoloration at several samples. The measurements show current and resistance change over time along with sample visual mapping.
The behavior is to some extend similar to previous published findings [1], [2], but also new phenomena are observed, i.e. the formation of lines and impermanent spots in the bulk. These are analyzed by different ex-situ characterization techniques (EDX, mösbauer spectroscopy, AFM, etc.). Furthermore, 1D drift-diffusion simulations of the temporal evolution of the oxygen vacancy distribution are performed, which represent well the initial progress of the virtual cathode region.
[1] J. Blanc, Physical Review B, 4, 3548-3557, 1971
[2] R. Waser, Journal of the American Ceramic Society, 6, 1654-1662, 1990

Nanoelectromechanical systems (NEMS) switches are a candidate "beyond CMOS" technology, with a key benefit being massively reduced power consumption. However, the reliability of the contact interface is a principal challenge for the commercialization of NEMS switches, as the electrically conducting contacting surfaces need to be able to open and close up to a quadrillion times without suffering from excessive adhesion, wear, or contamination. These failure mechanisms are not well understood, and materials that can exhibit the needed performance have not yet been demonstrated.
To develop a better understanding of the failure mechanisms, we developed a nanoscale electrical contact testing method based on atomic force microscopy (AFM) that enables billions of contact cycles in laboratory timeframes. Single asperity Pt-Pt contacts were cycled using forces and environments representative of NEMS switch operation. Contact resistance increased by up to six decades due to cycling-induced growth of insulating tribopolymer at rates that were enhanced when cycled in humid air or under the presence of a voltage. Sliding of the contact led to recovery of conductivity through displacement of the tribopolymer, suggesting a route for ameliorating contamination-induced failure.
Second, to achieve desirable switch performance, we have canvassed compatible material sets to identify those that are highly conductive, minimally adhesive, chemically inert, mechanically robust, and amenable to CMOS fabrication processes. One promising candidate is platinum silicide (Pt_xSi). Successful integration of Pt_xSi contacts into many NEMS switch architectures requires the use of amorphous silicon (a-Si), a relatively unexplored approach compared to the use of single crystal Si. We have performed the first direct characterization of the mechanical and electrical contact properties of Pt_xSi of multiple stoichiometries, formed through controlled diffusion of a-Si and platinum (Pt), in comparison with pure Pt. The silicides were produced from bilayer a-Si/Pt film stacks inside a X-ray photoelectron spectroscopy (XPS) system for in situ quantification of stoichiometry as a function of temperature and annealing time. PtSi, Pt₂Si and Pt₃Si phases could be identified and distinguished, and layers of Pt and a-Si of approximately equal thickness were shown to favor Pt-rich silicides (Pt₂Si and Pt₃Si) instead of the PtSi phase commonly observed in Pt/sc-Si silicidation. The silicides demonstrated only modest increases in contact resistance and significantly improved mechanical properties. We also demonstrate that Pt_xSi can be used to release NEMS switches with a self-formed gap caused by interfacial separation driven by shrinkage-induced tensile stress. This indicates that a-Si thickness has a direct impact on stoichiometry, which can thus be easily tuned to obtain desired properties.

In0.53Ga0.47As and atomic layer deposited (ALD) Al2O3 are among the candidates channel and dielectric materials, respectively, for future high performance III-V n-channel MOS devices. In particular, the ability to achieve large band offsets and a thermally stable interface with Al2O3 makes it an interesting choice for an interlayer dielectric between an InGaAs channel and higher-k materials. Achieving a low density of electrically active defects at the interface has been a long-standing challenge for all deposited dielectrics on III-V arsenide channels. Moreover, traps in the oxide layer may also reduce the charge in the channel and thus degrade the on-state performance of InGaAs MOSFET devices. In this presentation, we describe approaches to passivate the interface and bulk oxide defects with various treatments, like large-dose exposure of the InGaAs surface to trimethyl-aluminum (TMA) prior to ALD, atomic hydrogen dosing, and either post-ALD or post-gate metal forming gas (5% H2/95% N2) anneals (FGA).
Experimental methods employed include quantitative interface trap and oxide trap modeling[1, 2] of MOS capacitor data obtained over a range of frequencies and temperatures. We also perform x-ray photoelectron spectroscopy to characterize possible film stoichiometry changes during annealing and the oxidation state of In, Ga and As at the dielectric/channel interface. These ex-situ data will be compared with the results of in-situ scanning tunneling microscopy/spectroscopy for certain passivation schemes[3, 4]. The effects of pre- and post-dielectric defect passivation schemes will be examined for ALD-Al2O3 samples prepared on both initially-clean and well-ordered As2-decapped In0.53Ga0.47As substrates and on initially air-exposed substrates. Relevant comparisons to low-temperature ALD-grown HfO2 films on InGaAs substrates will also be reported.
References
1. H. Chen, Y. Yuan, B. Yu, J. Ahn, P.C. Mcintyre, P.M. Asbeck, M.J.W. Rodwell, and Y. Taur, IEEE Transactions on Electron Devices 59, 2383 (2012).
2. Y. Yuan, B. Yu, J. Ahn, P.C. Mcintyre, P.M. Asbeck, M.J.W. Rodwell, and Y. Taur, IEEE Transactions on Electron Devices 59, 2100 (2012).
3. W. Melitz, T. Kent, A.C. Kummel, R. Droopad, M. Holland, and I. Thayne, The Journal of Chemical Physics 136, 154706 (2012).
4. W. Melitz, J. Shen, T. Kent, R. Droopad, P. Hurley and A. C. Kummel, ESCS Transactions, 35(4) 175-189 (2011)

Two of the leading materials considered for use in post silicon n-channel regions of planar-FETs and finFETs are SiGe and InGaAs, as both of these alternatives contain high intrinsic electron mobilities. A broader range of channel materials allowing better carrier confinement and mobility could be employed if a universal control monolayer (UCM) could be ALD or self-limiting CVD deposited on multiple materials and crystallographic faces. Si-OH is a leading candidate for use as the UCM, as silicon uniquely bonds strongly to all crystallographic faces of InGa1-xAs, InxGa1-xSb, InxGa1-xN, SiGe, and Ge enabling transfer of substrate dangling bonds to silicon, which is then readily passivated by atomic hydrogen or molecular H2 (g). The surface may subsequently be functionalized by dosing with an oxidant such as HOOH(g) in order to create the UCM terminating Si-OH layer which would react with nearly any ALD precursor. This process serves in eliminating the need for metal precursor nucleation, decreasing EOT, and lowering border trap density and fixed charged associated with interfacial layers or even direct bonding of oxide to non-silicon semiconductors. This study focuses on depositing a saturated Si-H seed layer via self-limiting and saturating CVD on InGaAs(001)-(2x4) at a low substrate temperature of 250°C. XPS in combination with STS and STM were employed to study and characterize the electrical and surface properties of the saturated silicon seed layer on InGaAs(001)-(2x4).
The self-limiting and saturating CVD procedure includes a decapped In0.53Ga0.47As(001)-(2x4) surface dosed with13 MegaLangmuir of Si3H8 at a sample temperature of 250°C. The XPS spectra was recorded following the self-limiting and saturating Si3H8 CVD and shows the increase of the silicon 2p3/2 peak and the decrease in the gallium 3p3/2 peak, indicative of saturating surface coverage as compared to spectra of the clean decapped surface. Additional dosing with Si3H8 does not further increase in the silicon 2p3/2 peak nor further decrease in the gallium 3p3/2 peak areas consistent with self-limiting CVD. STM images are acquired of the In0.53Ga0.47As(001)-(2x4) surface following self-limiting and saturating CVD of Si3H8 at 250°C and post annealing, and high atomic surface order is observed.

Replacing silicon with high-mobility channel materials such as InGaAs will be surely the next evolution of MOSFET devices. Alternative materials such as High-k dielectrics and metal gates have already been successfully introduced. InGaAs based channels hold the promise of circuits operating at lower Vdd and hence consuming low power as the dynamic power roughly scales as V2dd. Two different strategies for integrating As based compounds as MOSFET channels are actually foreseen: fully depleted III-V/On Insulator or FinFET. This integration still faces many challenges like direct III-V epitaxy on Si, channel/high k interface control, and contact resistance.
We focus on the direct growth of As compounds on Si(100) 300 mm substrates. GaAs and InGaAs layers are grown by an AMAT MOCVD tool. TMIn, TMGa and TMAl are used as group III elemental precursors whereas TBAs is used as group V elemental precursor. Typical growth temperature ranges between 300 and 700°C and pressure ranges between 1 and several hundred Torr. We have studied the structural and the physical properties of GaAs, InGaAs, AlGaAs layers grown either on blanket or patterned Si(100) wafers by AFM, FIBSTEM, TEM, SIMS, µPL, cathodoluminescence, XRD. We showed an improvement of the material quality as they are elaborated in SiO2 cavity even with an aspect ratio less than 2. Antiphase boundary and dislocation densities are strongly decreased as the width of the cavity goes bellow 100 nm. By adjusting properly the growth conditions and the stack in the quantum well structure, we were able to observe room temperature micro-photoluminescence of single InGaAs QW, with In composition ranging between 10 and 53% and a total stack thickness well below 1 µm.

The scaling of logic CMOS devices requires the use of high mobility semiconductor channel materials such as InGaAs. However, the interfaces of III-V and high K oxides such as Al2O3 and HfO2 can still possess a high interface state density, D_it. Various methods have been used to lower this density, such as choice of oxide, and recently the use of nitrogen treatment of the interface. We have calculated that the replacement of the last layer of the III-V by an Al-N layer greatly reduces the interface defect state density, because N-N dimers do not form, N dangling bond states are deep in the valence band and Al dangling bond states lies higher in the conduction band [1]. This result was recently confirmed experimentally [2,3]. Here, we extend these calculations to other III-Vs such as InGaSb and GaSb where a similar behavior is found.
1. Y Guo, L Lin, J Robertson, App Phys Lett 102 091 606 (2013)
2. T Aoki et al, Tech Digest SSDM (2013) J-8-3
3. V Chobpattana... S Stemmer, App Phys Lett 102 022907 (2013)

Since the fundamental material properties of Si start to limit the ultimate scaling of nanoelectronics, new materials will have to be introduced to continue the performance scaling. Germanium, various III/V compounds, nanowires and 2D materials, such as graphene or MoS2 are potential candidates to become the next generation high mobility channel material in highly scaled devices. Direct growth of both Ge and III/V in Si STI trenches is a very attractive option for co-integration of these materials on bulk Si substrates. Gate stack optimization on Ge and III/V is a major challenge but at present various solutions are available and it can be expected that Ge and III/V will find their way into advanced technologies in the near future, either in FinFET structures or in nanowires grown directly on Si. Ultimately power consumption rather than speed is limiting the scaling roadmap. Tunnel-FETs, based on III/V or graphene, can provide good performance at lower power consumption by virtue of their improved subthreshold behavior. The combination of new materials and devices generates exciting possibilities for future technologies and will allow to continue the scaling of nano-electronics beyond the Si roadmap.

We demonstrate, for the first time, high-performance GaAs devices (nMOSFETs and pMOSFETs) that are integrated into CMOS circuits (inverters, NAND and NOR logic gates, and five-stage ring oscillators). These devices were enabled by the high-quality interface of single-crystalline La2O3 grown on GaAs(111)A by atomic layer epitaxy.

A tunnel field-effect transistor (TFET) is expected to have the feasibility of apply voltage scaling because the carrier injection by the band-to-band tunneling in TFET allows us to yield steep subthreshold swing (SS) below 60 mV/dec, which is the lower limit of conventional MOSFETs. Therefore, TFETs have attracted much attention as a strong candidate for low power device applications. However, the reported results of Si TFETs show low drain current due to the large band gap. One of the feasible solutions for mitigating this problem is to employ a Ge/Si hetero-junction source structure. A Ge/Si hetero-structure with staggered type-II band alignment can effectively reduce tunneling width in the source junction, which can simultaneously satisfy the high on/off current ratio and steep SS in the TFET operation.
In the Ge/Si hetero TFETs, tunneling currents are generated near the Ge/Si junction and, therefore, a formation of high quality Ge with abrupt doping profile and high doping concentration in Ge is important. Ion implantation for doping in Ge layers can cause generation of many defects in the Ge layers. Moreover, the formation of abrupt Ge/Si hetero-structure is very difficult because the Ge atoms can diffuse into Si during annealing.
Therefore, we grow Ge layers with in-situ boron doping by molecular beam epitaxy at extremely low temperature of 200 °C. In this study, the effects of Ge layers with different boron concentrations in the Ge layers on the performance of the nTFET are examined. The Ge layer as the p⁺-source is grown on SOI substrates. It is found that the device performance improvement including 4-times-higher drain current is obtained by increasing the boron-doping concentration from ~10¹⁶ cm^-3 to ~10²⁰ cm^-3. The large drain on/off current ratio over 6 orders of magnitude and steep subthreshold swing of 58 mV/dec are obtained.

Ge has been extensively investigated as a potential channel material for post-silicon CMOS because of its higher carrier motilities. However, smaller bandgap and higher permittivity of Ge causes severe junction leakage current and short channel effects (SCEs). Recently, silicon-on-insulator (SOI) structure has been widely investigated due to better electrostatic integrity. Therefore, germanium on insulator (GeOI) is a solution with same concept of SOI to suppress junction leakage and SCEs. Hence it is highly desirable to create a high quality Ge layer on Si substrates.
In this work, we fabricated GeOI structure on Si substrate utilizing ELO technique with wafer scale and then demonstrated high performance tensile-strained GeOI nMOSFETs.
Ge has nearly the identical lattice constant to GaAs, and AlAs in which epitaxial lift-off (ELO) processes have been demonstrated by sacrificially etching an AlAs layer. Therefore, with the proper epitaxy and ELO technique for Ge layer, Ge layer transfer onto disparate materials systems can be realized. First of all, a crystal Ge layer is epitaxially grown on GaAs substrate with an AlAs splitting layer. Then, the epitaxial Ge/AlAs/GaAs heterostructure bonds with Si substrates. By splitting at AlAs layer with HCl solvent, epitaxial Ge layer transfers on Si substrates.
Using this ELO-GeOI substrate, we fabricated the tensile strained accumulation-type GeOI nMOSFETs with in-situ phosphorus doped epitaxial SiGe stressors. After GeOI layer was thinned by wet etching process, SiO2 dummy gates were formed on the GeOI substrates. n+ SiGe (x = 0.7) layer was epitaxially grown by LP-CVD to induce the tensile stress to GeOI channel. After removing the SiO2 dummy gates, GeOI active areas were defined by mesa-isolation. Al2O3 as a gate dielectric was deposited by ALD process with O3 passivation and TaN metal gate was sputtered, followed by patterning using electron-beam lithography and RIE process. Finally, BEOL process was performed at the maximum temperature of 300 °C. An enhancement of 70% in the maximum of transconductance was observed in tensile-strained device with Lg = 60 nm compared to the unstrained device. A record-high drive current of 457 mu;A/mu;m at Vd = 1V and Vg-Vth = 1.5V among Ge nMOSFETs was observed due to the strain and low-parasitic resistance.
These results indicate that ELO-GeOI substrate has a high potential to realize Ge based CMOS as well as to integrate Ge devices with Si CMOS.
Acknowledgement
This work was supported by a grant from JSPS through the FIRST Program initiated by CSTP.

We have already demonstrated superior properties of GeO2/Ge gate stacks formed by high-pressure O2 [1]. An obvious disadvantage of this process, however, is that relatively thick GeO2 is necessarily formed. We have very recently found that the retarded oxidation rate of Ge in high-pressure O2 by slightly decreasing the oxidation temperature [2]. This is quite promising because we can achieve ultra-thin and high quality GeO2/Ge gate stacks. Furthermore, the layer-by-layer oxidation is observed [3] by oxidizing the atomically flat Ge surface [4]. Both properties are quite beneficial for Ge n-FETs with very thin GeO2 together with very high mobility at high electron density region [5].
[1] A. Toriumi et al., IEDM (2011).
[2] C. H. Lee et al., APEX (2012).
[3] C. H. Lee et al., SSDM (2013).
[4] T. Nishimura et al., APEX (2012).
[5] C. H. Lee et al., IEDM (2013).

The high hole mobility in germanium has motivated a renewed interest in this semiconductor for future electronic devices. In particular its integration as channel material in Complementary Metal Oxide Semiconductor (CMOS) architectures would improve operation speed. However, many issues still need to be addressed before Ge can be efficiently integrated in high performance MOSFETs. Among them a critical problem is to provide a high-quality interfacial layer. The recent observation by electrically detected electron spin resonance spectroscopy (EDMR) of Pb-like centers at the Ge/GeO2 interface [1-3] allowed a more systematic investigation of the passivation of this technologically relevant interface considering both the Ge(001) and the increasingly attractive Ge(111) orientations. In this work we will report on the characterization of different interfaces produced on both Ge(100) and Ge(111) substrates by Al2O3 direct growth using atomic layer deposition (ALD), and GeO2 and sulfur passivation. We will report EDMR results correlated with admittance spectroscopy of the interface traps, and deep level transient spectroscopy (DLTS) measurements.
[1] S. Baldovino, A. Molle, and M. Fanciulli, Appl. Phys. Lett. 93, 242105 (2008)
[2] S. Baldovino, A. Molle, and M. Fanciulli, Appl. Phys. Lett. 96, 222110 (2010)
[3] S. Paleari, S. Baldovino, A. Molle, M. Fanciulli, Phys Rev. Lett. 110, 206101 (2013)

The next Ultra Thin Box and Buried Silicon-On-Isolator (UTBB SOI) p- Metal-Oxide-Semiconductor generations for the 14 nm and 10 nm nodes requires very low pitch patterns and the use of Si1-xGex sources and drains (S/D) to compressively strain the channel and improve hole mobility [1]. The silicidation process consists in sequential metal/semiconductor reactions under thermal budget to reduce access resistance between active areas and interconnexions [2]. Thus, growth mechanisms must be understood in terms of texture in order to optimize the silicidation process and thermal stability [3-5]. The texture is usually extracted from blanket wafers. Because of the extrem narrow S/D area, this study is proposed to evaluate the confinement impact on Si1-xGex metallization in terms of phase texture, phase formation and thermal stability for different Ni1-yPty alloys.
As reference, the texture evolution is studied on blanket wafers by varing Pt content. Then, the Ni-rich germanosilicide texture is explored in the bottom of regular arrays of aggressive trenches, by X-ray diffraction on the D2AM synchrotron beamline (ESRF). On a 20 nm thick Si0.7Ge0.3 epitaxial layer, SiO2 trenches are patterned by e-beam lithography inside 600*600 µm2 dies. The most aggressive trench pitchs / widths / depths are 64 nm / 32 nm / 100 nm respectively which matches with targeted dimensions of the next 10 nm node. Ultrathin Ni1-yPty films are deposited in the bottom of trenches by RF-PVD followed by the Ni rich germanosilicide phase growth using a RTA annealing system at 280 °C during 30 sec. In order to extract a trend of the texture as a function of Pt content and pitch, Pt content varies from 0 at. % up to 15 at. % and the pitch from 1 µm down to 64 nm. TEM analysis are also performed to observed the bottom germanosilicide morphology (interface, grains sizeshellip;)
A significant change in texture and phase is highlighted as a function of Pt content on blanket wafers. An epitaxial theta;-Ni2Si seems to grow preferentially compared to δ-Ni2Si in presence of Pt [6]. This impacts the mono-germanosilicide texture and consequently the morphological stability. When the salicidation process is carried out in the largest trenches, this phase change is still observed as on blanket wafer. However, with the pitch size decrease, the Ni1-yPty rich germanosilicide film switches from an epitaxial texture in the largest pitch to another texture in the narrowest pitch. The Pt content promotes the epitaxial texture in small patterns, but the effect seems to be lost with pitch size reduction. The texture transition seems to occur around 100 nm pitch which corresponds to the germanosilicide grain size.
[1] M. Vinet, 2012VLSI-TSA (2012).
[2] S. Kim, IEEE Transactions on Electron Devices 49 (2002) 467.
[3] C. Detavernier, Nature 426 (2003) 641.
[4] H. Kimura, Microelectr. Eng. 88 (2011) 557.
[5] S. Gaudet, JAP 107 (2010) 093515.
[6] F. Panciera, Microelectr. Eng. 107 (2013) 167.

Frequency dispersion is a commonly observed feature in the experimental capacitance-voltage characteristics of III-V MOS devices. This characteristic has been reported on a wide variety of III-V substrates in conjunction with many different dielectrics. The conventional interface state capacitance model, which works extremely well for Si devices, does not accurately model the frequency dispersion observed in III-V systems. Different physical models have been developed to explain the origin of this frequency dispersion. One model, disorder induced gap states (DIGS), attributes this dispersion to the tunneling of carriers into a disordered region caused by oxidation of the III-V substrate. A separate model attributes this dispersion to border traps located inside and associated with the high-k dielectric. In this talk, electrical characterization, modeling and physical characterization is used to demonstrate that the observed frequency dispersion must be due to the disruption of the crystalline III-V semiconductor during oxide deposition and not due to border traps located in the high-k dielectric.
Acknowledgments: The author acknowledges the SRC Global Research Collaboration, NSF ECCS-0925844, NSF ECCS-1039988, the SRC FCRP Center for Materials, Structures, and Devices, SEMATECH, and NIST for present and past support of this work. The work to be presented here was performed with numerous people including: C. L. Hinkle, R. M. Wallace, R. V. Galatage, A. Sonnet, B. Brennan, H. Dong, D. M. Zhernokletov, M. Milojevic, F. S. Aguirre-Tostado, S. Anwar and G. Bersuker

We report recent results with InAs/InGaAs MOSFETs with self-aligned MOCVD-regrown InGaAs source and drain. On-state transconductance as large as 2.7 mS/micron have been observed in 55nm Lg devices. We will describe the role of back barrier design, vertical spacers in the high-field region, and channel quantized bandgap on off-state characteristics. We will also describe recent results with ALE-defined InGaAs finFETs, a technology with the potential for few-nm body thickness and high height/pitch aspect ratios, and discuss its potential application in low-voltage logic

InGaAs MOSFET with Gate-all-around (GAA) structure is a promising candidate for CMOS logic circuit beyond the 10nm technology node because of its high electron injection velocity and excellent immunity to short channel effects. In order to further dramatically improve the on-current and meanwhile keep the off-state under control, vertically stacked nanowire structure, we call it as 4D transistor, is introduced. In this work, InGaAs 4D GAA MOSFETs with multiple stacks of ultrathin nanowires are demonstrated. On-current over 2uA/um normalized by device width are obtained and good electrostatic control are achieved for the first time for 4D transistor due to the ultrathin nanowire structure. Junctionless MOSFET structure is used to reduce the series resistance. Meanwhile, we also report on the exploratory experiments on the vertically stacked double-gate structure first time on InGaAs MOSFETs to achieve high on-current and good electrostatic control at the same time.

Measurements of the reflectivity of low-energy electrons, typically 0 - 10 eV above the vacuum level, are known to provide a sensitive means of characterizing 2-dimensional (2D) materials such as graphene or hexagonal boron nitride (h-BN). Phenomenologically, it was found that one can determine the number of 2D layers on a substrate, and also obtain information concerning the interface between the 2D layers and the substrate [1]. However, up to now there has not been a fundamental understanding of how the measured reflectivity is determined by these quantities. A first-principles description of low-energy electron reflectivity spectra has recently been developed, yielding results that compare well with experimental data for both graphene and hexagonal boron nitride (h-BN) on various substrates [2]. Results comparing experiment and theory will be presented, from which the interface structure between the 2D material and the substrate is determined.
2D materials enable the development of a range of novel electronic devices. This presentation will focus on one such device, a SymFET (Symmetric Field-Effect Transistor) that relies on the symmetry between the valence and conduction bands in opposite graphene electrodes of a graphene-insulator-graphene (GIG) junction [3,4]. The state-of-the art in GIG and SymFET fabrication will be described, focusing on recent experimental results [5] in which negative differential resistance was observed in SymFET type devices employing h-BN for the insulator layer. The theory describing SymFET device operation will be discussed, including the aspects of energy and momentum conservation as well as the possible roles of (i) relative orientation of the two graphene electrodes, and (ii) scattering within the insulator layer.
*Work performed in collaboration with N. Srivastava, P. Mende, Q. Gao, M. Widom (Carnegie Mellon University), T. Roy, E. Vogel (Georgia Inst. Technology), A. Ismaj, R. Ruoff (Univ. Texas - Austin).
References
[1] H. Hibino et al., Phys. Rev. B 77, 075413 (2008).
[2] N. Srivastava et al., Phys. Rev. B 87, 245414 (2013).
[3] R. M. Feenstra, D. Jena, and G. Gu, J. Appl. Phys. 111, 043711 (2012).
[4] P. Zhao, R. M. Feenstra, G. Gu, and D. Jena, IEEE Trans. Electron Devices 60, 951 (2013).
[5] L. Britnell et al., Nature Comm. 4, 1794 (2013).

We demonstrate a new paradigm of electronic switches without using semiconducting channels. Metallic nanoparticles deposited on one dimensional (1D) insulators has led to the creation of room-temperature tunnel field effect transistors (TFETs).
Our TFETs are based on quantum tunneling between gold quantum dots (QDs) deposited on the insulating boron nitride nanotubes (QDs-BNNTs) [1]. We show that QDs-BNNTs are insulating at low bias voltages, but allow electron tunneling at room-temperature when sufficient potential is applied. Since the switching behaviors are based on quantum tunneling, these FETs have suppressed leakage current and contact resistance. In addition, the performances of our FETs are enhanced at shorter tunneling channel, in contrast to the short channel effects in Si devices. Thus QDs-BNNTs are advanced materials for FETs that could by-pass some of the fundamental limitations in semiconducting channels.
High-quality BNNTs were grown by the growth-vapor-trapping (GVT) approach [1]. The as-grown BNNTs are insulators with diameters of ~15-50 nm. These BNNTs are used as 1D substrates for the deposition of gold QDs by pulsed-laser deposition [2]. BNNTs are almost ideal as the substrates for the deposition of these QDs due to their uniform and controllable diameters. Furthermore, their defect-free sp² BN network makes them chemically inert to the deposited QDs, and remains electrically insulating. Scanning transmission electron microscopy (STEM) [3] suggests that the gold QDs are crystalline, and are preferentially deposited on one side of the BNNTs. These QDs form a 1D array of particles with estimated diameters ranging from about 3-10 nm and inter-dot spacing of about 1-5 nm. The transport properties of these QDs-BNNTs were characterized by a four-probe scanning tunneling microscopy (4-probe STM) [4]. We show that the turn-on voltages of this QDs-BNNT decrease from ~30V to < 0.1V as the transport length decreased [5]. These switching behaviors can be modulated by a gate potential and are fully simulated by a theoretical model. The on-off ratio of these devices is estimated to be on the order of 10⁴. Details of these results will be discussed in the meeting.
Y. K. Yap acknowledges the support from the U.S. Department of Energy, the Office of Basic Energy Sciences (Grant DE-FG02-06ER46294), the Center for Nanophase Materials Sciences at Oak Ridge National Laboratory (CNMS at ORNL) (Projects CNMS2009-213 and CNMS2012-083), and the ORNL&’s Shared Research Equipment (ShaRE) User Program (JCI).
References:
[1]. (a) Wang et al, Nanoscale2, 2028 (2010); (b) Wang et al, in Chapter 2 of B-C-N Nanotubes and Related Nanostructures (Springer, 2009); (c) Lee et al, Nanotechnology19, 455605 (2008); (d) Lee et al, Chem. Mater.22, 1782 (2010).
[2]. Wang et al, Nano Letters5, 2528 (2005).
[3]. Zhou et al, Nature Nanotech.7, 161 (2002).
[4]. Kim et al, Nano Letters10, 3096 (2010).
[5]. Lee et al, Adv. Mater.25, 4544 (2013).

In 2008, we theoretically predicted that it could be possible to stabilize a ferroelectric material at a state of negative differential capacitance, which when used as a gate insulator in a MOSFET, could reduce the subthreshold swing below the otherwise fundamental 60 mV/decade. Reducing the swing below 60mV/decade means that the overall supply voltage and power dissipation could be reduced significantly. The difference of this concept with other existing proposals to reduce the subtheshold swing in MOSFETs is that the mechanism of electron transport remains unchanged and therefore the speed of operation does not need to be traded off for lower energy dissipation. In the recent years, multiple experimental demonstration have established this concept from both fundamental and technological point of view. In this talk, I shall discuss the conceptual background and recent experimental studies regarding this concept. I shall also discuss challenges and open questions as we currently see them.

Multiferroic devices, i.e., a magnetostrictive nanomagnet strain-coupled with a piezoelectric layer, hold profound promise for ultra-low-energy computing in beyond Moore&’s law era. Such devices operate according to the principles of converse magnetoelectric effect, i.e., when a tiny voltage of few millivolts (with appropriate choice of materials) is applied across the structure, the magnetization of the magnetostrictive nanomagnet can be switched between its two stable states in sub-nanosecond switching delay while expending a minuscule amount of energy of ~1 attojoule at room-temperature [Roy, K. et al, Nature Highlight, Switching up spin, Nature 476, 375 (2011) http://www.nature.com/nature/journal/v476/n7361/full/476375c.html, Appl. Phys. Lett. 99, 063108 (2011), Phys. Rev. B 83, 224412 (2011), Scientific Reports (Nature Publishing Group) 3, 3038 (2013), J. Appl. Phys. 112, 023914 (2012)]. Such devices have been proposed not only for memory bits, but also for building logic for computing purposes [Roy, K. Appl. Phys. Lett. 103, 173110 (2013), Fashami M.S., Roy, K. et al, Nanotechnology 22, 155201 (2011)]. This study has opened up a new field called straintronics [Roy, K., SPIN 3, 1330003 (2013)] and experimental efforts to demonstrate such electric field induced magnetization switching are considerably emerging too. I would review some recent developments on building nanoelectronics using such multiferroic magnetoelectric materials for our future information processing paradigm.
In a recent development, it is shown that in a magnetostrictive nanomagnet, it is possible to achieve the so-called Landauer limit (or the ultimate limit) of energy dissipation [Roy, K., under review]. According to Landauer's principle, postulated by the famous scientist R. Landauer back in 1961, it necessarily dissipates an energy of amount kT ln(2) [~3e-21 joule at T=300 K, k is the Boltzmann constant, and T is temperature], compensating the entropy loss while erasing a bit of information. This is the foundation of the link between information and thermodynamics.
Furthermore, I will talk on the scaling limit of multiferroic devices [Roy, K., under review]. Material parameters pose an important impact over the device performance. I will discuss that how the material parameters should be tuned to achieve superior performance while scaling down the device dimensions.
On a very recent development, apart from digital computing, I will talk about how multiferroic devices, with appropriate choice of materials, can be utilized for analog computing purposes [Roy, K. and Datta S., in prep.], e.g., voltage amplification, filter. Using tunneling magnetoresistance (TMR) measurement, a continuous output voltage while varying the input voltage can be produced.
Finally, I will discuss on how exotic coupling phenomena at the interface between the ferroelectric and ferromagnetic materials can lead to highly-dense yet an ultra-low-energy computing paradigm [Roy, K., under review].

AlGaN/GaN HFETs grown on Si substrate by MOCVD are very promising in commercial applications of power devices. And high-resistivity (HR) GaN is essential to decrease parallel conduction and to ensure a good channel pinch-off. The HR-GaN buffer has been achieved by introducing higher edge-type dislocation to compensate the n-type background residual donor. However, the off-state performance of HFETs fabricated on these HR-GaN buffer layers encountered a bottleneck for further leakage current reducing, due to the poor confinement of the 2DEG, which could cause much more serious problem when the gate length (Lg) of HFET decreased for higher frequency operation of the transistors. The introduction of back barrier structures beneath the 2DEG channel, such as the double-heterostructure and Mg-doped GaN buffer layer, have been proved to be very effective to enhance carrier confinement with much lower leakage current. However, all these methods would easily result in poor crystal quality, which led to degradation of the 2DEG channel layer grown subsequently. In addition, thick and heavy Mg-doped GaN would cause serious memory effect which may lead to the deterioration of out-put current densities of the fabricated HFETs.
In order to solve these problems, we report a novel structure of AlGaN/GaN HFETs with very thin Si and Mg pair-doped interlayer grown on Si substrate by MOCVD. This pair-doped interlayer, including a 14nm Si lightly doped GaN above a 14nm Mg lightly doped GaN layer, is inserted into the HR-GaN and located at the position 30nm below the AlGaN/GaN interface. The thin Mg-GaN grown here not only ensures the better 2DEG confinement with lower leakage current, but also weakens the memory effect of Mg atoms. While, Si-GaN interlayer is necessary for compensating the excess Mg due to memory effect and preventing the 2DEG from depleted. By optimizing the doping concentrations of Si and Mg pair-doped interlayers, the electron transport properties of 2DEG (mobility: ~8000 cm²/V.s@5K) was improved significantly with much enhanced electron mobility in comparison with that of conventional AlGaN/GaN heterostructure (mobility: ~4000 cm²/V.s @5K). The improved electron transport property is benefitted from the improved crystalline quality of conduction channel layer which was proved by higher luminescence intensity and better PL FWHM (not shown here), and flatness of AlGaN/GaN interface (RMS:~0.25nm). Furthermore, the insertion of pair-doped interlayer in AlGaN/GaN HFETs also greatly reduced the off-state drain current (as low as 10^-7 mA/mm) down to more than 4 orders of magnitude, which is attributed to the good channel crystal quality and improving of 2DEG confinement. The proposed HFET show great improvements in electrical characteristics with extremely high on/off ratio up to ~10⁹ and high I_Dmax up to 792 mA/mm.

Al2O3 has emerged as an viable gate dielectric for III-nitride-based electron devices. ALD [1] and MOCVD [2] are the primary growth techniques being used to deposit this dielectric film. A potential advantage of MOCVD is that Al2O3 can be grown in-situ therefore the deposition is free of ambient air contaminants and native oxide growth, and extensive chemical pretreatments which are normally employed before ALD. In this work we have done a growth comparison study of Al2O3/GaN system using atom probe tomography.
The 5 nm ALD Al2O3 was grown on a MOCVD GaN/Sapphire template using a H2O first process with H2O pretreatment at a temperature of 300 °C and a pressure of 200 mTorr [1]. The 5 nm MOCVD Al2O3 was grown in situ in the same reactor after GaN growth at a temperature of 900 °C and a pressure of 100 Torr [2]. These samples were then analyzed comparatively in Atom Probe . Mass spectrum analysis of dielectric layer from all the samples show the presence of impurities like C, N etc but no presence of GaxOy was found at the interface. Detailed composition analysis of MOCVD grown oxide shows a stable Al:O ratio throughout the layer and comparatively abrupt interface. On the other hand ALD oxide reveals a diffuse interface. Roughness measurement shows rougher interface for ALD than MOCVD sample. Qualitative estimation of carbon impurities within dielectric was done for both samples and was found to be in the order of 10^19/cm^3. C was suggested as a source of positive fixed near-interface charge and slow near-interface states [3]. Capacitance-voltage (C-V) measurement showed that the slow near-interface states for both ALD and MOCVD sample were on the order of 10^12 cm-2eV-1. However, the MOCVD sample exhibit much less hysteresis and an order of magnitude smaller fast near-interface trap state density (10^11 cm-2eV-1) compared with the ALD sample [1,2,4]. These feedback from atom probe analysis on dielectric/III-V system grown by different techniques is used for growth optimization towards better device fabrication.
1. X. Liu, R. Yeluri, J. Lu, and U.K. Mishra, J. Electron. Mater. 42, 33 (2013).
2. X. Liu et al., Appl. Phys. Lett. 103, 053509 (2013).
3. M. Choi et al., Appl. Phys. Lett. 102, 142902 (2013).
4. X. Liu et al., J. Appl. Phys. 114, 164507 (2013).

At present, there is little fundamental understanding of the role and nature of interface defects and fixed charge in the high-κ gate dielectrics on GaN. In this paper we will show that the interface defect density (D_it) in the Al₂O₃/GaN MOS device can be modified by post metal gate deposition annealing under controlled ambient and temperature conditions [1-3]. We report the role of hydrogen in the annealing of the Pd/ALD-Al₂O₃/GaN MOS device characteristics using Capacitance-Voltage (CV) and Deep Level Transient Spectroscopy (DLTS)/Deep Level Optical Spectroscopy measurements (DLOS), combined with Secondary Ion Mass Spectroscopy (SIMS) analysis. From the combined DLTS and DLOS techniques, a “U-shaped” interface state distribution across the GaN band gap is observed. Forming gas (H₂/N₂) annealing of atomic layer deposited Al₂O₃/GaN reduce the interface state densities to levels that are generally lower than prior literature reports for such structures [4]. The SIMS analysis showed the interface state density to correlate inversely with the hydrogen concentration level in the gate stack, suggesting that hydrogen is beneficial for passivating defects at the high-κ/III-V interface [3].
We will also present an analysis of employing the TiO₂/Al₂O₃ bilayer gate dielectric stack on the subsequent GaN-based MOS device characteristics. Our CV characteristics of GaN MOSCAP structures with TiO₂/Al₂O₃ bilayer gate dielectrics will demonstrate the potential to engineer the flat band voltage using the fixed charge and/or oxide-oxide charge dipoles present within these stacked metal oxide layers. We extend previous studies of such fixed charge and dipole engineering of InGaAs and Ge MOS gate stacks in [5-6] to investigate the possibility of engineering the threshold voltage using fixed charges and/or oxide-oxide charge dipoles of AlGaN/GaN MOSHEMT devices. Furthermore, the influence of the bilayer gate stack on the leakage current density and the total Equivalent Oxide Thickness (E_OT) of the MOSHEMT will also be presented.We will demonstrate that AlGaN/GaNMOSHEMTs with TiO₂/Al₂O₃ bilayer dielectrics show superior I_on/I_off ratio of over 10⁸, and smaller subthreshold slope (SS) <70 mV/dec compared to AlGaN/GaN MOSHEMTs with Al₂O₃ single layer dielectric. We hypothesize that higher Ioff and larger SS of single layer dielectric devices may result from parasitic leakage associated with fixed charge in the Al₂O₃ layer that is compensated when TiO₂ is present.The possible influence of this parasitic leakage will be tested and discussed.
[1] D.J. Meyer et al., Solid-State Electron.5, pp.1098-1104 (2010).
[2]O.I. Saadat etal., IEEE Electron. Dev. Lett. 30, No. 12, pp. 1254-1256 (2010).
[3] R.D. Long et al, Appl. Phys. Lett., accepted (2013).
[4] Y. C. Chang et al., Microelectron. Eng. 88, 1207 (2011).
[5] S. Swaminathan et al., Appl. Phys. Lett. 96, 082904 (2010).
[6] J. Ahn et al., Appl. Phys. Lett. 99, 232902 (2011).

The future evolution of GaN-based electronics relies largely on the development of proper dielectrics and associated deposition techniques to meet the increasingly stringent requirements for gate insulations and device passivations. We at UCSB have developed an in situ metalorganic chemical vapor deposition (MOCVD) approach to grow oxide dielectrics on GaN sequentially in the same reactor without breaking the vacuum [1]. Initial effort has been focused on the growth and interface characterizations of Al2O3 on GaN. Metal-oxide-semiconductor capacitor (MOSCAP) test structures were fabricated and measured using capacitance-voltage (CV) methods and additional stress and ultraviolet (UV)-assisted techniques [1-3]. The densities of near-interface fixed charge and trap states were extracted. The properties of the in situ MOSCAPs were compared with those of the atomic layer deposited (ALD) Al2O3 on GaN MOSCAPs [4].
References:
1. X. Liu et al., Appl. Phys. Lett. 103, 053509 (2013).
2. X. Liu et al., J. Appl. Phys. 114, 164507 (2013).
3. R. Yeluri et al., J. App. Phys. 114, 083718 (2013).
4. X. Liu et al., J. Electron. Mater. 42, 33 (2013).

Today, the physical limitations of nanoscale transistors operation, in particular the increasing of the power consumption per chip have led to the development of innovative MOS architectures. Nanodevices based NWs have been identified as a potential candidate for sub-10nm technology node because of their suitability for the gate all around architecture [1] which represent the ideal case for the electrostatic control of charge inversion and can ensure the further reduction of the “ultimate” transistor size. However, it is essential to implement these transistors on nanowire arrays in order to reach high current drive level. In that context, vertical integration [2] is a particularly attractive approach because its 3-D character is directly compatible with both top-down and bottom-up growth methods and the process results in extremely high integration densities. The vertical NW array based transistor is much easier to manufacture, because the gate length is simply defined by the thickness of the deposited gate material.
In this framework, several material issues should be tackled in order to ensure structure engineering at nanoscale. One prerequisite is the development of dense NW arrays with a perfect control of structure, location, direction, and doping, in CMOS-compatible technology. We will present the fabrication of dense Si NW arrays obtained using a top-down approach that couples e-beam lithography with plasma etching and sacrificial self-limited oxidation. Free standing NWs arrays with perfectly controlled diameters (16 nm) NWs, location and density have been obtained. The process, based on the stress retarded oxidation phenomenon, is developed as technological nanoscale tool, enables to control the nano-object shape, the size distribution and the interface properties. Moreover, the stress induced during the reaction, that we estimate based on numerical models, can be potentially used as a channel mobility booster.
Another challenge is the formation of low resistive S/D contacts in a vertical configuration. We developed metallic silicide contacts in order to get a better contact reliability and reduce the defect density at the metal/NW interface. We investigate the formation of platinum silicide/Si NW heterostructures by combining the chemical analysis of the formed phases with the electrical characterization of such realized nano-contacts. We will show that the silicidation process as well as the current injection mechanism in such 1D nanocontacts are not comparable with what is well known in planar bulk configuration.
Finally, layer engineering at nanoscale (insolating spacers, conductive thin films) will be presented in order to fabricate vertical NW gate all around device with gate length sub-15 nm.
[1] C. Cress et al. Science 341, 140 (2013);
[2] G. Larrieu et al. Nanoscale, 5, 2437 (2013).

One of the major challenges associated with the incorporation of high mobility III-V channel materials into future MOSFETs is the characterization, understanding and passivation of electrically active interface states present at the oxide/III-V interface. Considering the case of the high-k/InGaAs MOS system, there is a wide range of interface state concentrations D_it(E) reported for nominally similar structures [1]. One of the main issues associated with the accurate extraction of D_it(E) for the high-k/InGaAs MOS system is the question of how each gate voltage (V_g) is related to the corresponding surface Fermi level position (E_f) relative to the valence band edge (E_v). For a D_it(E) which changes density exponentially with E_f-E_v, this is clearly a potential source of error and variation between research groups. Moreover, the relationship of E_f-E_v to V_g is further complicated in the case of high D_it and for MOS systems where the semiconductor has a low conduction band density of states. It has recently been shown that good agreement can be obtained for the E_f-E_v at V_g = 0 V in the SiO₂/Si [2] and strongly pinned case of the Al₂O₃/GaAs MOS systems [3] using a combination of C-V analysis and hard x-ray photoelectron spectroscopy (HAXPES), where the high photon energies used in the synchrotron based HAXPES (2000-5000eV) allow the semiconductor core levels to be detected even in the presence of an overlaying thin metal gate and oxide layer [4].
In this work, we report on a combined HAXPES (4150 eV) and C-V study of the surface Fermi level position in the Al₂O₃/InGaAs MOS system. Samples with high (Ni) or low (Al) work function metals were employed in an attempt to move the surface Fermi level at V_g = 0 V. The experimental study included samples for C-V analysis with metal gates (~160 nm) and samples with thinner gates (~5 nm), or no gate, for the comparative HAXPES analysis (HAXPES analysis has no applied gate bias). InGaAs surface Fermi level positions determined by HAXPES revealed surface band bending occurring prior to metal deposition, which is attributed to a combination of fixed oxide charges and donor-type interface states. Following the metal deposition, HAXPES yields very similar surface Fermi level to the results obtained from high frequency C-V analysis at V_g = 0 V, providing more certainty on D_it(E) extractions and also bridging the gap between interface chemistry and electrical properties at a buried interface. The InGaAs surface Fermi level does move following metal deposition, but is found to be less than the expected metal-InGaAs work function difference, which is consistent with the partially pinned nature of high-k/InGaAs interface and suggests a peak interface state density near InGaAs midgap energy.
[1] R. Engel-Herbert et al., J. Appl. Phys. 108, 124101 (2010)
[2] L. A. Walsh et al., Appl. Phys. Lett.101, 241602 (2012)
[3] L. A. Walsh et al., Phys. Rev. B 88, 045322 (2013)
[4] K. Kakushima et al., J. Appl. Phys. 104, 104908 (2008)

We report the first successful application of corona charging noncontact C-V and I-V metrology to interface and dielectric characterization of III-V/oxide structures. The metrology, which has been commonly used in silicon IC manufacturing, uses incremental corona charge dosing, ΔQ_C, on the dielectric surface, and the measurement of surface voltage response, ΔV, using a Kelvin-probe. Its application to In_0.53Ga_0.47As with a high-k stack required modifications related to the effects of dielectric trap induced voltage transients. The developed Corona Charge-Kelvin Probe Metrology adopted strictly differential measurements using ΔQ_C and ΔV, and corresponding differential capacitance rather than measurements based on total global charge, Q, and voltage, V, values.
The results are obtained for a sample containing a In_0.53Ga_0.47As channel overlaid with a bilayer (2nm Al₂O₃/5nm HfO₂) dielectric stack. This stack is considered to be very promising for application in performance NFETs with high-mobility channels.
It is demonstrated that the Corona Charge-Kelvin Probe Metrology is able to address four issues that are critical for III-V MOSFET technology: 1-extraction of the density of interface traps, D_it, which is determined practically over the entire InGaAs energy gap in the test experiments; 2- extraction of the dielectric stack capacitance and the corresponding EOT, which was performed in deep accumulation; 3-investigation of the effect of charge traps (border traps) in dielectrics that is manifested as a corresponding voltage decay in time resolved measurements; 4- determination of the Al₂O₃/HfO₂ band offset from noncontact corona-dielectric I-V characteristics measured in the direct tunneling regime. This noncontact approach, which does not require fabrication of test structures, carries advantages of cost effectiveness and rapid data feedback.

There is currently a growing research interest in exploring alternative semiconductors to silicon in either MOSFET or Tunnel FET configurations for future energy efficient logic switches. In narrow energy gap (E_g) MOS systems such as In_0.53Ga_0.47As (E_g=0.75eV) and Ge (E_g=0.66eV), a considerable body of research has been focused on methods to characterise electrically active interface defects (D_it) and to reduce their concentration through surface preparation methods, interface control layers and post deposition thermal treatments. The experimental method most commonly reported to characterise and quantify D_it concentrations is based on the multi-frequency capacitance-voltage (C-V) and associated conductance-voltage (G-V) responses of MOS structures formed on Ge or narrow band gap III-V semiconductors. In the case of MOS systems based on narrow band gap semiconductors it can be difficult to provide a clear discrimination between high D_it values and genuine surface inversion. In addition, the evaluation of the oxide capacitance (C_ox) is complicated by the presence of interface states and/or border traps in the case of In_0.53Ga_0.47As MOS systems.
The paper describes experimental and simulation based studies of the characteristic behaviour of the capacitance and the conductance of the In_0.53Ga_0.47As MOS system in inversion. The reduction of D_it concentrations (< 1x10¹² cm^-2eV^-1 at mid-gap) to a level which allows genuine surface inversion behaviour in the In_0.53Ga_0.47As MOS system will initially be presented. For samples exhibiting genuine surface inversion it will be shown that the measured capacitance (C_m) and conductance (G_m) as a function of the ac signal angular frequency (omega;) are uniquely related, and that the peak value of G_m/omega; is equal to peak value of -dC/dlog_e(omega;) (equiv;-omega;dC/domega;), and that the peak magnitudes occur at the same angular frequency. The experimental observations are confirmed by first principles ac simulations of the InGaAs MOS system, showing that the equality holds for the case of strong inversion. Based on the equivalent circuit for the MOS system in strong inversion the equality is demonstrated mathematically, and shown to be generally true for any MOS system in strong inversion. From the mathematical analysis of the equivalent circuit in inversion, the peak values of Gm/omega; and -omega;dC/domega; are found to be uniquely related to C_ox and the semiconductor depletion capacitance in inversion (C_D). The relationships of the capacitance and conductance obtained can be used to discriminate between high interface state densities and genuine surface inversion for narrow band gap MOS structures. Moreover, it is demonstrated that the peak value of G_m/omega; and -omega;dC/domega; opens a new route to experimentally determine C_ox from multi-frequency capacitance or conductance measurements of an MOS structure in inversion.

Scaling electronic devices to (and beyond) the 10 nm gate-length will likely require intrinsically two-dimensional (2D) materials. This stems from the necessity of confining electrons within the thickness requires by conventional scaling laws, avoiding the intolerable gate leakage currents that result from the shift of the ground-state subband induced by quantum confinement. Pseudopotentials- empirical and ab initio - are now being more commonly used to study not only the atomic and electronic structure of these 2D materials (e.g., graphene, silicene, transition-metal dichalcogenides -TMDs), but also their electronic transport properties. Here we shall give a bird&’s-eye view of the use of density functional theory (DFT) to calibrate empirical pseudopotentials (EPs), of EPs to calculate efficiently the electronic structure of low-dimensionality systems, the most significant electronic scattering processes, and to study semiclassical electronic transport. Low-dimensionality systems considered here include thin semiconductor layers, graphene, graphene- and silicane-nanoribbons, silicon nanowires, TMDs and single-layer Sn (“stannanane”). Regarding graphene, the high electron mobility measured in suspended graphene sheets (~200,000 cm²/Vs) is the result of a relatively weak carrier-phonon coupling and the strong dielectric-screening property. However, in practical applications graphene is likely to be supported by an insulating substrate, top-gated, and possibly used in the form of narrow armchair-edge nanoribbons (AGNRs) in order to open a gap. We will discuss several scattering processes that may affect electron transport in these situations. First, we shall present results of the calculation of the intrinsic electron-phonon scattering rates in suspended graphene and AGNRs using empirical pseudopotentials and the rigid-ion approximation or DFT calculated deformation potentials, resulting in an electron mobility consistent with the experimental results. We shall then discuss the role of interfacial coupled substrate optical-phonon/graphene-plasmons (i.e., remote phonons) in depressing the electron mobility in graphene supported by SiO₂, HfO₂, Al₂O₃, and h-BN. We shall also review the strong effect of line edge roughness (LER) on electron transport and localization in narrow AGNRs resulting from the `claromatic&’ width dependence of the band-gap of the sp2-coordinated AGNRs. This will lead us to consider sp3-coordinate ribbons (silicane) and Si nanowires as possible alternative structures -- less affected by LER scattering -- of interest in nano-electronics application. Finally, we shall discuss the effect of high-κ gate dielectrics to boost the mobility of MoS₂ single layers and DFT calculations of the properties of halogen-terminated stannanane as a 2D topological insulator.
Work supported by NRI/SWAN2.0

Hydrogen is a ubiquitous impurity in many solids and particularly in oxides. As high K oxides replace SiO2 as the gate dielectric in future CMOS devices, hydrogen is introduced into high K oxide devices during ALD deposition and during the post-deposition anneal. Ionized hydrogen centers are therefore possible sources of positive fixed charge and bias instability. Interaction of H and materials has been extensively studied. Standard DFT approaches with local density functional have predicted the energetically active H induced defect levels and other related behaviours of H interstitial in many host materials. However, LDA is well known for underestimation of band gap and underestimation of Jahn-Teller or polaronic distortions of defect geometries. This failure can be traced back to poor description of exchange in LDA. In this work, we present HSE06 hybrid functional calculation of the geometry relaxation and charge transition levels of H interstitial in various test-case oxides. H has three charge states, -1, 0, +1. H0 in most cases form amphoteric interstitials except for rutile-GeO2, LaAlO3, TiO2 and SnO2 where H0 act as donors bonding to O. H+ bonds to anion and H- bonds to cation. This is different from the behaviour of H in tetrahedral semiconductors where H+ or H- bonds to the anion or cation and breaking a host cation-anion bond, leaving a cation or anion dangling bond, respectively. In ionic oxides, however, the oxygen site has four or less neighbours, but the cation site can have more neighbours. Often, H+ or H- can datively bond to the oxygen or metal site, without breaking a metal oxygen bond, it just sits at the side. We find H0 is never the lowest energy state. H acts exclusively as a donor for SnO2, thus SnO2 becomes n-type conductive. In other cases, +/- charge transition level lies in the upper part of the band gap except for La2O3 and CuAlO2 where +/- charge transition level lies in the lower part of the band gap. The charge transition levels are shown by aligning the band edges of oxides to their respective charge neutrality levels. It is quite interesting that +/- charge transition levels of SnO2, CuAlO2, HfO2 and La2O3 are very close when referred to the vacuum level, regardless of distinctive +/- charge transition levels relative to their respective band gaps: +/- for SnO2 lies above the conduction band, in the lower part of band gap for CuAlO2, in the upper part of band gap for HfO2 and in the midgap for La2O3. +/- charge transition levels also match among LaAlO3, theta Al2O3 and TiO2, and between quartz GeO2 and beta Ga2O3. There is not the close relationship to dangling bonds or charge neutrality levels as there was in the tetrahedral semiconductors. It is possible that this reference energy happens more generally, but not certain. We also align the band edges to the vacuum level. There is sign of constant +/-charge transition levels below vacuum energy, but not as significant as it is in tetrahedral semiconductors.

Miniaturization of metal-oxide-semiconductor field effect transistors (MOSFETs) is approaching its fundamental limits. New materials and innovative device structures are needed in order to continue the evolution of complementary metal-oxide-semiconductor (CMOS) technology. The use of high-k dielectrics in conjunction with semiconductors with better transport properties than silicon (Si) is an attractive alternative. Germanium (Ge) has bulk electron and hole mobilities that are 2.8 and 4.2 times those of Si, being a promising candidate. However, the formation of a stable passivating layer on Ge surfaces with a low density of electrically active defects is still a challenge. Beneficial effects of a post-deposition annealing (PDA) in forming gas (FG) were reported for MOS structures prepared with different dielectric materials deposited on Ge (see for example Oshima et al., Appl. Phys. Lett. 94 (2009) 183102). Such improvements were related to passivation of interfacial traps. This process seems to occur in a different way than in SiO₂/Si structures: both experimental (Afanas&’ev et al., Appl. Phys. Lett. 87 (2005) 32107) and theoretical works (Houssa et al. ECS Transact. 41 (2011) 39) state that defects in the dielectric/Ge interface region are resistant to H₂ passivation. In order to elucidate the role of H incorporation in the passivation of electrically active defects in dielectric/Ge structures, a deeper understanding of the modifications induced by H₂ annealings is needed. GeO₂/Ge structures are of special interest since GeO₂ can be unintentionally formed during deposition of high-k dielectric layers. In the present work, GeO₂ films underwent thermal annealing in deuterium (D₂) atmospheres at different temperatures. The use of D₂ enabled the determination of the amount of this isotope by nuclear reaction analyses. Moreover, we could distinguish the amount of H that is incorporated following annealing from that already present in the dielectric/semiconductor structure. GeO₂ films were deposited on both Ge and Si substrates in order to investigate the effect of the interfacial GeO₂ + Ge harr; 2GeO reaction. Oxygen vacancies generated by this reaction diffuse towards the GeO₂ surface promoting GeO desorption. Such vacancies are also produced during annealing in D₂ and may constitute incorporation sites for D. D incorporation in GeO₂/Ge structures as a function of the annealing temperature presented a maximum at 450 °C (16.9×10¹⁴ D/cm²). This behavior is in contrast to that observed for SiO₂/Si counterpart structures where a maximum is observed for higher temperatures (~500 °C). In the case of GeO₂/Ge, pronounced desorption of GeO₂ in the 500-600 °C range was observed, which influences the amount of incorporated D. Besides the interfacial reaction described above, D₂ annealing also promotes GeO₂ volatilization. These finding have strong implications in the stability of dielectric/Ge structures submitted to PDAs in FG.

Bipolar resistive switches were recently proposed as a new class of non-volatile switches capable of reading, writing and erasing memory information by switching non-linearly between low- and high-resistance values by application of mV voltage pulses in the ns range1. A basic characteristic of such a resistive switch is its hysteretic current-voltage profile depending on carrier flux, namely its "memristance". Several oxide-based materials such as SrTiO3, (La, Sr)(Co, Fe)O3, CaCu3Ti4O12, binary titania or hafnia, revealed memristance hysteretic current-voltage profiles at high local electric field strength in a metal-oxide-metal struc-ture 2,3,4. Despite their promises resistive switches are classically studied in their hysteretic current-voltage profiles or pulsed voltages to study current response over time and it is not resolved whether the electrode-oxide-electrode structure is in an equilibrium state during the different states of resistive switching. The diffusion kinetics and participating carriers relative to a selected oxide material require attention. In this work we propose chronoamperommetry measurements to diffusion kinetics of resistive switches to the field. For this, we focus on the model system Pt-SrTiO3-Pt and Pr-SrFeO3-Pt in which the band gap of the oxide can be changed by almost 1.5 eV through change in the transition metal ions d-band electrons and cationic size. Pulsed laser deposition of thin films with few nm to 400 nm allows for high local electric field strengths to observe hysteretic current-voltage profiles. In chronoamperommetry measurements the time constants (till stable currents establish with respect to a constant voltage) are measured. The applicability of the classic Cottrell equation is discussed and conductivity time constants reported relative to applied constant bias magnitudes for the examples of SrTiO3 vs. SrFeO3. Conclusively, the role of the oxides charge carrier transport requirements and diffusion kinetic characteristics are discussed for the model oxides Pt-Sr(Ti, Fe)O3-Pt for resistive switches based on new measurement approaches. In the final part of the paper, we present new structuring routes and materials to confine space charge potentials in resistive switching binary oxides5.
References
1) R. Waser et al. Adv. Materials, 2009. 21: 2632.
2) R. Waser and M. Aono. Nature Materials, 2007, 8:833.
3) J.L.M. Rupp et al. Appl. Phys. Letters, 2012, 100:012101.
4) A. Felix et al. J. Appl. Physics, 2012, 112:054512.
5) S.Schweiger, M. Kubicek, F. Messerschmitt, C. Murer, J.L.M. Rupp. J Materials Chemistry C, 2014, in review/invited

Metal-oxide-based resistive switching memory (RRAM) is one of the promising candidates for future non-volatile memory application due to its simple structure, low switching voltage (<3 V), fast switching speed (<10 ns), and great compatibility with the CMOS process technology. Recently, a 32-Gb test chip has been demonstrated as well. Yet, the development of a practical RRAM technology requires a deep understanding of a broad set of issues such as the physics of resistive switching in oxides, an exploration of the scaling limits, and a practical scheme for 3D integration for future mass storage. This talk gives an overview of efforts to address these issues through experiments and modeling.
The physical mechanism of resistive switching is generally attributed to the conductive filament (made up of oxygen vacancies) formation and rupture in the oxide due to field assisted oxygen ion migration. A Kinetic Monte Carlo (KMC) model system for device physics study is developed based on various electrical characterization efforts such as I-V measurements at various temperatures, low-frequency noise measurements, and AC conductance measurements. The model elucidates the oxygen ion migration dynamics and electron transport across the oxide, as well as captures many experimental observations successfully. Furthermore, a RRAM compact model is developed in MATLAB, HSPICE, and Verilog-A, to enable the study of circuit and system interactions.
The scaling limits of RRAM device has been investigated through three approaches. First, first metal oxide RRAM device using diblock copolymer self-assembly lithography patterning is experimentally demonstrated, which successfully scales down the active area to less than 12 nm. Second, the e-beam lithography technique enables an ultra-scaled cell with the active area down to few nanometers (< 10 nm) in diameter. Third, a RRAM cell using carbon nanotubes (CNT) as contact electrodes is experimentally demonstrated. CNTs which average diameter is 1.2nm effectively localizes the conduction filaments and allows the study for ultra-scaled RRAM cells. The key features of each approach will be presented.
To develop a storage solution beyond NAND FLASH, a novel 3D vertical RRAM cross-point array architecture and a cost-effective fabrication process is proposed. This 3D RRAM concept is experimentally demonstrated using a double-layer stacked RRAM structure. The devices show excellent and consistent switching characteristics for all the layers, suggesting the potential of stacking even more layers. A comprehensive understanding in vertical-RRAM research, ranging from memory architecture design, corresponding read/write schemes, device fabrication and characterization, interface engineering, array demonstrations, and scaling limit investigations will be reported.

Conductive-Bridge RAM memory constitutes an interesting perspective for a post-Flash non volatile scenario, thanks to its low power [1-2], high speed [3] and large on/off ratio [4]. Its mechanism is based on the migration of metallic ions from a top electrode of Ag or Cu into a chalcogenide insulating layer as, e. g., GeS2 [5] or GeSe [6], creating a conductive filament (CF) that shunts both electrodes. Despite their importance, the physics at the basis of these memories are still not completely understood. In particular, mechanical stresses acting on the CF are still not well analyzed.
Experimentally, it is observed that reset transition is triggered by a reset voltage which is inferior to the voltage obtained after set transition. The same refers for reset current, which is reduced with respect to compliance current. The origin of this asymmetry could reside in the mechanical forces that act on the filament. In fact, migration of ions during set transition from the top electrode into the chalcogenide generates a compressive stress in proximity of the bottom electrode, while a tensile stress arises near the top electrode because of the reduced ion density due to migration. This gradient of mechanical stress facilitates the subsequent CF dissolution in the reset transition, hence a minor voltage is needed. This effect is demonstrated through a finite-element 3D model of nanoionic drift-diffusion [7].
An analytical model has also been developed, based on a previous one [8], in which set and reset transitions are modelled as Arrhenius processes with a certain activation energy. This parameter increases during set due to the mechanical stress gradient that prevents from further ion migration. During reset, the energy barrier decreases due to the stress gradient that drives ions back to the top electrode. This model also allows for the study of the switching kinetics. Actually, stress can be relaxed in the surrounding oxide layer through a plastic relaxation accelerated by Joule heating. For increasing set times, longer heating time is provided to the filament, relaxing stress. As a consequence, experimental evidences show that reset voltage increases, because no stress aids in dissolving the CF. Retention data also show that longer set times correspond to higher time failures. The analytical model, through an energy barrier set time dependence [9] can capture all these features, providing a new vision of the set/reset asymmetry.
[1] R. Waser, et. al., Nat. Mater., 6, 833 (2007).
[2] C. Schindler, et al., Appl. Phys. Lett., 92, 122910 (2008).
[3] K. Aratani, et al., IEDM Tech. Dig., 783 (2007).
[4] K. Prall, et al., Proc. IEEE IMW, 1 (2012).
[5] C. Gopalan, et al., Solid- State Electronics 58, 54 (2011)
[6] M. Kozicki, et al., IEEE Trans. Nanotech., 4, 331 (2005).
[7] S. Larentis, et al., IEEE Trans. Electron Devices 59, 2468 (2012).
[8] D. Ielmini, IEEE Trans. Electron Devices 58, 4309 (2011).
[9] P. Lucas, et al., J. Am. Ceram. Soc. 92 (1986).

Previously, it was reported that the metal oxide high-k gate dielectric film can have many improved bulk and interface electrical properties by doping with a third element [1]. For example, the Zr-doped HfO2 film (ZrHfO) has a higher crystallization temperature, a lower interface state density, and a larger effective k value than the un-doped HfO2 film has [1,2]. Moreover, ZrHfO has been successfully used in the nonvolatile memories as the tunnel and control layers to prevent the large leakage current problem [3]. AlOx can be embedded in the ZrHfO film used as the charge trapping layer because of its high charge trap characteristics at the low O content condition [4]. In this study, the MOS capacitor composed of the (tunnel ZrHfO/embedded AlOx/control ZrHfO) tri-layer was fabricated on a p-type Si wafer using the one pump down sputter deposition process followed by a post deposition annealing step at 800oC in the N2 atmosphere. The nonvolatile memory characteristics were demonstrated by the capacitance-voltage (C-V) and current density-voltage (J-V) curves. When the gate voltage (Vg) was swept from -6 V to +6 V to -6 V, a large flat band voltage (VFB) shift of 0.323 V was obtained while a very small VFB shift of 0.011 V was obtained in the control sample, i.e., containing the ZrHfO gate dielectric film without the embedded AlOx layer. Compared with the fresh C-V curve swept from Vg -2 V to +1 V, the forward and backward curves of AlOx embedded sample both shifted to the negative Vg direction, which showed that holes were strongly trapped in the embedded AlOx site. The G-V curve were dependent on the measurement frequency, which indicated the partial trapping of the charges to the AlOx/ZrHfO interface. Both J-V curves of the control and embedded samples showed small peaks close to the flat band voltage due to the quick release of trapped holes. More than 30% of the trapped holes could be retained in the AlOx sample after 10 years. In summary, the AlOx embedded ZrHfO dielectric stack has a large hole-trapping capability with a long retention time, which is suitable for the nonvolatile memory application.
1. Y. Kuo, J. Lu, S. Chatterjee, J. Yan, H. C. Kim, T. Yuan, W. Luo, J. Peterson, and M. Gardner, ECS Trans., 1(5), 447 (2006).
2. J. Yan, Y. Kuo, and J. Lu, Electrochem. Solid-State Lett., 10, H199 (2007).
3. C.-C. Lin and Y. Kuo, ECS J. Solid State Sci. Technol., 2 (1), Q16-Q22 (2013).
4. S. Nakataa, K. Saitob, and M. Shimada, Appl. Phys. Lett., 87, 223110 (2005).

The integration of the selection device is the most promising approach to prevent misreading problem in 3D-stacked ReRAM device caused by its snake-path current. Recently, transition metal oxides with metal-insulator transition (MIT) have attracted interest due to abrupt change in their conductance at threshold voltage for the application of selection devices. For this reason, selection devices have been tested for 1S1R-structured 3D ReRAM using MIT materials, such as VO₂ and NbO₂. Despite its high ON/OFF ratio and low threshold voltage, VO₂ shows metallic property at operating temperature of memory device (~400 K) because of its low transition temperature (~340 K), which makes it impossible to use VO₂ for the practical application of selection devices. NbO₂ is more suitable to be used due to high-temperature stability of its insulating phase. However, NbO₂-based selection devices are operated at over 2 V that is higher than required ON voltage for selection devices.
Here we investigate an approach to tune threshold voltage of NbO₂ thin film. We prepared NbO₂ thin film using ultra high vacuum radio-frequency (UHV RF) sputtering with Nb₂O₅ oxide target. To obtain stable NbO₂ films from Nb₂O₅ target, NbO₂ films are grown on Pt(50nm)/TiO₂(20 nm)/SiO₂(300 nm)/Si substrates in reducing condition with H₂/N₂ forming gas at 500 °C. We fabricated the metal-insulator-metal (M-I-M) devices with Pt top electrodes on 30 nm-thick NbO₂ thin films and measured I-V characteristics using semiconductor parameter analyzer (Agilent B1500). We observe large ON/OFF ratio of over 100 and the shift of the threshold voltage as a function of film thickness. Moreover, we succeed in doping with tungsten (W) for n-doping and nitrogen (N) for p-doping in NbO₂ thin film to improve threshold voltage and ON/OFF ratio. These results can be interpreted as a band filling control of the NbO₂ thin film with doping, giving rise to the tuning of the Mott-Hubbard gap. Finally, we will present 1S1R device characteristics using our selection devices integrated in 3D ReRAM.

Detailed description of defect dynamics is central to the understanding of memristive switching phenomena. In a recent paper [1] we reported first-principles atomic-scale calculations on the basis of which we proposed memristive switching in polycrystalline ZnO is caused by Filed-induced migration of oxygen vacancies in and out of grain boundaries.In this talk we will describe multiscale modeling of this phenomenon to get quantitative information.
The accumulation of oxygen vacancies at the grain boundaries in ZnO during the switching process leads to the formation of conducting path. We use a first-principles-based theoretical approach to obtain both spatially- and time-resolved defect profiles under different defect concentrations, initial defect distributions, temperature, and external electrical field. Similar approach was used in Ref. [2] to study ion-induced dielectric breakdown in nanoscale SiO2.
Parameters of the simulation are obtained from density functional theory (DFT) static calculations and nudged elastic band calculations. The effect of an electric field is taken into account by modifying the diffusion/dissociation barriers according to the defect charge states and directions of defect motions [3]. The kinetic Monte-Carlo (KMC) uses the parameters obtained from first-principles DFT calculations to produce the time-dependent snapshots of the defect configurations. From the snapshots of defect maps obtained in KMC simulations, percolation model is employed to calculate the time-dependent current-voltage (I-V) characteristics of ZnO.
In addition to the percolation model, a full quantum mechanical method of calculating charge transport is applied for particular defect configurations in ZnO. We perform full quantum calculations in small systems containing a few defects to explore the individual tunneling process between defect and electrode and between defects. The result is used to optimize the parameters used in the percolation model. Finally, we will combine these two methods and establish an integrated routine that provides quantitative description of physics-based mechanisms in resistive switching.
References
1. X. Shen, Y. S. Puzyrev, and S. T. Pantelides, “Vacancy breathing by grainc boundaries - a mechanism of memristive switching in polycrystalline oxides” MRS Commun., 3, 167 (2013)
2. M. J. Beck, Y. S. Puzyrev, N. Sergueev, K. Varga, R. D. Schrimpf, D. M. Fleetwood and S. T Pantelides, "The role of atomic displacements in ion-induced dielectric breakdown", IEEE Trans. Nucl. Sci. 56, 3210-3217 (2009).
3. K. H. Warnick, Y. S. Puzyrev, T. Roy, R. D. Schrimpf, D. M. Fleetwood, and S. T. Pantelides “Room temperature diffusive phenomena in semiconductors”, Phys. Rev. B., 84, 214109 (2011)
Acknowledgement
This work was supported by National Science Foundation grant DMR-1207241 and the McMinn Endowment at Vanderbilt University. Computational support was provided by the NSF XSEDE under Grant #DMR TG-DMR130121.

For practical use of Resistive Random Access Memory (ReRAM), it is important to ensure reliability. Typical stress parameters for the estimation of reliability include a voltage [1], heat [2], and humidity. However, knowledge on the influence of humidity on reliability and memory characteristics is lacking.
In this paper, we investigated the influence of water on memory characteristics, such as operation voltages and data retention, for Pt/NiO/Pt structures. As a result, the decrease in voltages to form a filamentary conduction path, called a filament, (V_form) was confirmed. In addition, the degradation of data retention for low resistance values was confirmed by dropping water.
NiO films with the thickness of 60 nm were deposited on Pt/Ti/SiO₂ substrates at 380 °C using the RF reactive sputtering method, followed by the deposition of a Pt top electrodes (TEs) with the thickness of 100 nm. We measured current-voltage (I-V) characteristics for the Pt/NiO/Pt/Ti/SiO₂ (Pt/NiO/Pt) structures before and after providing ultrapure water (H₂O). The provided H₂O covers the whole of the area of the Pt-TE.
The decrease in the resistance in initial state (R_ini) and V_form by providing H₂O was confirmed, suggesting that H₂O enhances the forming. Then, Pt/NiO/Pt devices that was fabricated on the same wafer was heated in vacuum (6.0×10^-4 Pa) at 200 °C for 10 min, in order to induce desorption of H₂O that was absorbed in the devices. Consequently, the drastic increase in both R_ini and V_form (about three times larger than in air) was confirmed. The large V_form damages the filament at the moment of filament formation [3], and makes the filament too leaky to be reset. These results suggest that H₂O makes the formation of filaments easy by reducing R_ini. Therefore, resistive switching effect developed with very high probability in devices for which the forming operation was performed under the presence of H₂O.
We also investigated the effect of the desorption of H₂O after the completion of forming on the I-V characteristics. We provided H₂O to Pt/NiO/Pt devices and forming operations were performed to set the devices to low resistance state. After the forming, the devices were heated in vacuum. These devices show resistive switching effect, and voltages for both set and reset switching are almost equivalent to those observed under the presence of H₂O. This result seems to suggest that H₂O is not necessary for set and reset switching. However, we clarified that H₂O strongly induces reset switching, resulting in high failure probability of a data retention test for low resistance state. 89 % of the devices which absorbed H₂O was reset to high resistance state without applying a voltage.
This study suggested that H₂O is closely related to resistive switching effect of ReRAM, and enhances both forming and reset switching.
[1] C. H. Ho et al., VLSI Tech. Dig. 229 (2007).
[2] I. G. Baek et al., IEDM Tech. Dig. 587 (2004).
[3] B. J. Choi et al., JAP 98, 033715 (2005).

Resistive random access memory (ReRAM) has been studied intensively as a promising candidate for post-flash memory. Among various types of resistive switching devices, a TiN/Pr_0.7Ca_0.3MnO₃ (PCMO)-based device utilizes the resistance change as the two materials goes through reversible interfacial reactions. It has been suggested that the reactions are driven by the electrochemical migration of oxygen vacancies, leading to multi-level switching between the low resistive state (LRS) and the high resistive state (HRS). Previous microstructural characterization studies have reported only final snapshot images of the HRS and the LRS after switching, which do not allow a direct correlation between structural transition and the electrical properties during the switching processes. We present direct observations of the switching processes of TiN/PCMO/Pt-based ReRAM devices using in situ transmission electron microscopy (TEM). The capacitor-like cell structure was fabricated by conventional deposition, patterning, and etching processes. Cross-sectional TEM specimens for in situ TEM experiment were prepared using focused ion beam (FIB). In situ TEM experiments were performed by using a field emission TEM (JEOL JEM-2100F) operated at 200kV and a single-tilt STM-TEM holder (Nanofactory^TM). For elemental analysis, electron energy loss spectroscopy (EELS) was carried out by using an aberration-corrected scanning TEM (STEM). To observe the switching process from LRS to HRS (RESET process), we used a device initially switched to the LRS. For the RESET process a cyclic ramping of DC bias from 0 to 4 V and back to 0 V was repeated for four times in sequence. The DC current was measured simultaneously while observing the microstructure of TiN/PCMO interface in real-time (25 fps). During the 1st positive voltage sweep, the formation of an amorphous layer (~3 nm in thickness) was detected near the TiN/PCMO interface, and the I-V curve clearly represented the expected I-V characteristics of RESET process. As the voltage sweeps continued, the I-V characteristics remained essentially the same but the contrast of the amorphous layer became more pronounced. Interestingly, the amorphous layer was formed within the TiN layer a few nm away from the interface. For the reverse switching to the LRS (SET process), DC negative bias was applied from 0 to minus;4 V and back to 0 V at the same ramping rate as the positive sweep. While the SET process was completed in the first voltage sweep, the contrast of amorphous layer decreased gradually during the subsequent sweeps. To characterize the nature of amorphous layer, we performed the EELS line scan across the TiN/PCMO interface. The Ti-L₃, L₂ and also O-K edges were detected and the relative ratio of Ti and O was approximately 1:1, indicating the prevalence of Ti-oxide. Based on the direct observations of the microstructural evolution and correlated I-V characteristics, a resistive switching model for TiN/PCMO devices will be presented.

Due to their less vulnerability to charge losses through isolated defects in the bottom tunnel oxide, non-volatile memory (NVM) devices with charge storage in discrete nanocrystals (NCs) offer the chance for better scalability and to operate at lower voltages compared to continuous floating gate (FG) flash devices. Compared to Si NCs, the smaller bandgap of Ge NCs is expected to further improve the memory performance, which offers the opportunity for an additional reduction of the operating voltage, faster program/erase speed, better endurance and longer data retention. Moreover, the operating voltage can be supplementary tuned by using high-k materials as blocking oxide instead of SiO2.
In this work, Ge NCs embedded in a high-k control oxide have been fabricated by radio frequency magnetron sputtering of Ge-TaZrO2/TaZrO2 layers on a p-type Si-Wafer covered by a 5 nm thermal oxide. The elemental composition was determined by Rutherford Backscattering (RBS) and X-ray Photoelectron Spectroscopy (XPS). The formation of spherically shaped Ge NCs in an amorphous TaZrO2 matrix occurs during a high temperature annealing process via phase separation of the co-sputtered Ge-TaZrO2 layer and is demonstrated by cross-sectional transmission electron microscopy (TEM). To achieve a Metal-Insulator-Semiconductor (MIS) structure for the electrical measurements, electron beam evaporation was used to deposit Ti/Al contacts. Capacitance-voltage (C-V) measurements exhibit a counter clockwise hysteresis indicating the tunneling of holes through the SiO2 and their subsequent trapping in the Ge NCs. In contrast, reference samples without Ge do not show a significant hysteresis. The window of the flatband-voltage shift (memory window) widens with both, sweep voltage range and programming time. If the sweep voltage is kept constant, the investigation of the memory window versus the programming time shows a saturation, which indicates that the number of stored holes per NC is finite for a given programming voltage. An investigation of the memory window as a function of the annealing temperature indicates that the smoothest C-V curves with the biggest memory window can be achieved after annealing at 725 °C. Lower temperatures lead to distorted C-V curves with weak reproducibility. Anneals at temperatures above 750 °C decrease the memory window, which is attributed to the crystallization of the TaZrO2 matrix. Thus, the leakage current to the gate electrode increases and the NCs become discharged. Furthermore, the discharging kinetics is examined by the constant bias method. In summary, it could be shown that MIS structures comprising Ge NCs in amorphous high-k TaZrO2 show promising NVM characteristics.

The properties of atomic layer deposited holmium doped titanium oxide (TiO2:Ho2O3) and holmium titanate (HoTiOx) as high-k dielectrics for Metal-Insulator-Metal (MIM) capacitors have been investigated. The permittivity value of holmium oxide is only about 10. However its high band gap (about 5.3 eV) makes this oxide an interesting material when mixing with titanium oxide, as the latter is known to be a leaky oxide due to its low band gap. On the other hand, it has been widely reported that titanium oxide based MIM capacitors exhibit resistive switching behavior and can be used as resistive random access memory (RRAM) cells. In this work we proved for the first time that both TiO2:Ho2O3 and HoTiOx MIM capacitors also exhibit bipolar resistive switching behavior.
Thin high-k films were deposited by atomic layer deposition (ALD) on TiN electrodes using TTIP as titanium precursor and Ho(thd)3 as holmium precursor. Ozone was the oxygen precursor. Ho:Ti ratio was modified by different pulsing ratios for different samples and verified by EDX measurements. Films thicknesses varied from about 8 to about 27 nm (measured by XRR).In order to study the annealing effects on the electrical properties of the oxide films, some of the samples were annealed in an N2 atmosphere.
The best result obtained was equivalent oxide thickness (EOT) of about 1.8 nm with a leakage current in the order of 10^(-6) A/cm2. EOT was lower in the case of annealed samples, probably due to a change in the degree of crystallinity. However, the leakage current also increases if samples were annealed. 600+800 degrees seems to be the best annealing temperature. Capacitance-Voltage linearity is good for samples with low leakage currents. However, C-V linearity worsens when leakage increases.
The main conclusion of our work is that TiO2:Ho2O3 and HoTiOx MIM capacitors are good candidates for DRAM and RRAM memories with superior performances.

Resistive switching phenomena in metal oxides have been intensively studied in recent years, because of the potential for nonvolatile memory application, i.e. resistance random access memory (ReRAM). The main mechanism of the resistive switching phenomena is a nanoionic redox reaction triggered by Joule heating or electrochemical migration of oxygen vacancies. Since chemical alterations of materials are inevitably induced in both mechanisms, there is concern for the reliability, such as the data retention and endurance. As a solution of this problem, resistive switching phenomena induced by reversal of ferroelectric polarization in ferroelectric capacitors have attracted a considerable attention, because polarization reversal does not induce a chemical alteration.
Recently, we have demonstrated the ferroelectric resistive switching in a Pt/BiFeO₃/SrRuO₃/ (Pt/BFO/SRO) device, and the device showed promising characteristics for nonvolatile memory applications, including data retention of > 10⁵ s and endurance of 10⁵ cycles. Based on the transport and resistive-switching properties, we proposed that an unintentionally-formed dielectric dead layer at the Pt/BFO interface plays a crucial role in the emergence of the ferroelectric resistive switching. In order to elucidate the role of the interfacial dielectric layer in the emergence of ferroelectric resistive switching, we fabricated interface-engineered ferroelectric capacitors in which a thin LaFeO3 (LFO) dielectric layer was inserted at one of the interfaces of SRO/BFO/SRO capacitors and investigated their resistive switching characteristics. The SRO/BFO/SRO device which has no interfacial LFO layer showed nearly ohmic currentminus;voltage (Iminus;V) characteristics without hysteresis. On the other hand, the SRO/LFO/BFO/SRO devices showed hysteretic Iminus;V characteristics, indicating the emergence of the resistive switching. In addition, the rectification was observed in the Iminus;V characteristics of the SRO/LFO/BFO/SRO devices, suggesting the insertion of the thin LFO dielectric layer induces an asymmetric potential distribution along the stacking direction in the device. Based on these experimental results, we propose a possible mechanism of the ferroelectric resistive switching observed in our devices. In SRO/LFO/BFO/SRO devices, the polarization charge in the BFO layer and the screening charge in the SRO electrode are separated by the inserted LFO dielectric layer. As a result, a finite potential distribution is formed in the LFO layer, and thus the device has an asymmetric potential distribution. The polarization reversal in the BFO layer changes the potential distribution, leading to the resistive switching in the device.

Although a large amount of interface states density (Dit) at dielectric/Ge interface has been reported, the success of extensive research efforts for GeO2/Ge interface passivation encourages us to realize high-mobility Ge complementary metal oxide semiconductor (CMOS) beyond Si CMOS. However, there are still two great concerns in the GeO2/Ge stack, namely, thermal instability and water solubility, which inevitably incur difficulty in Ge-based device process as well as the reliability issue.
In the present work, we demonstrate a significant improvement of both thermal stability and water resistance in GeO2/Ge stack by replacing GeO2 with yttrium-doped GeO2 (Y-GeO2). The excellent electrical properties of Y-GeO2/Ge stack with low Dit (~1011eV-1cm-2) are presented as well as enhancement of dielectric constant in Y-GeO2 layer, which is beneficial for further equivalent oxide thickness (EOT) scaling of Ge gate stack. On the basis of this understanding of Y-GeO2, we have achieved 0.47 nm-thick EOT in HfO2/Y-GeO2/Ge gate stack with 3 A/cm2 of gate leakage current at VG=-1V. The superior interface properties of this gate stack are maintained without any degradation up to 550oC thanks to the thermally robust Y-GeO2 interfacial layer. The influence of Y doping on the material properties of GeO2 is discussed from a thermodynamic viewpoint that Y can lower the oxygen potential of GeO2. In addition, a systematic comparison is also carried out between different M2O3 (Sc2O3, Y2O3 and La2O3) as doping materials into GeO2 and their similarity and difference are discussed.

Cylindrical brush polymers were developed as a novel approach for negative-tone molecular-scale photoresist polymer materials. The polymer architecture consists of a rigid backbone of polymerized norbornene, each linked to flexible short side brush chains. The resultant ‘bottle brush&’ topology has a cylindrical shape with short brush chains arranged concentrically around the backbone, in which the cylinder radius is determined by the number of monomers within the brush fragment, while the cylinder length is determined by the degree of backbone polymerization. The brush polymers composed of chemical components for substrate alignment and cross-linking chemistry with the high degree of control in their compositional placement and concentric and lengthwise dimensions over the synthetic chemistry provide facile access to cylindrical nanoscopic object without the supramolecular assembly processes as is typically required in block copolymer lithography with linear block copolymers. The modularity of the synthetic system allows a wide diversity of lithographically-useful monomers, sequencing, dimension, and property variation. The photoresist materials with the cylindrical brush polymers aligned perpendicular to the wafer surfaces and yielded electron-beam-generated patterns with widths of a few macromolecules with the minimum pixel size determined by the cylinder diameter.
In this presentation, the relationship between the composition of brush polymers and film morphology for negative tone lithography will be discussed. Three different fluorinated polymers have been used for surface energy reducing moiety and the morphologies of the corresponding block brush polymer films have been investigated in the point of vertical alignment.
In addition to negative-tone materials, design of bottle brush polymers for positive-tone lithography will be discussed. Several challenges in this pursuit including achieving vertical orientation, substrate adhesion, and sufficient structural integrity to survive development and rinse processes have been encountered. Synthetic routes to addressing these issues will be described, along with recent encouraging results.

3D cross-point Resistive Random Access Memory (ReRAM) for integration is making rapid progress to replace NAND Flash memory. 1bit is constructed by placing a ReRAM memory cell at the cross-point of bit line and word line. Stacks of layers with the countlessly arranged ReRAM memory cells achieve large capacity. The cross-point ReRAM has a technical issue that memory operation becomes a read disturb due to a sneak current [1]. To solve this issue, a selector with bidirectional diode characteristics needs to be developed for bipolar ReRAM. We are presently working to develop the selector using NbO_x [2] known for metal-insulator transition (MIT) material. The NbO_x layer is prepared by O2 reactive sputtering using Nb metal target. By adjusting the sputtering conditions such as the oxygen flow rate, Pt/NbO_x/Pt-cell can be obtained a threshold switching that is driven at ±0.5V. Furthermore vertically stacked one selector diode-one resister (1D1R) Pt/NbO_x/TaO_x/Pt-cell is realized. This cell obtains bipolar switching characteristics in which threshold voltage at ±0.7V, reset voltage at 1.2V and set voltage at -0.8V.
References
[1] E. Linn et al, Nat. Mater. 9, pp. 403-406, 2010
[2] H. Hwang et al, VLSI Symp. Tech. Dig, pp. 155-156, 2012

Recent simulation of the carbon nanotube enabled vertical field effect transistor (CN-VFET) has confirmed that two mechanisms contribute to the high performance characteristics of these Schottky barrier devices: gate induced modulation of 1) the barrier height and 2) the barrier width [1]. Both of these contribute to a high thermionic field emission from the nanotubes into the semiconductor in the on-state and a high and wide barrier leading to low injection in the off-state. Previous work from our group has concentrated on the use of organic semiconductor channel materials however our first devices were actually built on inorganic single crystal silicon (exploiting an electrolytic gate) but exhibited only 2 orders of magnitude current modulation [2]. Here we return to the use of inorganic silicon and exploit the availability of a high quality, high k, atomic layer deposited dielectric to demonstrate inorganic silicon based CN-VFETs with over 5 orders of magnitude current modulation.
[1] Modeling and Simulation of Carbon Nanotube-Semiconductor Heterojunction Vertical Field Effect Transistors, W. Chen, A.G. Rinzler, J. Guo, Journal of Applied Physics 113, 234501 (2013).
[2] Tunable Contact Barrier of Single Wall Carbon Nanotube Films For Electrical Contact to Semiconductors and Polymers, Z. Wu, PhD Thesis, University of Florida (2008).

Increasing information storage density is a principal objective of materials scientists, device physicists and semiconductor manufacturers throughout the world, driven primarily by substantial economic incentives. Historically, an effective means of achieving this goal has been to reduce the spatial dimensions of the information storage devices themselves, which have often been transistors. Recently, this approach has become increasingly difficult and costly, leading researchers and commercial manufacturers alike to turn to multi-level cell approaches where information can be stored as a state within a range of possible values as opposed to a digital ON or OFF. Where digital devices can be seen as 0-dimensional in information space, multi-level cell devices can be viewed as one-dimensional. Resistive switches are an excellent example of one-dimensional memories where the resistance can be set to any of a range of possible resistance values as opposed to simply a high or low resistance. We explain physically and demonstrate experimentally that this one-dimensional approach drastically under-utilizes the information storage capacity of these devices.
Using standard, CMOS compatible, tantalum oxide resistive memories we show that it is possible to configure the state such that the power required to change the resistance can be set and read independently from the resistance itself. Physically, these degenerate powers correspond to varied geometry and conductivity combinations of the same resistance value. For example, a single resistance could correspond to a large radius with a small conductivity or a small radius with a large conductivity. Despite having the same resistance, these two (or any of the possible) configurations require different electrical power to induce resistive switching. Using simple power-limited circuitry, we are able to set the geometry and conductivity of the filament separately and thereby separately set the resistance and the electrical power required to change the resistance. We show that this can be done over a wide dynamic range, and that our simple power-limited circuitry increases state-setting precision such that hundreds of states per device are easily accessible and tens of thousands or more may be possible in this two-dimensional information space. We also experimentally demonstrate a third dimension of information space in resistive memories and suggest approaches for achieving many more. By expanding into multi-dimensional information space, we demonstrate a complementary or alternative approach to the conventional and incredibly difficult scaling approach for increasing information density.

Implementing a unique two-step simple molecular beam epitaxy (MBE) growth technique in our laboratory, we have successfully demonstrated heteroepitaxial growth of high-quality Ge on Si (GoS) that opens up a possibility for many applications, including high-mobility transistors integrated on Si substrates and high-speed, read-only memory using Ge as the channel material. We note that our Ge film covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. Herein, we have investigated the characteristics of three such devices: p-MESFETs as well as p- and n-MOSFETs fabricated on GoS substrates. For p-MESFETs, we have measured the low-field peak effective hole mobility of 310 cm²/V-s under 0.1 MV/cm at 300K and a cut-off frequency of 10 GHz at 200K. In this presentation, we will provide additional details of the device characterization. In addition to MESFETs, we have investigated electrical characteristics of 2.5-µm p- and n-MOSFETs fabricated on GoS substrates. The defect density in n- and p-type GoS obtained from etch pit density measurements is below 1x10⁶ and 2x10⁷ cm^-2, respectively. MOS capacitors are first fabricated, using Ti/HfO₂/GeO_xN_y/GoS gate-stack structure. Angle-resolved X-ray photoelectron spectroscopy is employed to quantify the nitrogen content within the GeO_xN_y layer, where the largest N(1s)/O(1s) atomic percentage ratio is obtained from nitridation at 375^omicron;C. Spectroscopic ellipsometry is also used to measure the complex dielectric constant of the dielectric layer: ε(E)=ε₁(E)+iε₂(E). The corresponding gate leakage current density is below 10^-3 A/cm² for p-MOS and 7x10^-3 A/cm² for n-MOS, and D_it is 6x10¹¹ cm^-2eV^-1 at 300K on both MOSCAPs. For MOSFETs, a two-step thermally activated method, instead of ion-implantation, is used to define source and drain. Forward and transfer current-voltage characteristics are measured, and the p-MOSFETs built on GoS substrates show a subthreshold slope (SS) of ~100 mV/decade, compared to ~80 mV/decade for the identical p-MOSFETs built on Ge substrates. In comparison, the n-MOSFETs built on GoS substrates show a SS of ~200 mV/decade. The peak effective hole mobility (µ_h) obtained from our optimized p-MOSFETs is 401 cm²/V-s under 0.1 MV/cm. This is an 82% increase in the µ_h in the inversion channel in GoS, compared to the universal µ_h in Si. The peak effective electron mobility (µ_e) obtained from our optimized n-MOSFETs is 940 cm²/V-s under 0.1 MV/cm. This is a 34% increase in the µ_e in the inversion channel in GoS, compared to the universal µ_e in Si. In summary, a wafer-scale, epitaxial Ge layer on Si is used to fabricate high-hole-mobility p-MESFETs and p- and n-MOSFETs. In this talk, we will further discuss the performance of CMOS logic circuits by combining the p- and n-MOSFETs on GoS substrates.

We present and experimentally confirm a thermal heat flow model which determines the steady state solution of filamentary resistive switching. We show that the application of this model to a single current-voltage hysteresis loop provides a detailed characterization of filament evolution across the entire resistive switching range, providing a continuous description of the filament: radius, conductivity, heat flow, and temperature. This solution provides a description of the interplay between the two dominant state variables (filament radius and conductivity), and describes how to control each one separately. Finally, comparing our steady state solution to literature data, we confirm its validity of the steady state solution at all relevant timescales (ns and above), as well as its applicability in a wide range of materials.

The existence of anomalous capacitance transients which lead to overestimated interfacial state densities obtained by means of deep level transient spectroscopy (DLTS) has been experimentally demonstrated in metal-oxide-semiconductor (MOS) capacitors based on very thin Al2O3 layers (3.4 - 3.9 nm). In the DLTS technique a voltage pulse is imposed over the quiescent bias corresponding to weak inversion. This brings the sample to the accumulation regime, so that the interfacial traps are filled and then a capacitance transient occurs at the end of the pulse when the captured charge is released. In a conventional MOS structure, the capacitance transient amplitude can be related to the interfacial trap density. However, in very thin high-k dielectric based MOS structures, the capacitance transient amplitude is too big, and hence the interfacial state density is overestimated. This behavior does not depend on the sample temperature: in fact, transients are very large even at low temperatures. Moreover, the transient amplitude does not change when the bias voltage or the pulse height are changed.
In order to clarify this anomalous DLTS behavior, we have applied an “inverse bias pulse” (that is, from accumulation to weak inversion) and we have looked for capacitance transients. Decreasing capacitance transients occur with amplitude similar to those appearing in accumulation. These “reverse transients” are independent of temperature and voltage as well. When making the same test in samples without anomalous DLTS behavior (the thicker ones) these “reverse transients” do not appear.
To explain this behavior we conclude that a two-dimensional quantum well is formed at the metal insulator interface. The quantum well discrete electronic levels are emptied/filled when applying accumulation/inversion voltages: electrons coming to/from the semiconductor substrate pass through the very thin insulator barrier by tunneling (i.e., regardless the temperature and voltage stress).

Resistive random access memory (RRAM) devices are widely believed to be a promising candidate for future memory and logic applications due to its low energy consumption, low operation voltage, high switching speed and excellent scalability. In this study, we report detailed retention studies of a TaOx based RRAM at high temperatures and the development of oxygen diffusion reliability model of metal-oxide based RRAM devices. The device consists of a bilayer TaOx/Ta2O5 stacking structure as the functional layer, which has been shown to exhibit excellent performance metrics. The device conductance in low resistance state (LRS) was constantly monitored at several temperatures (above 300 degree Celsius), and an initial gradual conductivity drift and followed by a sudden conductance drop were observed. These observations were explained by the fact that oxygen vacancies diffused away from the filament region in the Ta2O5 layer where the oxygen vacancies concentration was higher than that of bulk, resulting in a reduction of the peak oxygen vacancy concentration in the filament and conductivity reduction. The sudden drop corresponds to the transition below a critical oxygen vacancy density such that a continuous electron conduction path is no longer maintained. Specifically, the activation energy for oxygen vacancy diffusion can be directly calculated from the failure time versus temperature relationship. Additionally, the initial gradual decrease in conductivity can be precisely modeled through lateral diffusion by assuming a Gaussian distribution of the oxygen vacancies. The experimental results can be well explained by both analytical modeling and detailed numerical multi-physics simulation, which confirm the filamentary nature of the conduction path in LRS and the importance of oxygen vacancy diffusion in device reliability. Finally, these high-temperature stability measurements also reveal the existence of multiple filaments in the same device, and the results were fully supported by device modeling.

Vertical thin film transistors (VTFTs) have an advantage of being able to be operated under high electric fields due to their extremely short channel lengths defined by the film thickness. As one type of VTFTs, permeable metal-base transistors (PMBTs) with a permeable metal film embedded between two semiconductor layers have been proposed. The advantages of PMBTs compared with other three-terminal devices such as field-effect transistors, hetero-junction bipolar transistors, or high electron mobility transistors are the simplicity of fabrication and the ability to be operated at high power density and higher frequency because of the short channel lengths. Recently, organic PMBTs employing a porous thin metal film as a permeable metal base have been reported. However, the current amplification factors are low (<10) and there is very little understanding of the device physics. In this work, by controlling the porosity of the metal base on top of the organic semiconductor, N,N&’-dimethyl-3,4,9,10-perylene tetracarboxylic diimide (Me-PTCDI), NPN type organic PMBTs with current amplification up to 476 were achieved with output current saturation. Because of the granular structure on the Me-PTCDI surface, we found that the nano-porosity of the metal base can be controlled with a high degree of accuracy by tuning the thickness of the metal base film. To fabricate high current gain PMBTs with current saturation, we discovered that 20 nm-size pores are required. Based on our device simulation results, current saturation can be achieved with the small pores (~ 20 nm) in the metal base due to potential-pinning effect at the emitter-base interface. Finally, we also extended this approach to fabricating inorganic-organic hybrid PNP-type PMBTs with a current gain of 260.

Using first-principles density functional theory calculations, we have investigated the electronic properties and O vacancy formation with the relevant induced defect states in La-doped hafnium oxides (Hf1-xLaxO2-0.5x) over a range of chemical composition from x = 0 to 0.5. The PBE0 hybrid density functional was employed for the analysis of the electronic properties and the charge transition levels of the O vacancy in amorphous Hf1-xLaxOy and the relevant Hf2La2O7 pyrochlore structure, respectively. Our hybrid functional calculations showed that the electronic band gap of the Hf1-xLaxO2-0.5x structure was slightly reduced by 0.35eV as the La content increases from x = 0 to 0.5. Our Bader charge analysis also showed that the average atomic charge on Hf (La) atoms can decrease from 2.32 (2.12) to 2.26 (2.06) as the La content increases from x = 0 to 0.5, which indicates that the ionicity of the Hf (La) atom tends to decrease as the La concentration increases. This result is consistent with our calculations for the Hf 4f core level energy, which reveal a binding energy shift of around 0.3~0.6 eV as the La content increases from x = 0 to 0.5, in good agreement with a recent experimental measurement. Furthermore, our calculations also demonstrated that the valence band edge of the Hf1-xLaxO2-0.5x structure tends to lift with the La concentration, which might thus reduce the valence band offset between Si and Hf1-xLaxO2-0.5x from 3.0 to 2.0 eV as the La content increases from x = 0 to 0.5. We next calculated the formation energy of O vacancy in the Hf1-xLaxO2-0.5x structures using the PBE0 hybrid functional. Based on our generated structure models, several typical kinds of O coordination structures were identified in the amorphous La-doped hafnium oxides. Different from the cases in Hf-silicates, the formation energies of O vacancy were found to be not only dependent on the local structure of the vacancy sites but also strongly dependent on the chemical composition of the Hf1-xLaxO2-0.5x structures. Our calculated results showed that the O vacancy formation energy is likely to increase as its La coordination increases. However, it appears to decrease as the La concentration increases primarily due to the reduction of ionicity of the cations in the Hf1-xLaxO2-0.5x oxide structures.

Resistive switching characteristics of the mixed layer consisting of Fe2O3 and Pt-Fe2O3 core-shell nanoparticles (NPs) were investigated. The Fe2O3 and Pt-Fe2O3 core-shell NPs were chemically synthesized with a diameter in the range of 10~15 nm. The Fe2Onot;3 NPs were synthesized through decomposition of Fe(CO)5 precursors and subsequent oxidation in the colloidal solution. The Pt-Fe2O3 core-shell NPs were synthesized through the decomposition and reduction of Fe and Pt precursors, and subsequent preferential oxidation of Fe for shell formation and pile-up of Pt into the core in the colloidal solution. The mixed layer of γ-Fe2O3 and Pt-Fe2O3 core-shell NPs with a thickness of ~30 nm between Ti and Pt electrodes exhibited both analog and digital bipolar resistive switching depending on the applied voltage. It showed the hysteresis of current-voltage curves with sequentially reducing resistance as repeating -1.5 V sweep at Ti top electrode while increasing one as repeating +1.5 V sweep. As increasing the voltage to +3 V, the digital bipolar switching could be obtained. After the first SET transition from high to low resistance state around at +3 V, the subsequent reverse RESET and SET transitions occurred about at -1 V and +1~2 V, respectively. Also, the pulse operation at 2 V for 100 ms led to the bipolar on/off switching with a ratio larger than two orders of magnitude. The bipolar switching is thought to be associated with facilitated interconnection of filaments between metallic Pt cores in the mixed NPs layer. In this presentation, the detailed resistive switching characteristics of NPs layers will be discussed for the application to nonvolatile resistive memory device with colloidal NPs assembly.

The quest for high-mobility MOSFET channel material has led electronic material researchers to replace silicon by germanium in advanced technologies. This field of research has been the subject of many studies in recent years (see for example [1]). One of the main problem of the rise of germanium as a possible material is its oxide, GeO2, and its interface with the latter, because of the larger defects density in Ge:GeO2 than in Si:SiO2.
In this study, we performed first principles calculations on defects and dopants in crystalline and amorphous GeO2. Calculations based on the Density Functional Theory (DFT) using the Local Density Approximation (LDA) are performed through the PWscf code from the Quantum ESPRESSO distribution [2]. These calculations allow us to have access to the atomic configurations of defects and dopants and to their energy properties. Starting from the wavefunctions and from the atomic configurations obtained in DFT, we use the SaX code version 2.0 [3] to apply the GW approximation to obtain a right value of the band gap and to evaluate the effects of point defects, dopants and impurities on the electronic properties of GeO2. Finally, the optical properties (particularly the absorption spectra) of pure and doped GeO2 are given including excitonic effects with resolution of the Bethe-Salpeter equation (BSE). A particular attention will be given to the levels introduced by dopants and defects in the electronic structure of Germania and their effects in terms of charge capture will be discussed. We already successfully applied this methodology to oxygen vacancies in pure and Germanium doped silica [4] and the results obtained will be discussed and compared to the results coming from this previous study and from literature.
[1] M. Houssa, A. Satta, E. Simoen, B. De Jaeger, M. Caymax, M. Meuris, and M. Heyns, in Germanium Based Technologies: From Materials to Devices, edited by C. Claeys and E. Simoen Elsevier, Amsterdam, 2007, p. 233.
[2] P. Giannozzi et al., J. Phys. Condens.Matter, 21, 395502 (2009).
[3] L. Martin-Samos and G. Bussi, Comp. Phys. Com., 180, 1416 (2009).
[4] N. Richard et al., J. Phys.: Condens. Matter, 25, 335502 (2013).

Germanium MOSFETs are a solution to extend the roadmap beyond traditional Si MOSFETs. High-k dielectrics are required to achieve the necessary gate capacitance densities for highly-scaled devices. Synthesizing a high-k/Ge interface with small interface trap density is a critical challenge for EOT scaling of Ge-MOSFET technology. Previous research shows that both pre-dielectric Ge surface preparation and post high-k dielectric deposition treatments are necessary to achieve low interface trap density in high-k/Ge structure. Previously reported post-deposition anneals of Ge MOS devices include oxygen based anneals and hydrogen based anneals.
We fabricated Pt/TiO2/Al2O3/Ge MOSCAPs with EOT ~ 0.6 nm with the help of post-electrode forming gas (H2/N2) anneal (FGA). Transistors with similar structure and processing with sub-1 nm EOT, and abrupt (SS = 71mV/dec) turn-on behavior were also fabricated. However, the mechanism by which FGA reduces the Dit of the Al2O3/Ge interface is not well understood. In this abstract, the post-ALD annealing by different methods on Al2O3 interface are compared and the influence on interface chemistry and defects passivation is discussed.
In Si/SiO2 system, FGA has been clearly shown to produce stable Si-H bonds that passivate oxide/Si interface traps. However, in high-k/Ge, our experiments show that the effect of post-metal FGA is directly related to the kind of gate metal used. FGA is also found to be less effective when it is done before metal deposition than after. D2/N2 annealing and SIMS analysis will be performed to detect the role of hydrogen(Deuterium) and potential Ge-H (Ge-D) bond formation during the annealing process. Previous researchers have demonstrated that, in vacuum, germanium oxide will react with Ge to form volatile GeO at temperatures above 320°C, but we observed that the temperature corresponding to best FGA effect (smallest Dit) is as high as 450°C. Third, we observed an inverse correlation between the Al2O3 physical thickness and a minority carrier feature associated with Dit in capacitance-voltage curves, which cannot be explained by conventional theory. This minority carrier associated Dit cannot be passivated effectively under normal reported FGA temperature (350oC), but can be further passivated under higher annealing temperatures.
Soft x-ray synchrotron PES techniques are used to investigate the Al2O3/Ge interface. The GeOx PES peak from the Al2O3/Ge interface is difficult to characterize due to its ultra-thin thickness and the barrier for escaping photoelectrons through the overlying Al2O3 film. Samples with pinhole free 1.1nm Al2O3 on p-type Ge substrate with various annealing conditions are fabricated and characterized under SSRL line 8-1 with 120eV photon energy. By detecting peak shifting between Ge 3d peak and its oxide peaks, a clear correlation of Ge +4 peak increase with longer FGA time and higher FGA temperature is apparent, indicating GeO2 formation at the interface.

Nanoscale metal/metal-oxide/metal resistance switches show a variety of outstanding device behaviors including high on-off ratios, robust non-volatile switching, multi-level resistance values, and excellent dimensional and energetic scalability, and are promising as scalable low power non-volatile memories, variable resistors for tunable devices, and adaptive computing circuits. Within this class of materials, record on-off ratios have been observed in W/GeOx/Cu films, where switching is believed to result from oxidation and transport of reactive Cu atoms to form conducting filaments.[1]
Understanding and controlling nanoscale electrochemical reactions and ionic transport through dielectric layers in defect-rich environments is an extremely difficult challenge, but is essential to developing a mechanistic understanding of the electrical switching process. In the W/GeOx/Cu system, both the oxidation state and crystallinity can be controllably tuned in the GeOx layer. This results in a modified activation energy of ionic hopping, and distribution of available low-energy transport pathways (e.g., grain boundaries), thereby changing the electric field required to grow or disrupt conductive filaments. Thus, GeOx is interesting both as a model system in which to investigate ionic transport in defect-rich environments, as well as a promising candidate material for devices with tunable resistance switching characteristics.
Here, we report a series of experiments designed to isolate the effects of variable oxygen stoichiometry and crystallinity on resistance switching characteristics in GeOx Thin Films. We grew GeOx films (10-50 nm thickness) on smooth W bottom contacts by reactive magnetron sputtering from a metallic Ge target under variable total pressure and oxygen partial pressure conditions. GeOx films were observed to have variable oxidation states from x = 0 in films grown under a pure Ar atmosphere to x = 2 in films grown above 70 mPa of partial pressure Ar. Film crystallinity and microstructure were controlled by deposition temperature and ion energy distributions (using DC, pulsed DC, and high powered impulse magnetron sputtering techniques). Resulting film microstructures were investigated with AFM, XRD, and TEM, and device switching properties (V_set, V_reset, R_set, R_reset) were characterized by standard probe station techniques utilizing a semiconductor parameter analyzer. Switching properties will be discussed in the context of standard ionic transport and redox reaction rate models.
[1] S.Z. Rahaman, et al., Appl. Phys. Lett. 101, 073106 (2012); doi: 10.1063/1.4745783

As continuously scaling down the devices for logic circuit, it is indispensable in overcoming the issues of mobility degradation and S/D parasitic resistance. Ge possesses high hole mobility and has been reported for replacing Si to continuously boost the device performance. The Si/Ge/Si quantum well architecture with biaxial compression strained and quantum confinement effect was presented being able to enhance the hole mobility. However, a large difference among Si and Ge of dopant activation temperature, indicating a stern challenge of S/D engineering should be surmounted. Therefore, we propose using NiSiGe/n-Si Schottky junction enables a further improvement the performance of Ge quantum well device.
Si cap and strained Ge films were epitaxially grown on an n-type (001) Si wafer using ultra-high vacuum chemical vapor deposition system. The Ge film (~5 nm) was grown at 420 °C after 900 °C for 10 minutes of baking in a high vacuum ambient followed by Si cap (~1 nm) deposition at 665 °C. A SiO2 was deposited on the Si/Ge/Si architecture as isolation after surface cleaning was conducted. Next, the active area of junction was defined by the lithography and wet etching was performed. The Ni (30 nm) was deposited by sputtering, followed by rapid thermal anneal (RTA) ranging from 450 to 650 °C for 60 s in N2 ambient to form the NiSiGe alloy. Subsequently, unreacted Ni film was removed, and Al was deposited to form back contact. A NiSiGe/n-Si Schottky junction was investigated with SEM, TEM, XRD, and electrical characterizations.
The SEM pictures show the surface morphologies of NiSiGe layer at various annealing temperatures. It is observed that the uniform NiSiGe layers have been achieved at lower than 600 °C and the agglomeration phenomenon occurs when the annealing temperature arises up to 650 °C. The cross-sectional HRTEM images show the polycrystalline structure, good uniformity of the NiSiGe and a distinct interface between NiSiGe and Si. Moreover, the GIXRD spectra for various annealing temperatures confirm the NiSiGe formation. The peaks corresponding to (111), (211), (121), and (301) NiSiGe can be identified and the peak intensity is a function of annealing temperature. Additionally, in order to study the impact of different annealing temperatures on NiSiGe/n-Si Schottky junction, the I-V characteristics is used to check the electrical performance. The Schottky junction exhibits the best ION/IOFF ratio of 1E5 formed at 500 °C. On the other hand, the effective Schottky barrier height and ideality factor of ~0.68 eV and 1.05, respectively, were extracted from the I-V characteristic which certainly is beneficial to boost the performance of Schottky junction.
The NiSiGe/n-Si Schottky junction is a quite crucial point for Si/Ge based quantum well p-channel MOSFETs. We think that our quantum well architecture is promising for the future applications of high performance logic circuits and enable Ge channel devices to be integrated on the Si.

GaN is one of the promising materials for the applications of high-temperature and high-power electronics with wide band gap energy, high breakdown fields, and high saturation velocities. Even though it in the development of GaN- based wide band gap semiconductors fabricated on high electron mobility transistors (HEMTs) have demonstrated promising device performances. However, Schottky-contact gate electrodes tend to cause a relatively high gate leakage current, which potentially limits their reliability and performance.
To address high gate leakage current issue, introduction of GaN cap layers and high-k gate dielectric materials on top of AlGaN/GaN channel have been suggested. In this work, we have combined these two techniques and fabricated high-k dielectrics deposited on n+ GaN cap layer for AlGaN/GaN MOS-HEMTs.
Addition of various cap layers (i-GaN, InGaN, p-GaN) on the AlGaN surface has been shown to mitigate dispersion effects for MOCVD grown material. Among them, n-GaN cap is very attractive because of advantages such as low leakage current and low contact resistance with possibly sustaining transconductance and drain current density of HEMT without cap structure.
AlGaN/GaN metal-oxide-semiconductor HEMTs (MOS-HEMTs) to suppress the gate leakage current have been developed by the use of dielectrics with high permittivity (high k). Because of larger dielectric constant, more efficient gate modulation is possible and it results in a smaller decrease in transconductance and a moderate increase in the threshold voltage in MOS-HEMTs.
We fabricated A 4um buffer layer, a 300nm undoped GaN layer, 20nm undoped AlGaN(Al=0.2) layer, and 20nm doped GaN layer with concentration 5e18 were sequentially grown by metal-organic chemical vapor deposition on a 6-in silicon substrate. Ohmic contacts were formed by electron-beam deposition of Ti/Al/Ni/Au(20nm/160nm/50nm/100nm) and a lift-off process followed by 900C anneal in N2 ambient. A 5nm-thick Al2O3, HfO2 were deposited for each sample as gate dielectric. Gate was formed by e-beam evaporation of Ni/Au(30 nm /250nm) and lift-off process. All levels of lithography were done by contact aligner. The gate lengths, Lg, for devices are 5, 10, and 20um/ The gate width, Wg, is 400um

We report systematic studies that co-relate electrical characteristics of AlGaN/GaN MOS-HEMT with the uses of atomic-layered-deposited Al2O3 and HfO2 on n+ GaN cap layer. Fabricated devices demonstrated encouraging output as well as transfer characteristics, such as a high drain current (Id) with negligible current collapse, a high transconductance (Gm) and low gate leakage current(Ig).

The charge trapping memory (CTM) devices such as silicon-oxide-nitride-oxide-silicon (SONOS) type and nanocrystals (NCs)-based CTM devices have been studied for many years. As a result of continued scaling down, some reliability issues still exist in SONOS type and NCs-based CTM devices. Few electrons for information storage and low charge trapping efficiency are the crucial problems for nanoscale SONOS devices. For NCs-based CTM device, when the size of the cells scales down to 22 nm or less, very limited numbers of NCs would be contained in a memory cell. As a result, the charge trapping capability of the devices will decrease dramatically. So, a charge trapping layer with high charge trapping capability in a small scale is critically important for the further application in CTM devices. The charge storage mechanisms in CTM devices have been researched for many years, and it is obvious that the charges are stored in the trap sites of the charge trapping layer for both SONOS type and NCs-based CTM devices. The more the trap sites exist in the charge trapping layer, the better charge trapping capability the device has.
In this work, an effective method to generate traps at the interface was developed to enhance the charge trapping capability of HfO2/Al2O3 multilayered memory devices. Three memory devices were fabricated with a consistent thickness of the charge trapping layer but with different numbers of Al2O3 intercalation layers inside the charge trapping layer. A high charge density was obtained in the inter-diffusion layer in which additional trap sites could be created by thermal-treatment induced inter-diffusion, and a lot of charges can be trapped in this inter-diffusion layers. As the number of the inter-diffusion layer increases, the charge trapping capability of the RTA samples increases significantly. Especially for 5L-RTA sample, the total charge trapping merit increases by about 60%, as compared with the as-deposited samples, indicating that increasing the number of the interfaces with strong inter-diffusion is an effective approach to create more traps in the charge trapping layer with a consistent thickness. Also, the intercalation layer Al2O3 in HfO2 can suppress the tunneling process of the trapped charges back to Si substrate, and enhance the retention characteristics of the devices. Therefore, the stack structure composed by HfO2 and Al2O3 can be a potential way to increase the charge trapping capability and the retention performance when the size of the devices scales down.

Resistive memories based on graphene oxide (GO) thin film have been extensively studied for application as next-generation nonvolatile memory devices. It has attracted much attention due to its electrical properties, solution processability and application to scalable device fabrication. In spite of this, the mechanism of GO based memory has not been clearly established because the observed switching behavior seems to differ depending on the electrodes. To clarify the underlying mechanism, it is crucial to evaluate electrical properties depending on the type of electrodes and microstructure between GO and electrode layers.
In this work, GO solution was prepared by a modified Hummers method. 5 × 5 cross-bar type electrode was deposited using thermal evaporator, and the thickness of electrodes were about 55 nm. A trilayer metal/GO/Al devices of cross-point structure were made on SiO2 wafer with uniform GO film prepared by spin coating. Chemical properties of GO thin film were characterized by Raman and IR spectra. Top electrodes had a different free energy of oxide formation, so the formation of the interface layer was confirmed by high resolution electron microscopy (HRTEM). Al/GO/Al device exhibited a typical bipolar resistive switching (BRS) with set/reset voltage of ~ -2.6 V/2.2 V and a high on/off ratio of >10^3. Both on and off states were stable for more than 10^5 s. No degradation of memory performance was observed ~ 100 cycles. The critical role of the interface between top electrodes and GO layer was confirmed by replacing the top electrode with Ni, Ag, and Au, where the switching performance was failed after some sweep cycles. Oxygen ion movement in the active layer was generally accepted as a primary mechanism. In order to compare the oxygen ion movement in the interface layer between the electrode and GO layer, electron energy-loss spectrometers (EELS) profile was analyzed. Detailed electrical properties of GO based memory and microstructural observation between GO and electrode layer will be discussed.

Strain engineering is an effective way to enhance p-channel field-effect transistor (pFET) drive current. Epitaxial Si1-xGex embedded source/drain (S/D) with larger Ge concentration generates higher compressive stress in the channel region. However, defect generation such as dislocations or stacking faults resulting from the strain relaxation limits the Ge concentration to a certain value. To minimize the generation of crystal defects in the epitaxial Si1-xGex layers in the S/D structures, and consequently maintain maximum compressive stress, graded Ge concentration in the epitaxial Si1-xGex layer has been suggested. In this study, we report the strain evolution in the channel region induced by the embedded epitaxial Si1-xGex layers with the graded Ge concentration by TEM and nano beam diffraction analyses.
Epitaxial Si1-xGex layers were grown by using ultrahigh vacuum chemical vapor deposition (UHV-CVD) on the bare and patterned Si wafers. The flux of Ge source gas, GeH4, was varied during the selective epitaxial growth process. From HR-XRD and EDS measurement, Ge concentration, x, was found to be 0.20~0.38. These Si1-xGex layers were stacked with different thicknesses. The crystal micro structures and the strain evolution are analyzed by transmission electron microscopy (TEM) and nano beam diffraction (NBD). By applying graded epitaxial Si1-xGex on the pFET, it is able to optimize uniaxial strain in the channel region.

In this work, the effect of crystallinity and concentration of non-lattice oxygen on the resistance switching characteristics of Al doped HfO2 films was investigated in conjunction with an analysis of the microstructure and chemical bonding states. TiN/Al doped HfO2/Pt metal-insulator-metal (MIM) stacks were fabricated using HfO2 films with various Al contents sputtered by reactive dc magnetron co-sputtering. From XPS analysis, the doping concentration of Al in HfO2 films was 2.9%, 5.6%, and 16.8%, respectively. The resistance switching characteristics of the MIM stacks were examined with a study on the physical properties such as the microstructure and chemical bonding states of Al doped HfO2 films.
The microstructure of as-grown HfO2 films shows the monoclinic and tetragonal structure. The crystallinity of Al doped HfO2 films, however, were decreased with increasing Al doping concentration. The number of grain boundaries of Al doped HfO2 was decreased with increasing Al doping concentration. At 16.8% Al doping concentration, the Al doped HfO2 film showed the amorphous phase. The concentration of non-lattice oxygen in Al doped HfO2 films was increased with increasing Al doping concentration. The change of non-lattice oxygen concentration in the Al2O3 films was also observed similar to the change of conductivity. TiN/Al doped HfO2/Pt stacks showed typical bipolar resistance switching characteristics after electro-forming process. In general, a large number of grain boundaries and high concentration of non-lattice oxygen lead to high conductivity of the metal oxides. The resistance switching characteristics of Al doped HfO2 films was influenced on change of grain boundaries and non-lattice oxygen concentration. From these findings, we estimated that the controlling of microstructure and the chemical bonding states influenced the resistance switching characteristics of Al doped HfO2.

Tunnel oxide of future SONOS memories would be very challenging to downscale if data retention of ten years were still required [1]. Using multi-layers of tunnel oxides is proven to be an effective solution; however, most of the published papers on Tunnel Band Engineering (TBE) for SONOS study the effect of triple-layer tunnel oxides in addition to their lack of an explanation of the physics of TBE [2]. In this work, a double layer SiO2/HfO2 tunnel oxide for SONOS is investigated and compared to single high-κ dielectric HfO2 and single SiO2 tunnel oxide cases using Physics Based TCAD simulations. Also, light is shed on the physics of the structure with the stack.
The structure is a Si N-MOSFET with gate length 130 nm and the following gate stack which can be Atomic Layer Deposited: 2 nm SiO2 or HfO2 for the single tunnel oxide case, while 0.5 nm HfO2 on top of 1.5 nm SiO2 for the stack , then 8 nm Si3N4 charge trapping layer and 4 nm SiO2 blocking oxide. Fowler-Nordheim, Direct, and Trap Assisted Tunneling were used to model charge transport across the device. The effect of the equivalent oxide thickness (EOT) on the threshold voltage (Vt) shift is studied with a Program/Erase Voltage (P/EV) of 10/-10V. The achieved Vt shift is highest for the double-layer oxide case at all EOTs thus allowing for thinner tunnel oxides without compromising the Vt shift. At an EOT of 2 nm; the obtained Vt shift is 1.8V with HfO2, 2.8V with SiO2, and 3.3V with the stack. Also, Vt shift vs. the programming voltage is studied for the structures with the same EOT (2 nm). For high Vt shifts, the SiO2/HfO2 stack achieves a higher reduction in programming voltages than single oxides. By analyzing the energy band diagram of the SONOS with the stack; when the applied voltage across the SiO2 layer is high enough, the conduction band edge of the silicon substrate becomes higher than the conduction band edge of the HfO2 leading to direct tunneling across a thinner SiO2 layer than in the case of single oxide due to the same EOT. And the quantum tunneling theory states that the probability of charge tunneling increases exponentially when the oxide thickness decreases. This proves the higher Vt shift achieved with SiO2/HfO2 than with single tunnel oxide. However, the stack leaks more charges in time than single SiO2 because electrons in the conduction band of Si3N4 can tunnel back through a thinner SiO2 due to the larger electron affinity of HfO2. However, the ten years data retention is maintained with the stack. These results prove that TBE can be used to further reduce the operating voltage or the EOT of future memory devices without sacrificing Vt shift or data retention of 10 years. [1] S. Lai, “Tunnel oxide and ETOXTM flash scaling limitation,” in Int'l Non-Volatile Memory Technology Conference, 1998. [2] G. H. Park and W. J. Cho, “Reliability of Modified Tunneling Barriers for High Performance Nonvolatile Charge Trap Flash Memory Application”, Appl. Phys. Lett. 96, 2010.

ZnO has been recently considered as a promising candidate to be used in flexible and/or transparent nanodevices due to its wide bandgap, good transparency, and low light sensitivity. Thin film transistors were demonstrated using ZnO channels deposited by Atomic Layer Deposition (ALD) [1]. In fact, the deposited ZnO is naturally n-type due to native crystallographic defects such as interstitial zinc and oxygen vacancies, which behave as electron donors [2]. Recently, we validated a functional ZnO-based charge trapping memory grown by single ALD step [3]. In this work, the latter memory performance was improved by replacing the ZnO charge trapping layer by an ultra-thin CrO2 layer.
The channel-last memory cells are fabricated on highly doped p-type (111) Si wafers. First a 15-nm-thick Al2O3 blocking oxide is first ALD deposited followed by a sputtering of a 5-nm-thick CrO2 as the trapping layer, then a 4-nm-thick Al2O3 tunneling oxide followed by an 11-nm-thick ZnO channel are ALD deposited at 250°C. Using the Atomic Force Microcopy (AFM), the CrO2 layer RMS surface roughness was measured to be 1-nm which highlights the continuity of the grown nanolayer. The fabricated memory showed a 2.6V threshold voltage (Vt) shift at a programming/erasing voltage (P/E) of 10V/-10V. Also, for a 2V Vt shift, the memory with CrO2 has a low programming voltage of 7.2V which means a reduction of 2.3V in the programming voltage compared to the same memory with ZnO charge trapping layer in our last work [5]. Moreover, the deep trapping levels in CrO2 provide a good retention time; allowing for additional scaling of the tunnel oxide. Finally, the structure was simulated using Physics Based TCAD. To the best of our knowledge, there are still no studies published on the CrO2 charge trapping and tunneling properties, however, TCAD simulations allowed getting approximate models for these properties. The simulations results fit very well with the experimental ones proving the accuracy of our proposed charge trapping and tunneling models of the 5-nm-thick CrO2 layer: a donor level at 1.1 eV from the conduction band with a density of 10E21 cm-3, an acceptor level at 0.2 eV from the valence band with a density of 10E21 cm-3, electron and hole effective masses of 0.29m0. These results are promising for future low cost, flexible and transparent electronic applications. [1] R.L. Hoffman, B.J. Norris, and J.F.Wager, “ZnO-based transparent thin-film transistors,” Appl. Phys. Lett., vol. 82, no. 6, pp. 733-735, 2003. [2] C.S. Hwang, H.S. Kwack, J.H. Lee, and H.Y. Chu, “Characteristics of ZnO Thin Films by Means of Plasma-Enhanced Atomic Layer Deposition,” Electrochem. Soild-State Lett., vol. 9, no. 10, July 2006. [3] Feyza B. Oruccedil;, Furkan Cimen, Ayman Rizk, Mohammad Ghaffari, Ammar Nayfeh, and Ali K. Okyay, “Thin-Film ZnO Charge-Trapping Memory Cell Grown in a Single ALD Step,” IEEE Electron Device Lett., vol. 33, no. 12, 2012.

In recent years high-k materials, such as HfO2, TiO2, ZrO2, Y2O3 and La2O3, have been studied to replace Si3N4 in SONOS type memory devices to achieve a better storage performance and retention property, and Al2O3 as a high-k dielectric was also chosen as the tunneling and blocking layers in many similar memory devices due to its good chemical and thermal stability and large band offsets with Si. In addition, new structures of dielectric stacks, such as multilayered charge-trapping layer HfO2/Al2O3/ HfO2 and ZrO2/Al2O3/ ZrO2 have been fabricated to further improve the charge storage and the retention characteristics of the memory devices. It was suggested that the enhanced charge-trapping ability was related to the interface formed by two different high-k materials, and point defects formed by the inter-diffusion at the interface may dominate the charge-trapping property. Here, we report a charge-trapping memory device with a structure Pt/Al2O3/(TiO2)0.8(Al2O3)0.1(TAO-82)/Al2O3/Si, in which an oxide composite layer including two different oxide dielectrics was employed as the charge-trapping layer. This kind of memory device with a simple structure, a further scaling-down ability, a fast write/erase speed, a good endurance and a good retention property should be a one of the choices for the next generation nonvolatile memories.

To make a practical Si-based optical interconnection system, transceivers have to be fabricated compatibly with Si CMOS processes. Due to superior optical properties afforded by direct band gap materials, compound semiconductors have been chosen for the materials for lasers and photodetectors. Historically Germanium has shown acceptable compatibility with existing Si CMOS processes. A significant progress has been reported on the improvement of Ge-based photodetector, which are fabricated monolithically on Si platform. There are few studies, however, yet reported on Ge-based lasers fabricated on Si substrates. In the fabrication of Si-compatible Ge lasers, two challenges have to be overcome. Germanium is epitaxially grown on Si substrate with a 4% lattice mismatch, and germanium&’s indirect band versus momentum has to be appropriately addressed. For the germanium, fortunately, there is small difference, 136meV, between L-valley and Γ-valley, called pseudo direct bandgap. It is possible to reduce the difference by giving a strain to germanium. When tensile strain is induced, both L-valley and Γ-valley bandgap is decreased, but Γ-valley bandgap decreases rapidly. Moreover, tensile strain increases the energy level of valence band of light hole, so the hole mobility is expected to improve. Therefore, germanium becomes a proper material for photonic transceivers.
In this work, we induced tensile strain to the epi-Ge layer grown on Si substrate using post growth annealing. Different thermal expansion coefficients of Ge and Si leave a tensile strain in a thin epi-Ge against Si substrates. Crystal defects caused by a lattice mismatch were annealed simultaneously. To understand the effect of post growth annealing, Ge was grown on Si at low temperature using chemical vapor deposition and subsequently post-annealed at various temperatures using rapid thermal process over growth temperature. We quantified tensile strain and crystal quality by Raman spectroscopy and HR-XRD analysis. Given penetration depth of germanium determined by the wavelength of Raman spectroscopy, results show a strong dependency of induced tensile strain on post annealing temperatures. This tensile strain behavior measured as a function of temperature was in good agreement with HR-XRD analysis. FWHM extracted from Raman and HR-XRD supported a simultaneous improvement of crystal quality during post anneal. Comparing Raman and HR-XRD data, we will describe the difference of strain and crystal quality depending on the depth. And the tensile strain inducing mechanism difference of in growth stage and in post growth annealing stage will be discussed.

In pursuing better ferroelectric materials and devices, doping and forming solid solutions are effective approaches to tailor the crystal structures and therefore to achieve the desired properties. The most well-known example is Pb(Zr_xTi_1-x)O₃ (PZT) solid solution with the morphotropic phase boundary (MPB), which exhibits much enhanced electromechanical coupling response. Recently, BiFeO₃ (BFO) has attracted great interest due to its multiferroic nature at room temperature. In order to explore new opportunities in BFO-based solid solutions, which are currently less studied, here we report ~100-nm-thick epitaxial BiFe_0.6Ga_0.4O₃ (BFGO) thin films synthesized by RF sputtering that apparently show colossal switchable polarization larger than 600 mu;C/cm².
High resolution synchrotron X-ray diffraction reveals that the intrinsically stable phase in BFGO thin film is a super-tetragonal-like phase with a giant c/a ~ 1.25 and a monoclinic tilt ~ 2^o, irrespective of the substrate induced misfit strain. Moreover, two pairs of twins with monoclinic tilts along four different directions within {110}_pc planes are observed. Piezoresponse force microscopy (PFM) demonstrates their ferroelectric behaviors and domain configurations. First-principles calculation predicts that a monoclinic Cm phase is energetically favored. The ferroelectric polarization vector and the contribution from each atom were calculated.
Macroscopic P-E loops show extremely high values of electrical polarization > 600 mu;C/cm² at frequencies below 3.3 kHz. The overall polarization is strongly dependent on the frequency at the low frequency range, indicating that the extrinsic contribution from space charge to the overall polarization at low frequency is significant. Remanent hysteresis loop and positive-up negative-down (PUND) measurements were performed to properly evaluate the intrinsic ferroelectric polarization (Pr ~ 150 mu;C/cm²). The BFGO thin film shows a very low dc leakage current density (~1×10^-6 A/cm² at 100 kV/cm) and the J-E curve is fitted well by the space charge limited current (SCLC) model. Investigations into dielectric relaxation and scaling behaviors identify the most likely charge carriers to be oxygen vacancies (VOs). Furthermore, these VOs tend to reside within domain walls and form clusters. X-ray photoelectron spectroscopy (XPS) further confirms the existence of VOs. Based on these experimental observations, we propose an operational mechanism in BFGO thin film — charged VOs (and also other defects) migrate and assemble with the motion of domain walls when polarization switching takes place, whereby the oriented space charge can greatly enhance the overall polarization.

Current research towards the development of smart multifunctional materials with novel improved properties is gaining momentum as they can be used to build intelligent components for a broad range of applications. The most attractive class of smart materials are those exhibiting a phase transition or a metal-insulator transition. The metal-insulator transition is a large area of research that covers a magnitude of systems and materials. In particular, certain transition metal oxides exhibit such phase transition and among these the vanadium oxide family (V2O5, V2O3, VO2) shows the best performance, in particular, presenting a noticeable resistivity change between the two phases. Among these vanadium dioxide(VO2) has been studied intensively in the last decade because of the large reversible change in its electrical, magnetic and optical properties at a temperature close to the room temperature (~68°C) which makes it a potential candidate for introducing advanced functionalities.
Control of material structure at nanometer level has significant effect on its properties. New techniques are being investigated to synthesize different materials with control over the structure at nanometer level. We are reporting, in this communication, the developed vanadium oxide films on glass substrates by simple sol-gel dip coating technique. We have developed needle like structures, multi-corner granule structures and leaf like spongy growth by addition of suitable dopant into the precursor sol used for coating the film. We have investigated these films by UV-Vis transmission, SEM, XRD tools. Phase transition studies are under way. The technique we have used is economic over conventional thin film coating techniques like sputtering, thermal evaporation, pulsed layer deposition (PLD), CVD etc. Further the present technique gives VO2 films directly contrary to most of the techniques where V2O5 film is formed first, which is subsequently reduced to VO2 by post deposition annealing in reducing atmosphere.

Recently, ferroelectric thin film barium-strontium-titanate (BST) varactors play an important role on frequency agile reconfigurable RF and microwave front-end devices. Tunable low pass filters are anticipated for several communication systems. In this paper, a tunable planer low pass filter is proposed. A coplanar meander line structure integrated with thin film BST varactors is projected. Detailed analyses with an equivalent circuit model for the proposed low pass filter will be presented. A wide tuning range has been achieved by utilizing parallel plate BST varactors. The 3 dB frequency of the proposed low pass filter tunes continuously from 373 to 605 MHz with a tuning voltage of 5 volts and this corresponds to a tuning range of 62%. The capacitance of the employed parallel plate BST varactors varies in the range of 12 to 6 pF for applied voltages of 0 to 5V. The size of the proposed compact filter is 18x26 mm2. The measured rejection bands are greater than 50% of the tuned 3 dB frequency. The proposed tunable parallel plate BST capacitors have been fabricated on sapphire substrates. The growth method of the ferroelectric parallel plates BST capacitors will be presented. The Agilent&’s ADS commercial tool has been used for filter design and optimization. The filter has been fabricated on Rogers RO3210 substrate with loaded discrete tunable devices. The frequency response of the filter was measured using Agilent E8364A vector network analyzer.

A compact multi-bands frequency agile antenna is becoming tremendously attractive for modern wireless applications. A meander line structure with two radial stubs have been employed for proposed antenna. The Agilent&’s ADS has been utilized for the antenna design and optimization. Tunable parallel plate BST capacitors have been loaded to the proposed patch antenna for tuning purposes. The parallel plate BST capacitors have been fabricated on sapphire substrates. The fabrication procedure of proposed parallel plates BST capacitors will be presented. Frequency agile dual-bands microstrip antenna has been verified experimentally. Measured first tunable band ranges from 742 to 856 MHz and the second tunable band ranges from 1180 to 1330 MHz corresponding to changing the DC voltage from 0 to 5 V. The maximum dimensions of the proposed antenna is 22x25x1.6 mm3 which is relatively compact compared to the conventional antenna works at the same operation frequency. The size reduction has been achieved due to the novel structure of the antenna and the employment of parallel plates BST capacitors.

Lately, ferroelectric barium-strontium-titanate (BST) varactors are becoming extremely important particularly for frequency-agile RF and microwave circuits. Tunable bandstop filters are desired to eliminate unwanted signals for several communication systems. In this paper, a basic planer tunable bandstop filter is proposed. It consists of a single hairpin resonator integrated with two variable capacitors. The frequency response of proposed bandstop filter is adaptable by varying the dimensions of the hairpin resonator. Comprehensive analyses with an equivalent circuit model for the proposed bandstop filter will be introduced. The tuning capability of the proposed bandstop filter has been obtained by two methods which are employing parallel plates thin film BST varactors and by using semiconductor varactors. The resonant frequency of the proposed BSF integrated with BST varactors filter tunes from around 4.55 to 4.85 MHz with a tuning voltage of 5 volts. The capacitance of thin film BST varactors varies between 6 to 3 pF for applied voltages between 0 to 5V. Also, for BSF integrated with semiconductor varactors, the notch frequency tunes from 4.7 to 5.2 GHz. The capacitance of the employed semiconductor varactors changes from 5 to 0.8 pF by applying a tuning voltage of 15 volts. The proposed tunable thin film BST varactors have been fabricated on sapphire substrates. The growth technique of the ferroelectric BST varactors will be presented. The Agilent&’s ADS commercial tool has been used for BSF design and optimization. The filter has been fabricated on a FR-4 substrate with assembled discrete tunable devices. The frequency responses of the filter have been measured using Agilent E8364A vector network analyzer.

Ferroelectric single crystals with tailored domain structure are widely used in acoustic, nonlinear optical and data storage devices. As such, the investigation of the polarization reversal mechanisms on the level of a single domain is of immense scientific importance. Scanning probe microscopy (SPM) offers a powerful paradigm to probe polarization switching phenomena and domain formation on the nanoscale.
Here, we explore polarization switching on LiNbO3 surface as a function of temperature, humidity, bias, and domain spacing. Wide range of unexpected domain dynamics including intermittency, quasiperiodicity and chaos has been revealed . Investigations of the phenomena at different temperatures and relative humidities demonstrated essential influence of the top water layer on the domains behavior in the chain.
Observed phenomena have been explained by long-range interaction between neighboring domains in the chain due existence of spatially inhomogeneous partially unscreened depolarization field. Thorough theoretical calculations of the electric fields in vicinity of isolated fresh domain and complex computer modulation of the domain growth with presence of the top water layer on the sample surface have confirmed proposed model.
From the point of view of potential applications, the domain interaction effect demonstrated in this paper is very interesting in connection to the emergent computing paradigm known as memcomputing. It enables a new generation of memristive, memcapacitive and neuromorphic devices and potentially leads to new forms of information processing.
This research (AI, SJ, ES, AK, SVK) was conducted at the Center for Nanophase Materials Sciences, which is sponsored at Oak Ridge National Laboratory by the Scientific User Facilities Division, Office of Basic Energy Sciences, U.S. Department of Energy. AVI and VYS acknowledge CNMS user proposal, RFBR (Grants 11-02-91066-CNRS-a, 13-02-01391-a, 13-02-96041-r-Ural-a).

Great progresses have been made during the past decade in electromagnetic metamaterials, which enable numerous unprecedented applications from optical frequencies to microwave regime. However, most of these designs were static and non-reconfigurable, while the capability of active control and tuning would be beneficial for novel electronic, optical and thermal devices. Recently, the properties of vanadium dioxide (VO2) have attracted lots of attention. VO2 could change from dielectric to metal when its temperature becomes higher than 68°C. The phase transition of VO2 can be used to design novel metamaterial to have tunable optical properties.
In this work, we will numerically demonstrate two VO2 based metamaterials with switchable absorption/emission at particular wavelengths and tunable absorption/emission peaks in the mid-infrared region, by employing the excitation of magnet resonance. Magnetic resonance has been recently shown to construct perfect absorbers and selective thermal emitters, which are usually made of subwavelength metallic grating structure on a dielectric spacer and a ground metal film. The dielectric spacer plays a crucial role in exciting magnetic resonance by forming a capacitor between top and bottom metallic layers. With the finite-difference time-domain method, we will show that, selective absorption could still occur when the dielectric layer is made of VO2 with temperature below its transition temperature. However, when the temperature increases beyond 68°C, VO2 becomes metallic and as a result, the strong absorption peak disappear and the structure is basically highly reflective, resulting in a switchable metamaterial. Furthermore, magnetic resonance could also exist with polar materials within their phonon absorption band, rather than metals. Note that, dielectric VO2 has several optical phonon modes in the mid-infrared. A second metamaterial structure is then proposed, consisting of a MgF2 thin film sandwiched by a VO2 grating and a VO2 ground film. When the temperature is below its transition temperature, magnetic resonance could occur inside such a structure due to the phonon modes of dielectric VO2. On the other hand, magnetic resonance could also exist when VO2 becomes metallic, but at a different resonance wavelength due to different optical constants between its dielectric and metallic phases. As a result, a strong absorption peak could shift from 9.6 mu;m to 14.5 mu;m upon phase transition of VO2, indicating a tunable metamaterial realized by temperature change. Electromagnetic fields will be plotted and an inductor-capacitor model will be used to elucidate the underlying physical mechanism in both structures. The fundamental understanding gained here will lead to a new class of switchable and tunable metamaterials by excitation of magnetic resonance.

The band alignments of interfacial layers at the TiN/cubic-ZrO2 interface are investigated by first-principles density functional theory calculations. According to our calculations, the most stable interface structure is determined by contacting the Ti-terminated TiN (111) surface and the O-terminated ZrO2 (001) surface. Using the hybrid functionals based on the generalized-gradient approximation, we calculate the band offset of this interface structure. The calculated valence band offset is as high as 4.37 eV, which is much larger than the experimental value of ~3.6 eV. To understand this discrepancy, we focus on an interfacial layer between TiN (111) slab and ZrO2 (001) slab. Here we propose that the interfacial layer composed of TiO2 changes the direction of interface dipole moment because of bigger relative electronegativity of Ti ion than that of Zr ion, resulting in both a decrease of the valence band offset and an increase of the conduction band offset. Our model implies that the leakage current properties of TiN/ZrO2 stack and also the other metal/high-k systems can be controlled by designing the electronegativity configuration at the interface. We expand to investigate another interfacial layer of Ti2O3 that plays the same role with TiN metallic layer.

Today, Germanium Metal-Oxide-Semiconductor Field-Effect Transistor (Ge MOSFET) is drawing attention because of its high carrier mobility and excellent compatibility with silicon process technology. However, Fermi-level pinning near the valence band in Ge exists when Ge contacts to metal, and thereby large Schottky Barrier (SB) in Ge MOSFET is inevitable, resulting in high contact resistance between metal and semiconductor. To tackle the technical challenge, Metal-Interlayer-Semiconductor (MIS) structure on the source/drain regions in Ge MOSFET is now being widely investigated. In this work, a new model for the MIS structure in Ge MOSFETs is suggested, to consider the effect of inserting heavily-doped interlayer (especially n⁺-ZnO) between metal and Ge in MIS structure.
In choosing a material for the interlayer of MIS structure, ZnO is singled out from various materials. Its property is not only Fermi-level unpinning but also lower tunneling resistance to Ge. However, there still exists another SB between metal and ZnO, which must have been another tunneling resistance in the MIS structure.
A new model for the MIS structure is proposed, which includes the doping effect of interlayer on contact resistivity. The doping concentration of interlayer is closely associated with tunneling probability of carriers in the MIS structure, so that Poisson equation is first solved in the proposed model. Then, the SB thickness between metal and heavily-doped ZnO is calculated, and the tunneling probability is obtained depending on the doping concentration in ZnO. With the model, the contact resistance in Ti / n⁺-ZnO / Ge structure is investigated. As compared to the contact resistance in Ti / undoped-ZnO / n-type Ge structure (i.e., ~2.1×10^-5Omega;-cm²), it is found that the heavily-doped (5×10¹⁹cm^-3) ZnO interlayer with 1.5nm thickness can achieve ultra-low contact resistance of ~6.1×10^-7Omega;-cm².
In the Ti / n⁺-ZnO / n-Ge MIS structure, the higher the doping concentration of the ZnO interlayer is, the sharper the energy band structure is. This causes a larger built-in voltage in the n⁺-ZnO, so that the conduction band of n-Ge at the interface between n⁺-ZnO and n-Ge is pulled down. This effect would lower the SB of n-Ge. In the MIS structure with n⁺-ZnO, however, the doping effect of the interlayer is not significant factor in estimating tunneling probability.
In summary, the doping effect of the interlayer on the contact resistance has been identified using a newly-proposed model for the MIS structure. The effect is primarily originated not from the improvement of tunneling probability but from the additional SB lowering of n-Ge. As a result, ~35× improvement in contact resistance has been achieved in the Ti / n⁺-ZnO / n-Ge, compared to Ti / undoped-ZnO / n-Ge. Hence, a heavily-doped interlayer insertion on the source/drain regions in Ge MOSFET is one of the promising ways to tackle the issue of ever-degenerating contact resistance.

The electrical reliability of high-k metal gate transistors is a growing concern as the nano-electronics industry moves to sub-10 nm dimensions and new 3D multi gate transistor technologies. In order to understand the various possible reliability failure mechanisms in high-k dielectric devices, knowledge of the band gap and defect states in high-k dielectrics is needed. However, experimental identification of both the chemical identity and energy level of the defects contributing to reliability issues in high-k materials has gone largely unreported in many cases. In this regard, we have utilized Reflection Electron Energy Loss Spectroscopy (REELS) to determine the band gap of numerous single crystalline and amorphous high-k dielectric materials. We demonstrate that for standard single crystalline materials such as Quartz, Al2O3, and TiO2 REELS band gap measurements agree with known values. For amorphous high-k thin film materials, we further demonstrate that REELS band gap measurements in most cases agree with optical measurements of the same materials. However, in some cases, we have observed that REELS analysis is complicated by the existence of defect states within the band gap of these materials. While troublesome for band gap measurements, we demonstrate that this sensitivity can be utilized to determine the energy level of various defects in pristine and sputter damaged high-k dielectrics and in some cases the chemical identity of the defect can be determined.

To determine energy band gaps of ultrathin gate oxides, the onset of energy loss signals of O1s photoelectrons has often been measured. However, for Hf-based oxides, it is imperative that Hf4s signals are subtracted accurately from the measured spectrum in the lower kinetic energy side of primary O1s photoelectrons to obtain true energy loss signals, and the O1s spectral analysis in consideration of a mixture of different chemical bonding features is also needed for the accurate calibration of the loss energy. Similarly, for Ge oxides, the overlapping of Ge LMM Auger signals and O1s energy loss signals makes it difficult to determine the onset of the true energy loss signals.
In this work, we have demonstrated that the energy loss spectra of core lines of cationic elements rather than O1s photoelectrons (Si2p3/2 for Hf-silicates and Ge3d5/2 for GeO2) are practically useful for energy band gap measurements. Also, the determination of the energy band alignment for a high-k dielectric stack on Ge(100), in which a ultrathin TaOx layer was inserted in between HfO2 and Ge(100) to control interfacial reactions, has been shown in combination of valence band offsets determined from the analysis of valence band spectra and energy band gaps from the analysis of energy loss spectra of core lines.

The disparate polarization at AlGaN/GaN heterostructures engenders a 2D electron gas (2DEG) that effectively reduces on-resistance and power loss, resulting in a high electron mobility ideal for high-frequency, high-temperature, and high-voltage requirements associated with HFETs and HEMTs. Since GaN and AlGaN are characterized by a large spontaneous polarization, there is a large polarization bound surface charge (2.2x1013 and 3.2x1013 charges/cm2) that must be compensated presumably by states near the dielectric-GaN or dielectric-AlGaN interface. While specific failure mechanisms have yet to be identified, it is clear that these states may play a role in gate leakage and current collapse. Recent efforts to improve performance of high power devices have focused on the role of a high-k dielectric as a gate oxide between the gate metal and AlGaN/GaN and as a surface passivation layer between the gate and source-drain contacts. The use of a specific dielectric requires a large band gap and band offsets that confine carriers in the semiconducting layers. Moreover, the concentration of the 2DEG is directly affected by the presence of interface states and defect states associated with the dielectric. In this research, we have employed remote plasma enhanced ALD (PEALD) and in-situ photoemission spectroscopy to prepare and characterize different dielectric layers on GaN and AlGaN surfaces. The in-situ x-ray and UV photoemission (XPS and UPS) measurements provide insight into the interface bonding, presence of impurities, band alignment, and band bending, which indicate the presence of defects. This report will concentrate on the properties of PEALD Al2O3 and HfO2 layers on AlGaN and GaN on both the Ga-face and N-face. Results establish that the band alignment is relatively independent of processing and may be described by the charge neutrality level model. In contrast, the band bending is dependent on processing and can be directly related to the presence of charged defect states at the interface and in the dielectric. The wet chemical and in-situ surface cleaning processes and the PEALD growth affect the band bending, resulting in similar band bending regardless of the surface polarization. This consistency indicates the presence of interface states that compensate the polarization charge on Ga- and N-face surfaces even though the polarization charge is opposite in sign and for GaN and AlGaN surface where the polarization charge increases by a factor of two. The interplay of polarization and the defect states and the 2DEG properties are discussed for the different dielectric layers and processing approaches.
Research is supported by ONR through DEFINE MURI.

Although Moore&’s Law scaling, the exponential increase in the number of CMOS transistors per unit area, continues unabated, computer clock speeds have been frozen since 2003 due to power constraints. We describe the materials underlying a new digital switch, the PiezoElectronic Transistor (PET) [1-2], which is designed to circumvent the speed and power limitations of the CMOS transistor. The PET operates on a novel principle: an electrical input is transduced into an acoustic pulse by a relaxor piezoelectric element (PE) which, in turn, is used to drive a continuous insulator-to-metal transition in a rare earth chalcogenide piezoresistive element (PR), thus switching on the device with high ON/OFF (~10^4) at low voltage (~100mV) - mechanical contact is continuous, distinguishing the concept from NEMs. Exceptional device performance is enabled by the use of two high performance materials, the relaxor piezoelectric and the rare earth chalcogenide piezoresistor - provided the materials exhibit nearly bulk properties at the nanoscale. The development of thin film piezoresistive and piezoelectric materials and associated characterization tools is presented, along with the theory and modeling designed to understand their behavior [3-4]. Lastly integration of these novel materials into 1st generation PET devices, and subsequent device characterization, are described [5].
1. “The piezoelectronic transistor: A nanoactuator-based post-CMOS digital switch with high speed and low power”, D.M. Newns, B.G. Elmegreen, X.-H. Liu, G.J. Martyna, MRS Bulletin 37, 1071 (2012).
2. “High Response Piezoelectric and Piezoresistive Materials for Fast, Low Voltage Switching: Simulation and Theory of Transduction Physics at the Nanometer-Scale”, D.M. Newns, B.G. Elmegreen, X.-H. Liu, G.J. Martyna, Adv. Mat. 24, 3672 (2012).
3. “Giant Piezoresistive On/Off Ratios in Rare-Earth Chalcogenide Thin Films Enabling Nanomechanical Switching”, M. Copel, M.A. Kuroda, G.J. Martyna, D.M. Newns et al, Nano Lett. 13, 4650 (2013).
4. “Electron transport in nano-scaled piezoelectronic devices”, Z. Jiang, M.A. Kuroda, D.M. Newns, G.J. Martyna et al, Appl. Phys. Lett. 102, 193501 (2013).
5. “Piezoelectronics - A New Low-Power Switch”, P.M. Solomon, B. Bryce, G.J. Martyna, D.M. Newns et al, in preparation.

Silicon Germanium (SiGe) is a well-known material for its high mobility and useful applications in strain engineering. Its advantages can be utilized to overcome the challenges when scaling down silicon-based devices. As the interest in introducing new kinds of materials increases, the cleaning and passivation methods also become more significant in order to provide uniform and clean surfaces, which would result in improved electrical properties such as high mobility and low interface trap density (Dit). In this study, combined wet and dry cleaning and passivation of SiGe(100) surface is discussed, using scanning tunneling microscopy (STM), scanning tunneling spectroscopy (STS), and x-ray photoelectron spectroscopy (XPS).
Wet cleaning using 2% hydrofluoric acid (HF) was implemented to strip the native oxide off the SiGe sample but left residual carbon contamination on the surface. By keeping the SiGe sample covered in the HF cleaning solution until the sample is introduced to the vacuum chamber or by transferring the sample in an inert environment all oxygen is eliminated from the surface. Dry in-situ atomic hydrogen cleaning was implemented to remove the carbon contamination on the surface. A post deposition anneal at 550C was used to obtain an atomically clean, flat, and ordered SiGe surface and this was verified using STM. The clean SiGe sample was dosed at room temperature with a saturation dose of H2O2(g). STM and XPS measurements indicate that H2O2(g) dosing leaves the SiGe surface, which is mostly Ge atoms due to surface segregation, terminated with an ordered monolayer of Ge-OH sites. STS measurements of the Ge-OH sites show the conduction band edge dangling bond states are eliminated due to the passivating Ge-OH bonds, but the Fermi level is pinned near the valence band edge due to the large surface dipole. When the surface is annealed to 310C, XPS measurements indicate that the -OH species on the surface break bonds with the Ge atom and bond instead to the Si atoms, raising Si atoms towards the surface. XPS also verifies that no oxygen leaves the surface due to the 310C anneal. Instead, the oxygen remains on the surface in the form on Si-OH or SiOx species. TMA is subsequently dosed on the surface forming and ordered monolayer of Al-O-Si bonds. STS indicates this unpins the Fermi level, leaving an electrically passive ordered layer which serves as an ideal template for further high-k ALD.

In_0.53Ga_0.47As is a leading candidate to serve as an n-channel material in future metal oxide semiconductor field effect transistors (MOSFETs). Metal/Al₂O₃/InGaAs MOS structures are at the center of attention as high mobility gate stacks. Al₂O₃/InGaAs gate stacks show the presence of fixed charges and traps (e.g. border traps) within the oxide layer, and trap states produced by defects at the Al₂O₃/InGaAs interface. Post oxide deposition annealing (POA) and post metal deposition annealing (PMA) can help in improving the quality of the Al₂O₃/InGaAs system by reducing the dielectric bulk traps and interface states, reducing the amount of bulk and interface #64257;xed charge in the Al₂O₃, and improving the Al₂O₃/InGaAs interface. In addition, soft x-ray exposure-induced damage of the dielectric during e-beam deposition can be removed during post metallization anneal.
In this work the effects of different annealing environments and different metal deposition methods on the effective work functions (EWF) in metal/Al₂O₃/InGaAs gate stacks and on the Al₂O₃/InGaAs interface were investigated.
Al₂O₃ was deposited by thermal atomic layer deposition (ALD) at 270°C using a standard trimethylaluminum/H₂O process on n-type InGaAs(100) substrates. The samples were then annealed at 400°C for 30 min either in vacuum (P<10^-7 Torr), or in 10%H₂/90% N₂ forming gas (FG), or in N₂. Different metal layers were deposited by electron beam or thermal evaporation through a shadow mask to be used as the gate metal. A second thermal annealing was performed after the gate metal deposition on the PMA samples. Various techniques including high resolution transmission electron microscopy, energy dispersive x-ray spectroscopy, and electrical measurements were utilized to analyze the MOS samples.
A difference of 0.3 eV was observed for the EWF values obtained on the same gate metals after vacuum POA compared to FG and N₂ POAs. The difference in the EWF extracted from C-V measurements was found to be in good agreement with the energy shifts measured by XPS on similar gate stacks. The difference in the EWF values is attributed to chemical bonds formed between indium and oxygen that carry a dipole due to the difference in electronegativity of the two atoms. These chemical bonds are formed during the FG or N₂ POAs but not during the vacuum POA.
A decrease in the #64257;xed charge density was observed after PMA for all metals studied. In addition, a significant shift in the EWF was found before and after annealing. This shift was larger in the case of electron beam evaporation of the metal electrode compared to thermal evaporation. The effect of POA and PMA on the EWF of various metals was correlated with the metal/Al₂O₃/InGaAs gate stack band alignment.

Moving towards future technology nodes for MOSFETs, new combinations of materials may be required in the metal gate/high-k dielectric gate stack. Producing and maintaining appropriate work functions (WFs) is a major issue. As the gate length decreases, WF variation becomes more significant. This is attributed to the different grain orientations, and hence different WFs, of the polycrystalline metal gate as the gate length approaches the grain size. Another problem arises due to metal-fill materials such as Al and W diffusing into or through the thin WF metal gate resulting in WF instability as well as reaction with the dielectric. A solution to these problems is the use of an amorphous metal gate. This eliminates the work function variation by eliminating the grains, as well as enables better work function control as an amorphous material serves as a better diffusion barrier than a polycrystalline metal gate.
In this work we investigate the possibility of making an amorphous metal gate based on a commonly used gate material, titanium nitride. An addition of appropriate extra element(s) often destroys the crystallinity of the material. For example, in our previous work thin film tantalum can be made amorphous with an addition of Si, C, and/or W. An amorphous TaWSiC film has a very high thermal stability, remaining amorphous up to an annealing temperature of 1120°C, as well as a good diffusion barrier property against copper diffusion. In an attempt to make a TiN-based amorphous gate, Co is added to TiN and the composition range of CoxTiyNz, from pure TiN to pure Co, is explored. While these films are grown using co-sputter deposition, we believe that the general results should apply to other deposition techniques such as ALD as well. XRD and XPS are used to study the phase, composition and bonding in the CoTiN films. From the results, we observe that with increasing amount of Co, TiN grains become smaller, with the TiN crystalline peaks broadening and peak intensities decreasing. We find that at above 50 at% of Co (Co50(TiN)50), the film becomes amorphous. Being amorphous, the CoTiN WF metal can be made thin while maintaining WF stability by blocking the indiffusion of Al or W fill material. With its low resistivity, cobalt also reduces the overall resistivity of the WF metal gate/metal fill stack. Furthermore, with cobalt&’s high WF, this opens up the possibility of WF tuning with composition.

To achieve high performance in future low power devices, a low threshold voltage, a high capacitance and a low leakage current are all of critical importance in CMOS technology. These electrical properties are strongly related to the interface of the dielectric layer and the semiconductor. Defects such as Dit and oxide charges are known as the main causes of the C-V curve distortion and influence the different I-V transport mechanisms.
In this research, we tailor the amount and type of defects in a gate oxide stack by systematically exploring different layered structures combining MgO and Al2O3 on silicon. The first series of samples are made of only two layers with different materials, thickness and sequence. The second set of samples are multilayer structures composed of MgO/Al2O3 pairs (up to 6) while keeping the total thickness the same.
MgO and Al2O3 were grown by MBE on p-type Si (100) wafers. The oxide films were deposited at 295 °C under an oxygen pressure of 1 x 10-5 mbar with an evaporation rate 0.1 Å/s. Total thickness was 6 nm for all samples. Forming gas annealing (FGA) at 450 °C for 15 minutes was performed on selected samples. RHEED was used to monitor the crystallinity. The film thickness was characterized by X-Ray Reflectivity. With Pt as top contacts the electrical properties were performed on 40 x 40 mu;m2 pads. Dit, EOT, flatband voltage (VFB) and oxide charges were extracted from C-V curves and conductance measurements. Frequency dispersion and I-V curves were also measured.
We find that in general, the bottom oxide layer - directly in contact with the Si - dominates the electrical properties. For Al2O3 bottom layer samples, lower EOT and smaller frequency dispersion are observed, whereas the VFB is larger due to negative oxide charges. The Dit of Al2O3 bottom layers is lower and the defect states are located closer to the midgap. In contrast for samples with a MgO bottom layer, a lower leakage and a lower VFB can be achieved. However, I-V shows soft breakdown under forward bias. In addition, for such samples with a bottom MgO layer, only the thinnest film (0.5 nm) shows a positive VFB shift, indicating a loss of passivation due to the large effect from the negative charges in the above Al2O3 layer. The Dif defect states of the MgO bottom layers are mainly located close to the valence band, and lead to an obvious frequency dispersion in the depletion region. The Dit of the multilayer structure is always higher than that of the single layer structure, which can be due to the higher amount of interfaces. The Dit can be reduced by one order of magnitude after FGA.
Because the effects of MgO and Al2O3 and their interfaces on the electrical properties are so different and complementary, our results demonstrate effective methods to modulate and fine tune the electrical properties of MOS gate stacks.

The CMOS device channel material for sub-10nm dimensions has been identified to be major challenge as per the ITRS roadmap. Among the options that are defined by ITRS roadmap is the high mobility III-V based channels. The overall goal of this research is to focus on new III-V materials that are capable of achieving nanometer scale transistors, in support of applications that can operate at 0.3-0.5 V. Our research is focusing on developing the Sb channel based FinFET devices. One of the key challenges is to develop an optimum metal contact to the III-V FinFET channel. In the first phase of this project we are focusing on Molybdenum/InGaAs contacts (moving to InGaSb channels later) to develop basic unit processes and characterization techniques. In this paper we are focusing on the interface characterization between the two layers and presenting our electrical and material assessment. This involves electrical measurements followed by detailed Mo/InGaAs interface studies using SEM and TEM techniques. The characterization process is focused on studying the effect of different fabrication processes and splits on the quality of the Molybdenum/InGaAs interface. To characterize this, Kelvin structures of Molybdenum over InGaAs were fabricated as test structures to measure the sheet resistivity and the contact resistance of the different sample. The starting material bilayer of the samples is InGaAs (150 Å) over InP (4000 Å), the fabrication sequence involves: the deposition of 30Å of Moly over the InGaAs layer, then patterning the Moly to form the nano TLM lines for kelvin test structures. The Moly lines in the test structures are patterned to a minimum contact length of 275nm. Then, an area of the InGaAS layer under the Moly lines is defined as an active layer (Mesa definition), the remaining area is etched by Chlorine based etch chemistry. In a final step, Pad areas are defined using lift-off of Titanium/Gold. In order to study the effect of various fabrication steps, different experimental processes are carried out. This includes the effect of different metal deposition techniques: sputter vs. e-beam evaporation. This is crossed with exposure to plasma damage and the use of “digital etch” to clean the channel to metal interface. The first set of baseline electrical and physical measurements was conducted by our collaborators [1]. Their first set of measurements indicate that the sputtered Mo gives a lower metal sheet resistance, 0.97 Omega;/sq and metal to pad contact resistance, 3.7×10-8 Omega;.cm2, compared to the evaporated Mo, 5.6 Omega;/sq and 4.1×10-8 Omega;.cm2, relatively. The samples with the various cleans just finished fabrication and electrical and TEM characterization are under way and will be reported in the meeting.
This research is funded by SRC MEESII project P14897.
Technical Collaborator: Prof. Jesus del Alamo, EECS, MIT, Boston, USA.
[1] A. Guo, “Nano-scale Metal Contacts for Future III-V CMOS,” M.S. thesis, Dept. Electrical Engineering, MIT., 2012

Narrow and short channel bulk Si nMOSFETs incorporated with p+ polysilicon ‘side-gate&’ structures around the Si body were fabricated using standard front and back end-of-line processing techniques and with SiO₂ dielectrics and shallow trench isolation (STI). The side-gate has an independent contact, and it is used to accumulate or deplete the Si body. The fabricated nFETs with narrow-channels (W_effective ~15 nm, L_effective ~27 nm) show excellent threshold voltage (V_T) sensitivity for side-gate bias (ΔV_T / ΔV_side > 1 V/V) while sustaining a good subthreshold slope. When side-gate is used to accumulate the body (V_side < 0 V), improvements in subthreshold slope and drain induced barrier lowering (DIBL) are also observed for a wide temperature range (80 K - 600 K).
Prior work included accumulated body nMOSFETs with Si₃N₄ side-gate dielectric and Si₃N₄ / Si_3+xN₄ stack as STI. The side-gate was n+ doped, showing significantly reduced off-currents and improved subthreshold characteristics for V_side < -1 V [1]. In this work, along with experimental demonstration of significantly narrower and shorter accumulated body MOSFETs with standard processing techniques and SiO₂ dielectrics, we also analyze the accumulated body phenomenon through 3D TCAD studies. Computational analysis involves the investigation of the effect of side-gate work function to accumulation of body, as well as the combined effect of the side-gate and substrate biasing.
[1] A. Gokirmak and S. Tiwari, "Accumulated body ultranarrow channel silicon transistor with extreme threshold voltage tunability " Appl. Phys. Lett., vol. 91, pp. 243504, 2007.

As conventional methods for scaling down have reached its limit, an alternative route has recently gained much attention: device performance improvement via channel strain engineering. The integral part of channel strain engineering is incorporating a stress-inducing structure into the transistor structure. For p-channel transistors, a widely adopted approach is growing epitaxial Si1minus;xGex layers in the source and drain (S/D) regions to introduce compressive strain in the Si channel. At sub-22nm nodes, fundamental change to transistor structure is required: from the 2D planar transistor structures to the 3D structures such as tri-gate transistor or FinFET structures. To apply the strain engineering to the FinFET structures, however, has limitations in increasing the channel strain to an extent large enough to significantly influence the hole mobility, and there is a lack of direct strain measurement method in such a nanoscale structures. Thus, we applied selective epitaxial growth (SEG) of SiGe layer around the S/D region, and the channel strain was measured by using nanobeam electron diffraction (NBD) method.
Epitaxial Si1-xGex layers with thickness of 25 and 45 nm were deposited on FinFET transistor arrays with 18, 36, and 54 nm fin widths. The microstructures of the films were investigated using a TEM. The spatial resolution of the NBD method was estimated to be around 2 nm. The resolution of the strain measurement was found within 0.1%. The fin structures of the TEM samples were fabricated along the fin direction and the cross sectional direction.
TEM and EDS results indicate that 30% SiGe epi-layer was successfully grown on S/D region of the fin structures. Channel strain profile obtained under the gate along the fin direction shows that after the SiGe layer deposition, there was a distinct increase in compressive strain along the [110] direction. In addition, TEM results of S/D region of FinFET structures indicates that different growth rate of SiGe layers on the top ({001} plane) and the sidewall ({110} plane) of the Si fin structures. The strain distribution in the [001] directions in the S/D regions reveals that the increase in transverse tensile strain within S/D region enhanced the longitudinal compressive strain in channel region with decreasing the fin width.
In summary, we investigated the strain distribution in Si fin structure with SiGe stressors. Our results showed that the epitaxially grown SiGe on S/D region induced the compressive channel strain effectively and NBD method can measure the strain variation in FinFET structures.

Doping - the purposeful introduction of impurities into a semiconductor material - is a key step in semiconductor processing. Controlled doping of semiconductor materials is becoming progressively more difficult as feature sizes are reduced.¹ Localised dopant profiles and sharp junctions are key for controlling electronic structure and nanoscale properties. At the nanoscale, the various existing doping technologies suffer from a number of drawbacks. Ion implantation, for example, is not compatible with one-dimensional materials and causes severe crystal lattice damage in addition to the problem of arbitrary dopant distribution.²
Monolayer doping (MLD), a technique developed by the Javey group ³ is a surface functionalisation technique, incorporating dopant atoms as part of self-assembled monolayers. The technique has the potential to overcome some of these drawbacks. MLD requires pristinely clean surfaces with suitable surface passivation and pure chemical precursors. Semiconductor/organic hybrids have become of considerable interest recently and there are many possible applications in devices.⁴
Presented is current work being carried out on routes to silicon surface functionalization using short-chain organic molecules as part of self-assembled monolayers both for passivation and doping purposes. Functionalisation was attempted using thermally-induced hydrosilylation and, for thermally unstable molecules, U.V-initiated hydrosilylation. Success of functionalisation and stability of the various monolayers under a variety of conditions was assessed using x-ray photoelectron spectroscopy and topography was monitored using atomic force microscopy.
References
1) Lundstrom, M. Science2003, 299, 210-1.
2) Jones, E. C.; Ishida, E. Mater. Sci. Eng. R Reports.1998, 24, 1-80.
3) Ho, J. C.; Yerushalmi, R.; Jacobson, Z. a; Fan, Z.; Alley, R. L.; Javey, A. Nat. Mater.2008, 7, 62-7.
4) Boettcher, S. W.; Warren, E. L.; Putnam, M. C.; Santori, E. A.; Turner-Evans, D.; Kelzenberg, M. D.; Walter, M. G.; McKone, J. R.; Brunschwig, B. S.; Atwater, H. A.; Lewis, N. S. J. Am. Chem. Soc.2011, 133, 1216-9.

The goal of this study is to determine whether strain can modify electronic structure of graphene and induce a reasonable bandgap in graphene with high mobility. We have studied changes in electronic properties of graphene transferred onto nanopillar structures with various heights that induce biaxial strain in the graphene sheet, using photoemission from C1s core levels and valance bands and NEXAFS absorption from the C1s to the graphene conduction bands.
Synchrotron photoemission from the C1s core levels of strained graphene was shifted by ~0.5eV to lower binding energy which indicates a change of electron density close to the carbon 1s electrons. Photoelectron spectra from the C1s electrons had a large shifted peak and a shoulder that appeared to be at the position of the C1s of graphene on a planar substrate. Thus, indicating that most of the graphene is strained. Synchrotron Near Edge X-Ray Absorption Spectra (NEXAFS) measures transitions from the C1s to the graphene π* and σ* orbitals. The π* are associated with the bottom of the conduction band, so changes of NEXAFS spectra indicate potential changes in the graphene conduction bands with strain. From the NEXAFS spectra, the transition from the C1s to π* orbital for strained graphene was reduced by approximately a factor of three from that of the unstrained graphene and there appeared to be subtle changes in the shape of the XAS. Furthermore, the peak of the π* absorption appeared to be narrower for the strained graphene than the unstrained graphene. In contrast to the π*, the absorption of the σ* appeared to have the same magnitude for strained and unstrained graphene. These results indicate that the conduction band of strained graphene is being changed by the strain. Ultraviolet Photoemission Spectra from strained appeared to have higher relative photoemission than that from unstrained graphene. A surprising observation that needs to be verified is that the photoemission from the SiO2 valence band with strained graphene appeared to be shifted from that on unstrained graphene.
Thus, preliminary results indicate strain induces changes in the graphene conduction band orbitals (π*) which could result in changes of graphene electron mobility; however, this needs to be electrically verified. Changes in the C1s photoemission indicate that strain changes the electron density close to the C1s electrons which potentially indicates a change in π electron density and there may be changes in the valence bands. This requires determining the precise location of the graphene valence band edge and the Fermi level.
Additional experiments are planned to examine the core level photoemission, NEXAFS, and more detailed studies of photoemission from the graphene valence band.

Topological insulators are a new class of materials with a special property that is likely to prove useful in spintronics: the ability to carry spin-polarized currents on their surfaces. The coupling strength between nuclei and electrons of a topological insulator material is an important value to measure because nuclear magnetism could cause the spin-polarized electrons to scatter and move out of phase during the transports, thereby affecting the transport of spin if the surfaces are used for a spintronic device. Nuclear magnetic resonance (NMR) measurements can probe the hyperfine coupling between specific isotopes and the electronic system of a material. We present ²⁰⁹Bi NMR spectra and relaxation rate data on single crystals and powder samples of the topological insulator material Bi₂Se₃ grown under various conditions. Our NMR data on single crystals reveal a significant hyperfine coupling strength between the nuclei and the bulk carriers, suggesting that nuclear spins may have a sizeable effect on spin-polarized surface currents. We then demonstrate attempts to obtain the nuclear coupling with the surface state in Bi₂Se₃ by performing measurements on powder samples, which have a much greater surface to volume ratio than do single crystals and should reveal surface states. We find that further basic research is invaluable to discerning the hyperfine interactions between the surface states and ²⁰⁹Bi nuclei.

This study demonstrates the remarkable role of natural defects in the MoS2 on the electrical characteristics of metal contacts. The presence of low work-function metallic defects at the interface of a deposited metal/MoS2 contact results in the formation of an inhomogeneous junction where the resultant current is due to parallel contacts of metal defect/MoS2 and deposited metal/MoS2. The work function and areal density of each play a role in determining the resultant junction current and it is found that even defect densities as low as 0.3% can dominant the overall Schottky barrier when high workfunction metals are deposited. The presence of these defects is verified using scanning tunneling microscopy. Simulated I-V characteristics show that the experimentally observed trends can be explained by the variations in deposited metal work functions and also variations in metallic defect density. This phenomenon explains the previously poorly understood Fermi level pinning observed for high workfunction metals on MoS2.(1)
The properties of the deposited metal/MoS2 portion of the junction are more easily studied by photoelectron spectroscopy, where the contribution of each signal is linearly dependent on areal concentration and so is dominated by the deposited metal/MoS2 signal rather than the metal defect/MoS2. A range of metals are deposited in situ and the reactions or lack there-of are presented and discussed. It is found that low workfunction metals such as Cr and Ti chemically react with the MoS2 forming new compounds at the interface. Despite some electronic overlap at that interface, which can be monitored by Raman spectroscopy, the deposition of high workfunction metals such as Pd and Au results in no detectable chemical interactions. The metal workfunctions are characterized using ultra-violet photoelectron spectroscopy and the band bending at the interface is monitored by x-ray photoelectron spectroscopy. The thermal stability of these interfaces are also examined.
This work was supported in part by the Southwest Academy on Nanoelectronics sponsored by the Nanoelectronic Research Initiative and also by the Center for Low Energy Systems Technology (LEAST), one of six centers supported by the STARnet phase of the Focus Center Research Program (FCRP), a Semiconductor Research Corporation program sponsored by MARCO and DARPA.
1 Das, S., Chen, H.-Y., Penumatcha, A. V. & Appenzeller, J. High Performance Multi-layer MoS2 Transistors with Scandium Contacts. Nano Lett, 100-105 (2012).

We designed a series of experiments using scanning tunneling microscopy and spectroscopy (STM and STS), X-ray photoelectron spectroscopy (XPS) and Schottky diode measurements to show that reliable interpretation of electrical data requires a consistent selection of identical areas. The photoemission study shows detectable variations in the core level spectra across the same MoS2 sample. Explicitly, a low binding energy shoulder on the Mo 3d core level is observed. Also, the stoichiometry MoSx (1.7le;xle;2.3) changes dramatically between regions. The Schottky diode measurements show that are large percentage of regions exhibit a p-type behavior. Additional STM and STS experiments are performed to understand the origin of the observed conductivity. The STM images registered on the pristine MoS2(0001) surface show the presence of two distinct defects, both are very similar to those generated by Ar+ sputtering of MoS2 [1]. The defect density changes across the same surface generating a variation in the electronic signature measured by STS. We established a precise correlation in the observed MoS2 variability between I-V, STM/STS, and XPS measurements. The regions with low defect density act as expected n-type conductivity due to sulfur vacancies. However, the regions with high defect density reveal a p-type behavior concurrent with the detection of additional component in the Mo 3d core level and high ratio S/Mo. Consequently, device performance will be significantly affected by the concentration of these defects. This finding suggests that natural MoS2 is not of sufficient quality for reliable device studies and the synthesis of controllable and high quality TMD substrates must be synthetized in order to provide low-defect and large-area TMDs.
This work was supported by the Southwest Academy on Nanoelectronics center sponsored by the Nanoelectronic Research Initiative.
[1] A. Inoue et al. “Atomic-scale structures and electronic states of defects on Ar+-ion irradiated MoS2”, J. Electron Spectrosc. Relat. Phenom. (2013), http://dx.doi.org/10.1016/j.elspec.2012.12.005.

Portable electronics, such as a smart phone and a tablet PC, have been rapidly developed. For this reason, demand for high-performance NAND flash memory are increased dramatically. As the cell size is scaled down for high density, however, reliability issues like endurance and retention have been occurred frequently, especially under 20-nm technology node. In this work, we studied post metallization annealing (PMA) condition with varying PMA temperature and process time to overcome these obstacles. The threshold voltage (Vth) distribution analysis of cells, junction leakage current and DC-IV measurement are used for verifying the reliability characteristics of NAND flash memory.[1] These results indicate that the higher temperature and the longer time during PMA process reduce the moisture in the ILD/ IMD layer [2]. With this optimization, better reliability properties can be achieved for high-end NAND Flash memory devices.
References
[1] Arnost Neugroschel et al., IEEE Trans. Electron Devices, vol. 42, no. 9, pp. 1657-1662, Sep. 1995.
[2] Zih-Song Wand et al., IEEE Trans. Electron Devices, vol. 60, no. 1, pp. 254-924, Jan. 2013.

We demonstrate a redox-based resistive switch exploiting the formation of conductive filaments in bulk silicon-rich silicon oxide.
Our devices exhibit multi-level switching and analogue modulation of resistance as well as standard two-level switching. We demonstrate different operational modes (bipolar and unipolar switching modes) that make it possible to dynamically adjust device properties, in particular two highly desirable properties: non-linearity and self-rectification. Scanning tunnelling microscopy (STM), atomic force microscopy (AFM), and conductive atomic force microscopy (C-AFM) measurements provide a more detailed insight into both the location and the dimensions of the conductive filaments. We discuss aspects of conduction and switching mechanisms and propose a physical model of resistive switching. We demonstrate room temperature quantisation of conductance in silicon oxide resistive switches, implying ballistic transport of electrons through a quantum constriction, associated with an individual silicon filament in the SiOx bulk.

Two dimensional (2D) MoS2, a transition metal dichalcogenide, has been considered as potential channel material for field effect transistor (FET) applications. For example, a multilayer MoS2-based FET was reported to have reasonably high electron motilities on the order of 470 cm2/Vs, where the field effect mobility values showed a dependence on the dielectric environment of the channel [1]. Despite the promising progress, a better understanding of the 2D material-dielectric interface is still needed, in parallel with the development of deposition processes for high quality and uniform high-k dielectrics on the 2D material inert surfaces.
Recently, it has been reported that the lack of dangling bonds on MoS2 surface will cause island growth for HfO2 film deposited by atomic layer deposition (ALD), whereas the presence of contaminants on the MoS2 surface will impact the nucleation process [2]. This suggests that surface treatments are needed in order to obtain continuous and uniform dielectric films.
In this work, an in situ study of UV-O3 treatment on bulk MoS2 as a route to generate an oxygen-functionalized MoS2 surface will be presented. By using X-ray Photoelectron Spectroscopy (XPS), the thermal stability of the covalently bonded oxygen will be monitored. In addition, it will be shown that due to the creation of nucleation sites for ALD on the oxygen-functionalized MoS2 surface, uniform Al2O3 thin films of ~ 3 nm in thickness can be obtained. Finally, the ALD temperature dependence on the uniformity of Al2O3 thin films studied by Atomic Force Microscopy and Transmission Electron Microscopy will be presented.
This work was supported in part by the Center for Low Energy Systems Technology (LEAST), one of the six SRC STARnet Centers, sponsored by MARCO and DARPA.
[1] Bao, W. et al. Applied Physics Letters 102, 042104 (2013)
[2] McDonnell, et al. ACS Nano Article ASAP (2013). DOI: 10.1021/nn404775u

As the size of microelectronic structures scale to smaller dimensions, new materials are required to maintain device functionality. Specifically, for the transistor industry, an essential quantity for device performance is the thickness of the gate component which plays a crucial role in determining the drive current. However, current leakage becomes increasingly prevalent with thinner gates - a problem that can be overcome by increasing the dielectric constant of the gate material. Although silicon dioxide (SiO2) has been the material of choice for years, it becomes unsuitable for the desired device performance due to its relatively low dielectric constant (k = 3.9). Alternate materials, such as BN:H (dielectric constant ~5.5) and HfO2 (dielectric constant ~25) possess higher k values and are thus promising choices to replace SiO2. These high-k dielectrics can be used to achieve the desired drive current while preserving the ultra-thin thickness (<10 nm) necessary for miniaturization and minimizing leakage currents. Despite these promising features, one concern of including these thin functional materials, are their mechanical and thermal properties that could result in a degradation of device functionality. These dimensions present serious challenges to traditional methods such as nano-indentation to evaluate the mechanical properties of these layers, and thus, there is a growing need for non-destructive responsive techniques to determine the Young&’s modulus (E) and Poisson&’s ratio (nu;) of such critical laminar components in emerging electronic devices. We report on Brillioun light scattering studies to determine the individual elastic constants and, thus the mechanical properties of BN:H and HfO2 high-k films with thicknesses as low as 24 nm. The values of E and nu; of these materials grown on Si were determined by measuring the frequency dispersion of confined and traveling transverse and longitudinal acoustic waves as well as their associated light scattering intensities. The findings will also be discussed in the context strain that may result from these layers being embedded in functional device configurations.

The current approach towards density scaling metal-insulator-metal (MIM) devices is to replace the conventional silicon dioxide (SiO₂) or silicon nitride (Si₃N₄) films by alternative high-k stacked charge storage layers to achieve higher capacitance density (> 20 fF/mu;m²), reduced feature size (4f² cell size, where 4 is a design factor and f, the half-pitch in microns), low standby power (~ 10^-8 A/cm² at 1V) at access transistor and storage capacitor, and stable sensing (i.e., good contrast in logic levels). The MIM stacked capacitors are of great technological interest as they find extensive applications such as radio frequency (RF) coupling and bypass capacitors in oscillators and resonator circuits, filter and analog capacitors in analog/mixed-signal (AMS) circuits, decoupling capacitors for microprocessors (MPUs) as well as storage capacitors in dynamic random access memory (DRAM) and embedded DRAM (eDRAM)/logic devices. We report characteristics of planar MIM mono-dielectric layer stacks fabricated using pulsed laser deposited ultra thin films of the new linear high-k dielectric material LaGdO₃ developed in our laboratory. These stacks showed high capacitance density ~ 43.5 fF/mu;m² with sub-nanometer capacitance equivalent thicknesses of ~ 0.66 nm, large breakdown field of ~ 6 MV/cm, greater energy storage density of ~ 40 J/cm³, smaller voltage coefficient of capacitance, and lower dependence of it on layer thickness α prop; d^-1 and frequency. All these features make LaGdO₃ a material of interest for next generation MIM structures for radio frequency, analog/mixed-signal, and dynamic random access memory applications.

CBRAMs (Conductive Bridging Random Access Memories) are one of the most promising emerging new technologies for next generation of non-volatile memory. These resistive memories can be fabricated using an Ag-Ge-S glass sandwiched between two electrodes: an Ag anode and an inert cathode. The 0 and 1 levels are associated to the resistivity difference between two conductive states due to the diffusion of Ag+ ions in the chalcogenide glass but the exact switching mechanism remains not fully understood. It is expected that, under the influence of an electric field, Ag ions are produced at the anode and migrate in the electrolyte to form a conducting path [1]. This process is reversible by applying a bias with opposite polarity and the formation and removal of the conductive pathway can be used for information storage. Although the physical properties of bulk Ag-Ge-S glasses have been well characterized for different glassy systems, these characterizations on thin films (50 nm thick) are scarce and the fundamental mechanisms of the ionic transport process are not yet fully understood from a microscopic point of view.
Recently, the analysis of the chemical environment of the Ge, S and Ag atoms in Ag-doped GeSx (1.6 In this presentation, CBRAMs devices have been analyzed by XAS in the hard X-ray regime (Ag-K edge) combining bulk- and surface- sensitive datasets via the use of the X-ray total reflection technique. In order to study the local order of the Ag+ ions involved in the resistive switching process, test devices have been prepared by magnetron sputtering deposition. The devices consist in a 25 nm thick W bottom electrode layer on a 200 mm Si substrate and a GeSx chalcogenide electrolyte (50 nm thick) covered with a 2*80 mm top Ag electrode layer (20 nm thick). These large area devices have been designed in order to perform the XAS measurements in grazing incidence mode to increase the fraction of material to be analyzed. Then the devices have been electrically tested in order to simulate a CBRAM device in its different states (typically electrically switched or not). Finally, before XAS analysis, the top Ag anode of the CBRAMs devices has been removed by Ion Beam Etching. Samples before and after cycles of SET/RESET are presented and the obtained results will allow answering to many questions related to the Ag+ diffusion phenomena in Ag-Ge-S thin films used in CBRAM devices.
[1] I. Valov et al., Nanotechnology 22, 254003 (2011).
[2] Deok-Yong Cho et al., Adv. Mater. 24, 4552-4556 (2012).