The tutorial will provide a broad-based overview of the physics, materials science and engineering aspects of ferroelectricity for enabling advanced and nanometer-scale microelectronic applications. It will feature four lectures -  two of which will discuss experimental aspects and two focusing on theory and simulations, covering both memory technology and the negative capacitance.

The lecture series will start with Paul McIntyre, Stanford University, who will introduce the atomic layer deposition (ALD) technique for the growth of nanolaminate and alloyed variants of semiconductor process compatible materials such hafnium oxide that exhibit ferroelectricity, the role of microscopic features such as polar structural domains and interfaces on the reliability and iniaturizability/scalability of ferroelectric memories, and metrology techniques for probing such microstructural features.  Continuing the discussion, Sven Beyer, GLOBALFOUNDRIES, will discuss the current state-of-the-art of ferroelectric field-effect transistors fabricated in the advanced semiconductor technology facilities and sketch a potential roadmap for ferroelectric memories--as seen from an industry perspective.  Jorge Íñiguez, Luxembourg Institute of Science and Technology, will shift the focus from memory applications to ferroelectric negative capacitance effects and will describe current theoretical understanding of this phenomenon. Finally, Kai Ni, Rochester Institute of Technology, will discuss the potential of ferroelectric devices for extreme miniaturization based on modeling and simulation studies.

Atomic Layer Deposition of Ferroelectrics Based on HfPO2—Polycrystallinity, Polar Domains and Interfaces
Paul C. McIntyre, Stanford University

This tutorial will start with a general introduction to the atomic layer deposition (ALD) technique for industrial applications, the use of super-cycle ALD for fluorite structure oxides such as hafnium oxide and their nanolaminate and alloyed variants, and ferroelectricity therein. Afterwards, the main focus will be on microscopic aspects of such nanoscale, polycrystalline ferroelectrics for memory applications. Memory write and read operations require local reorientation and sensing of polar crystallographic domains, respectively. We will discuss the impact of such structural aspects on the miniaturization of the memory devices, physical principles relevant to polar domains, and methods for characterizing nanoscale domain structure in order to obtain a local picture for interpreting electrical data measured from ferroelectric memories. Lastly, we will elucidate the role of the interface layer structure, polarization charge screening, interface states and fixed charges on the performance and reliability of ferroelectric field-effect transistor based memories.

Ferroelectric Field-Effect Transistors for 28nm Node and Beyond
Sven Beyer, Global Foundries

With the discovery of ferroelectricity in HfO2 based thin films 2011 and the co-integration of ferroelectric field effect transistors (FeFET) into standard high-k metal gate (HKMG) CMOS platforms 2016/17 by GLOBALFOUNDRIES,  the FeFET has emerged from a theoretical dream to an applicable reality. Maturing in the beginning as a low-cost, low power eFLASH replacement, the FeFET yet is much more than a classical stiff eNVM cell. With its great HKMG CMOS compatibility, its flexibility and its unique switching properties, it is rather to be seen as a new versatile device that promises to open up new worlds. Especially the neuromorphic design community has shifted focus towards this novel device with game-changing potential. In this talk we will discuss the actual status of GLOBALFOUNDRIES  FeFET technology, look into the operation and use of this device and sketch a potential roadmap.

Ferroelectric Negative Capacitance
Jorge Íñiguez, Luxembourg Institute of Science and Technology

We will discuss the effect known as “negative capacitance”, whereby some ferroelectric materials display an anomalous dielectric response (a negative permittivity) when subject to suitable electric boundary conditions. We will describe our current theoretical understanding, from both phenomenological and atomistic perspectives, drawing a clear distinction between equilibrium and transient negative-capacitance responses. We will also review the experimental evidence for both flavors of negative capacitance, and briefly present its expected technological applications (most notably in field-effect transistors, because of the concomitant “voltage amplification”). Finally, we will give our view of the current challenges and opportunities in the field.

Numerical Models for Ferroelectric Memory Devices
Kai Ni, Rochester Institute of Technology

Ferroelectric memories based on the doped HfO2 ferroelectric, including capacitor based 1T1C FeRAM and transistor based 1T FeFET, have received significant interests recently. The excellent scalability and CMOS compatibility of ferroelectric HfO2 has allowed its integration into 2x technology node. Such scaling reveals novel physical phenomena not observed before in perovskite ferroelectric devices, such as degraded device variation with scaling, switching stochasticity, switching probability accumulation. In order to understand such phenomena and exploit them for novel energy efficient computation, accurate device models would be indispensable. In this lecture, we will present ferroelectric memory models developed so far, covering computationally efficient compact models, Monte Carlo models, and computationally intensive phase field models. By comparing with experimental data, the application range of each model will be identified and the potential for scaling/miniaturization of ferroelectric devices will be discussed.