Revolutionizing Wafer Reusability: Innovative Porosification Techniques for Multiple Layer Transfers in Indium Phosphide

In pursuit of sustainable and cost-effective semiconductor manufacturing, we present ground-breaking porosification techniques tailored for multiple layer transfers in Indium Phosphide (InP) wafers, with the ultimate goal of achieving complete wafer reusability.<br/>Indium phosphide (InP) layers have wide range applications in various optoelectronic devices, such as solar cells, light-emitting diodes (LEDs), and high-speed transistors. In most of these applications, only a layer thickness in the order of 10 μm is typically needed. The main materials and device processing standard in industry for such layers are epitaxial growth techniques (MBE, MOCVD, etc), ion cut (Smart Cut ®) and chemical mechanical polishing (CMP) after a wafer bonding process. Smart Cut ® and CMP both require complex and expensive preparation steps to achieve surfaces suitable for bonding. Epitaxy (heteroepitaxy) on the other hand has a difficulty in producing layers with high crystalline quality especially when there is a high lattice mismatch.<br/>An attractive material processing alternative to these techniques is the use of electrochemical methods to grow pores with tuneable properties (pore morphologies, depths, and diameters) into the InP wafer. Such pore tunability means that at a certain desired pore depth, pore diameters can be enlarged to create a continuous cavity that can then be detached as one intact layer from the parent wafer. The parent wafer can then be recycled completely in subsequent runs. This technique provides a fast, inexpensive and simple way to transfer porous InP layers particularly in optoelectronic applications where porosity in the InP layer is an added benefit. Additionally, hetero-integration with such layers is similar to the unetched InP wafers since the entire wafer surface can be transferred.<br/>With the aid of a special etching profile invented by us, different types of pores can be grown into InP wafers, characterised as crysto-, curro- or mixed-pores using advanced characterisation techniques. It is crucial to have precise control of these pore growth kinetics in order to achieve a high device yield and to ensure reproducibility. This presents a challenge since electrochemical systems are complex systems containing many variables such as global and local doping differences, temperature fluctuations, heat generation and release, concentration fluctuations, surface conditions, back side contacts, etc. In these cases, quantitative approaches to estimate pore growth dynamics in semiconductor materials can be the key to producing well defined porous layers. This quantitative description of the growth kinetics is presented. The power of such a quantitative approach is that AI-driven models can be trained on this data that can then forecast pore growth dynamics in semiconductor materials, facilitating the tunability of porosity for specific applications and enhancing the reproducibility of porous layers.<br/>Keywords: Indium Phosphide (InP), Hetero-integration, Doping Concentration, Advanced Characterisation Techniques, Materials Processing, Device Processing, Porous Structures