Aditya Varma1,Nirmaan Shanker1,Suraj Cheema1,Mohamed Mohamed2,Sayeef Salahuddin1,3
University of California, Berkeley1,Massachusetts Institute of Technology2,Lawrence Berkeley National Laboratory3
Aditya Varma1,Nirmaan Shanker1,Suraj Cheema1,Mohamed Mohamed2,Sayeef Salahuddin1,3
University of California, Berkeley1,Massachusetts Institute of Technology2,Lawrence Berkeley National Laboratory3
Cryogenic CMOS, where CMOS systems operate at liquid nitrogen temperatures, is an attractive option to reduce the energy consumption of computing as the operating voltage can be aggressively scaled due to lower subthreshold swing in transistors [1]. To realize this, several performance boosters are required, including increasing the gate capacitance of transistors without degradation in carrier transport. We have previously demonstrated a 1.8-nm ferroelectric-antiferroelectric HfO<sub>2</sub>-ZrO<sub>2 </sub>superlattice (HZH) gate stack boasting a capacitance enhancement over the 8 Å SiO<sub>2</sub> IL layer [2] via the NC effect [3] and have successfully integrated it into a 90 nm US Defense CMOS R&D technology [4]. Additionally, since no SiO<sub>2</sub> interfacial layer (IL) scavenging was performed, the carrier transport is not affected, resulting in a significant increase in on-current and intrinsic transconductance at room temperature [2, 4].<br/>In this work, we characterize 90-nm L<sub>g</sub> nMOS and pMOS transistors integrating the NC HZH gate stack down to 77 K. From cryogenic RF characterization, we observe that the capacitance enhancement is maintained, suggesting that the mixed ferroelectric-antiferroelectric structure is stable at 77 K. Additionally, due to enhanced injection velocity at cryogenic temperatures, we observe 35% and 25% improvement in transconductance for nMOS and pMOS devices, respectively, at 77 K. Overall, this work confirms that NC is stabilized in the HZH gate stack down to cryogenic temperatures and can be an attractive option to realize cryo-CMOS systems.<br/>[1] S. Datta <i>et al.</i> “Toward attojoule switching energy in logic transistors.” <i>Science</i> 378, 733 (2022).<br/>[2] S Cheema <i>et al</i>. “Ultrathin ferroic HfO<sub>2</sub>–ZrO<sub>2</sub> superlattice gate stack for advanced transistors.” <i>Nature </i>604, 65 (2022).<br/>[3] S Salahuddin & S Datta. “Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices." <i>Nano Lett</i>. 8, 405–410<br/>[4] N Shanker <i>et al</i>. “CMOS Demonstration of Negative Capacitance HfO<sub>2</sub>-ZrO<sub>2</sub> Superlattice Gate Stack in a Self-Aligned, Replacement Gate Process.” in <i>2022 International Electron Devices Meeting </i>(IEEE, 2022).