Simon Jeannot1
STMicroelectronics1
Back end of the Line embedded Non Volatile Memories for Microcontrollers: constraints and opportunities.<br/>S. Jeannot , J. Sandrini , E. Petroni # , O. Weber ,A. Conte +, A. Redaelli # , L. Laurin #, R. Ranica, F. Arnaud, , J. Devin *, C. Boccaccio.<br/>STMicroelectronics Crolles France, #Agrate-Brianza Italy, *Rousset France, + Catania Italy. Email:
[email protected]<br/>Embedded non-volatile memories (eNVMs) are an essential component of modern microelectronics technologies, providing a reliable and cost-effective solution for storing critical data and program code in a wide range of applications. Microcontrollers, in particular, have shown a regular increase of their market, overpassing 20 Billions dollar by year with two digits growth in the last period. They benefit from the persuasion of microelectronics intelligent products in modern life, from the automotive and industrial sector, smartcards, to the communication grid and global interconnection growing needs. From a technological point of view, Mature Floating Gates technologies are progressively replaced by new back end of the line solutions, more compliant with High K / metal technology and density increase constraints. Spin Torque Transfer Magnetic Random Access Memories (STT MRAM), Oxide Based resistive Memories (OXRAM) as well as Phase change Memories (PCM) have been introduced in the last years and are nowadays qualified in production on different nodes by majors players. Different physics and architecture involved might lead to different memory characteristics and products best suited for each technology.<br/>Developing memories for embedded microcontrollers requires to sustain very aggressive mission profiles for memory reliability, and its introduction in the Back end of integrated circuits adds up important technology limitations. In this presentation the author will describe the constraint of eNVM for microcontrollers, both from the application and the integration side. A comparison of the different BEOL memories technologies will be done in regard to device level performance and architecture, reliability mission profiles, memory point architecture versus integration, and technology cost. A special emphasis will be applied on ePCM technology, with description of device, process flow and materials optimization involved to fulfill aggressive product requirement with competitive solutions. Lastly, emerging memory solutions for storage memories as well as working memories in “In Memory Computing” approach will be discussed, highlighting the main challenges for each competitor (FeRAM, FeFET, OTS, RERAM).