Exploring Architectural Innovations with Ferroelectronics

Data generated over social media, biomedical monitoring, and the Internet-of-Things is increasing exponentially. The ability to extract useful information from this big data is critical towards advances in varied domains. The enormity of the data is outstripping the ability for electronic systems to process, communicate and store the data that is being generated. While historically transistor scaling helped address the growth in computational needs, with scaling now reaching its limits, new approaches are needed. To this end, this work envisions a new ferroelectric-based platform that can provide unprecedented opportunities to scale chip designs in the third dimension, to blur the gap between memory and logic functionality through seamless integration and novel beyond Von Neumann architectures to accelerate big data analytics.<br/><br/>Ferroelectric devices leverage the ability of an electric field to induce reversible polarization. This polarization provides a state representation of digital design. The discovery of ferroelectricity in doped hafnia, reported in 2011, has had a transformative Impact on ferroelectric driven semiconductor platforms. As hafnia is integral to advanced CMOS nodes, the prospect of rapid integration of ferroelectric elements in advanced CMOS process nodes is promising. The integration of a ferroelectric material in the gate stack of a CMOS device enables another desirable feature, that of a logic compatible, compact single device memory primitive. This capability allows fine-grain integration of logic and memory, enabling processing in memory and reducing overheads of data movement. These prospects have fueled ferroelectric innovations from new materials to novel architectures. This work will emphasize the need for co-design of materials, devices and circuits informed by architectural and application needs.<br/><br/>By utilizing distinct properties of ferroelectric devices such as Ferroelectric Tunnel Junction (FTJ) and Ferroelectric Field-Effect Transistor (FeFET), system-level benefits for different metrics such as performance, power, area or security will be discussed. An example of that is an FeFET-based active interconnect that supports hardware functional obfuscation by utilizing the threshold voltage programmability of the FeFET. Another example is a FeFET 1T NOR array. FeFET 1T NOR array has many potential applications: routing switches for field-programmable gate array (FPGA), weight cells in a crossbar array to accelerate multiplication-accumulation computations in machine learning accelerators, and interaction controllers between artificial spins in Ising machines. We will discuss challenges in efficient write mechanisms in such NOR arrays.