Enhanced Robustness of Atomic Precision Devices under Accelerated Lifetime Testing

As transistor features move towards the atomic scale, the ability to study and design for atomic scale effects become critical for next-generation microelectronics. Atomic precision advanced manufacturing (APAM) of electrical devices, fabricated using hydrogen depassivation lithography in a scanning tunneling microscope (STM), offers a way to explore atomic scale physics with the ultimate degree of control. While almost all previous APAM work has focused on exploring applications in quantum physics, particularly with a focus on qubits, we have recently demonstrated successful integration of microelectronic-focused APAM devices within Sandia’s 0.35-micron CMOS node [1]. However, demonstration of the compatibility of APAM material with CMOS at relevant operational temperatures and device drive current conditions is lacking.<br/><br/>To establish APAM + CMOS operational compatibility, we performed accelerated lifetime testing of both standard photolithographically patterned APAM delta layer devices (&gt;5 μm width) as well as STM patterned APAM devices (&lt;1 μm width). Variable width devices allow for testing at higher current densities along with connecting robustness results to a wide range of different application spaces (transistor channel, interconnect material, etc.). Analysis of the APAM devices shows that all but one device survived for several weeks at 300 °C at high current densities (minimum of 2.5 MA/cm²) while all three implanted phosphorus samples failed under the same conditions [2]. Further characterization demonstrated that the failure mechanism was a result of the metal bond-wire interconnects used to package the devices, and not the APAM devices themselves. Modeling using Sandia’s open-source TCAD code Charon validates that the current flow is tightly confined around the delta layer, resulting in an estimate of current density of &gt;8 MA/cm², almost 10x higher than copper (~1 MA/cm² at 300 °C). Demonstration of the robustness of APAM devices relative to wire-bonds used to make device contacts coupled with the previous demonstration of APAM’s integrability [1] with a CMOS process opens the door for utilizing APAM to enhance CMOS transistors along with providing wider manufacturing interest.<br/><br/>This work was supported by the Laboratory Directed Research and Development Program at Sandia National Laboratories and was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE, Office of Basic Energy Sciences user facility. SNL is managed and operated by NTESS under DOE NNSA contract DE-NA0003525<i>.</i> The views expressed in the article do not necessarily represent the views of the DOE or the U.S. Government.<br/><br/>[1] Leenheer, A.; Halsey, C.; Ward, D.; Campbell, D.; Mincey, J. S.; Anderson, E. M.; Schmucker, S. W.; Ivie, J. A.; Scrymgeour, D.; Gao, X.; Lepkowski, W.; Misra, S. <i>ECS Meeting Abstracts </i><b>2021,</b> MA2021-02, (30), 918-918.<br/><br/>[2] Halsey, C.; Depoy, J.; Campbell, D. M.; Ward, D. R.; Anderson, E. M.; Schmucker, S. W.; Ivie, J. A.; Gao, X.; Scrymgeour, D. A.; Misra, S. <i>IEEE Transactions on Device and Materials Reliability </i><b>2022,</b> 22, (2), 169-174