MRS Meetings and Events

 

EL11.04/EL14.06.02 2023 MRS Fall Meeting

MOSFETs on (111) Highly Oriented Polycrystalline 1-Inch Diamond Substrate

When and Where

Nov 28, 2023
10:45am - 11:00am

Hynes, Level 2, Room 210

Presenter

Co-Author(s)

Yukihiro Chou1,Fuga Asai1,Kosuke Ota1,Atsushi Hiraiwa1,Yoshiki Nishibayashi2,Hiroshi Kawarada1

Waseda University1,Sumitomo Electric Industries, Ltd.2

Abstract

Yukihiro Chou1,Fuga Asai1,Kosuke Ota1,Atsushi Hiraiwa1,Yoshiki Nishibayashi2,Hiroshi Kawarada1

Waseda University1,Sumitomo Electric Industries, Ltd.2
We fabricated 2DHG diamond MOSFETs on a (111) highly oriented polycrystalline 1-inch diamond substrate and confirmed that the devices correctly functioned as a FET. The area of the 1-inch substrate is about 55 times larger than that of conventional 3mm square substrate. In this work, we fabricated 220 devices on the 1-inch diamond substrate, and the yield rate was about 95 percent. We found that the yield rate on the 1inch substrate tends to be much higher than that on the 3mm square substrate.<br/>Diamond has outstanding characteristics as a semiconductor, such as wide band gap (5.5 eV), high thermal conductivity (22 W/cmK), and high breakdown field (10 MV/cm). Therefore, diamond is expected to be applied to the next generation’s RF amplifier and power device. However, a problem in fabricating diamond devices is the low yield rate due to the small substrate size. In this work, we fabricated 2DHG diamond MOSFETs on the polycrystalline 1-inch diamond substrate, and we found that the yield rate was greatly improved.<br/>The highly oriented (111) polycrystalline substrate was fabricated by Sumitomo Electric Industries, Ltd. All the devices on the 1-inch substrate are double-finger structure. Firstly, source and drain electrodes were deposited Ti/Pt/Au (20 nm/ 30 nm/ 90 nm). After H-termination and isolation, 200 nm of Al<sub>2</sub>O<sub>3</sub> was deposited as the gate insulator. After that, 300 nm of Al was deposited as the gate electrode. 80 percent of all the devices have the gate length L<sub>G </sub>= 5 µm and the others have L<sub>G </sub>= 2 µm. There are 3 kinds of source-drain length L<sub>SD</sub>, 10 µm, 15 µm, and 20 µm. Also, there are 3 kinds of total gate width W<sub>GT</sub>, 1 mm, 2 mm, and 3 mm.<br/>The highest maximum drain current density was obtained from the device of L<sub>G </sub>= 2 µm, L<sub>SD</sub> = 10 µm, and W<sub>GT</sub> = 1 mm at V<sub>GS</sub> = -40 V and V<sub>DS</sub> = -40 V, and the result was 151 mA/mm. For all the devices that correctly functioned as a FET, the drain current density was in the range of 100 mA/mm to 150 mA/ mm. The decrease in current density was observed as the gate width expanded, but it is assumed that the effect of the grain boundary on the devices is not serious. About 95 percent of yield rate was achieved in this work, and the distribution of the devices that did not function were impartial on the 1-inch substrate. This is because, thanks to the substrate size, photoresists uniformly coated the whole substrate in the fabricating process.<br/>In this work, we fabricated 2DHG diamond MOSFETs on a (111) highly oriented polycrystalline 1-inch diamond substrate and confirmed that the devices correctly functioned as a FET. The highest maximum drain current density was 151 mA/mm, and the yield rate of devices on the 1-inch substrate was greatly improved. Fabricating 2DHG diamond MOSFETs on polycrystalline 1-inch diamond substrate is possible and it contributes to the yield rate improvement.

Keywords

chemical vapor deposition (CVD) (deposition) | diamond

Symposium Organizers

Philippe Bergonzo, Seki Diamond Systems
Chia-Liang Cheng, National Dong Hwa University
David Eon, Institut Neel
Anke Krueger, Stuttgart University

Symposium Support

Platinum
Great Lakes Crystal Technologies

Gold
Element Six

Silver
Plasmability, LLC
Qnami AG
SEKI DIAMOND SYSTEMS

Bronze
Applied Diamond, Inc.
DIAMFAB
Fraunhofer USA, Inc.

Publishing Alliance

MRS publishes with Springer Nature