CMOS-Compatible Electrochemical Synaptic Transistor Arrays for Deep Learning Accelerators

In-memory-computing architectures based on memristive crossbar-arrays can enhance the computing efficiency for deep-learning with massive parallelism. However, to fulfill their potential, the core memory devices must be capable of providing high-speed and symmetric analog programing with small variability, compatible with silicon technology, and scalable into nanometer-size footprint. We present an electrochemical synaptic transistor, built with CMOS-compatible metal oxides and operating by shuffling protons within a symmetric gate stack, to meet all these stringent requirements. It can be monolithically integrated with silicon transistors to form pseudo-crossbar arrays where parallel, precise, and symmetric programming of the channel conductance can be executed with gate-voltage pulses. High-speed programing with frequency approaching megahertz, endurance above 100 million read-write pulses, and device critical dimensions down to 150×150 nm² have all been realized.