Investigation of Drain Bias Stress Effect on IGZO TFTs Based Charge Storage Neuromorphic Circuits

Charge storage type neuromorphic synapse circuits such as 2T0C, 3T1C and 6T1C have recently emerged as alternatives to nonideal nonvolatile memories for on-chip training of deep neural networks, particularly in terms of linear and symmetric weight updates [1]. Utilizing amorphous InGaZnO (a-IGZO) thin film transistors as update transistors instead of traditional Si CMOS enables long data retention and low power consumption due to their superior low leakage characteristics [2]. However, the reliability of the IGZO TFTs remains a critical challenge, particularly regarding oxygen vacancies in the active channel, gate insulator, and channel/gate insulator interface [3]. While previous research has extensively studied stability problems under positive bias stress (PBS), negative bias stress (NBS), and hot carrier stress (HCS), investigations on the impact of drain bias stress (DBS) on IGZO TFTs are limited. During the off-state, where no programming occurs and weights are maintained in the storage capacitor, the update transistors are exposed to drain and off-state gate bias stress. The off-state accounts for the majority of time in the operational scenario in charge storage type neuromorphic circuits, thus highlighting the significance of DBS stability analysis. This study focuses on investigating the effect of DBS at the transistor level, modeling degradation and unveiling its mechanisms. Furthermore, the impact of DBS on IGZO TFTs based charge storage neuromorphic circuits was assessed using the proposed model.<br/>Electrical measurements were conducted to assess the reliability at the unit transistor level. The evaluation of gate bias stress, including both PBS and NBS, revealed little degradation in terms of threshold voltage (Vth), subthreshold swing (SS), and on-current. On the other hand, during the evaluation of drain bias stress, Vth and SS demonstrated little change, while a noticeable on-current degradation was observed. Additionally we simulated the off-state by applying both drain bias and negative gate bias simultaneously, it was observed that the greater the negative bias, the more significant on-current degradation occurred. Complementary measurements, including capacitance-voltage measurements and the evaluation of transistors with various dimensions, were performed in order to elucidate degradation mechanisms and indicate the physical meaning of degradation through a stretched exponential model. The degradation model parameters, such as the time constant of electron trapping and the saturation point of current degradation, demonstrate an increased degradation with more negative gate bias. Using the proposed degradation model, the weight change of 3T1C neuromorphic circuits after cycling endurance could be successfully predicted. Furthermore, the impact of DBS on training and inference accuracy was investigated. Leveraging the knowledge gained from this study enables the design of more reliable IGZO TFTs based neuromorphic circuits and their operation, advancing the development of robust and efficient neuromorphic systems.<br/><br/><b>References</b><br/>[1] Y. Li et al., "Capacitor-based cross-point array for analog neural network with record symmetry and linearity." 2018 IEEE Symp. VLSI Technol. IEEE, 2018.<br/>[2] M. Caselli et al., “Write-verify scheme for IGZO DRAM in analog in-memory computing.” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2022.<br/>[3] J. F. Conley, Jr, “Instabilities in amorphous oxide semiconductor thin film transistors.” IEEE Trans. Device Mater. Rel., vol. 10, no. 4, pp. 460–475, Dec. 2010.<br/><br/><b>Acknowledgements</b><br/>This research was supported by National R&D Program through the National Research Foundation of Korea(NRF) funded by Ministry of Science and ICT (2020M3F3A2A01081240). This work was supported by Samsung Electronics Co., Ltd (A0426-20190012).<br/><br/><b>*Corresponding Author :</b> Sangbum Kim; E-mail: [email protected]