MRS Meetings and Events

 

EQ01.11.05 2022 MRS Spring Meeting

High Aspect Ratio β-Ga2O3 FinFETs with Near-Zero Hystersis and Low On-Resistance by Matel-Assisted Chemical Etching

When and Where

May 13, 2022
2:45pm - 3:00pm

Hawai'i Convention Center, Level 3, 318B

Presenter

Co-Author(s)

Xiuling Li2,1,Hsien-Chih Huang1,Zhongjie Ren2,A F M Anhar Uddin Bhuiyan3,Zixuan Feng3,Andrew Green4,Keson Chabak4,Hongping Zhao3

University of Illinois Urbana-Champaign1,The University of Texas at Austin2,The Ohio State University3,AirForce Research Laboratory4

Abstract

Xiuling Li2,1,Hsien-Chih Huang1,Zhongjie Ren2,A F M Anhar Uddin Bhuiyan3,Zixuan Feng3,Andrew Green4,Keson Chabak4,Hongping Zhao3

University of Illinois Urbana-Champaign1,The University of Texas at Austin2,The Ohio State University3,AirForce Research Laboratory4
Beta-Gallium Oxide (β-Ga<sub>2</sub>O<sub>3</sub>) is a promising material for power electronics due to its ultra-wide band gap of ~ 4.8 eV, a reasonable electron mobility, and the availability of bulk substrates. Nonetheless, β-Ga<sub>2</sub>O<sub>3</sub> transistors reported so far still suffer from low current density compared to GaN devices. Thus, forming high aspect ratio channel structures to achieve lower on-resistance is still crucial for β-Ga<sub>2</sub>O<sub>3</sub> transistors. Although through RIE, β-Ga<sub>2</sub>O<sub>3</sub> vertical transistors with 9.27 aspect ratio has been fabricated,[1] the high energy ion induced damage from RIE degrades the device performance, leading to a limited effective channel mobility. In addition, the ion-induced damages result in a hysteresis in all β-Ga<sub>2</sub>O<sub>3</sub> transistor utilizing RIE process (ref?). On the other hand, β-Ga<sub>2</sub>O<sub>3</sub> fins with high aspect ratio and low interface trap density have been demonstrated by the metal-assisted chemical etching (MacEtch) process (ref). Moreover, an almost hysteresis-free CV loop was achieved on the MacEtch-formed β-Ga<sub>2</sub>O<sub>3</sub> structures, making it suitable for β-Ga<sub>2</sub>O<sub>3</sub> transistor fabrication. In this work, we demonstrate hysteresis-free β-Ga<sub>2</sub>O<sub>3</sub> FinFETs with 1.5 mΩ-cm<sup>2</sup> specific on-resistance (R<sub>on,sp</sub>) and over 10:1 aspect ratio through the MacEtch process.<br/>A 2 μm-thick lightly doped β-Ga<sub>2</sub>O<sub>3</sub> layer was grown on a (010) Fe-doped semi-insulating substrate by MOCVD, with Si doping concentration of ~ 4×10<sup>17</sup> cm<sup>-3</sup>. Then, channel and source/drain region were defined through lithography followed by 20 nm Pt MacEtch catalyst deposition with an ebeam evaporator. After a standard lift-off process, the samples were immersed in a mixture of hydrofluoric acid (HF, 49%) and potassium persulfate (K<sub>2</sub>S<sub>2</sub>O<sub>8</sub>) under deep UV illumination to etch and form fin-shaped channels and source/drain mesa. Then, Al<sub>2</sub>O<sub>3</sub> was deposited through an ALD process followed by 1 min RTA with N<sub>2</sub> ambient. A Ti/Au gold gate electrodes were sequentially deposited on the high-k layer to form the gate stack. Finally, 1 min RTA with N<sub>2</sub> ambient was applied for source/drain ohmic contact formation. Through the MacEtch process, β-Ga<sub>2</sub>O<sub>3</sub> FinFETs with high aspect ratio channels and smooth sidewalls were produced. The top width and fin height are ~ 170nm and ~2.1 μm, respectively, leading to an overall 10:1 aspect ratio. In addition, slight lateral etching on the β-Ga<sub>2</sub>O<sub>3</sub> fins also occurred during the MacEtch process, resulting in the trapezoid-like channel shapes.<br/>DC transfer characteristics of the β-Ga<sub>2</sub>O<sub>3</sub> FinFETs were measured and the drive current obtained is ~1.9×10<sup>-5</sup>A (4.34A/m when normalized to 2×Fin height + top width) under V<sub>ds</sub>=5V, V<sub>ov</sub>=5V and L<sub>g</sub>=1μm. The on/off ratio is around 10<sup>6</sup> and gate leakage current is at only ~ 10 pA level, suggesting a gate stack with good electrostatic control and low leakage. A dependence of threshold voltages on the fin dimension is also observed, causing the FinFETs to shift from depletion mode (normally on) to enhancement mode (normally off) as the fin width decreases. This tunability of the threshold voltage provides the freedom to choose transistor operation mode depends on the application. The subthreshold swings (SS) are extracted to be 101 mV/dec., indicating the interface trap density is low on the MacEtch-formed sidewalls. Moreover, all the transfer characteristics demonstrate almost zero hysteresis. The largest hysteresis is only 55 mV clockwise, which is small compared to the typical 120 – 800 mV hysteresis of reported β-Ga<sub>2</sub>O<sub>3</sub> FETs.[1-3] This hysteresis-free characteristic could be attributed to the absence of RIE-induced ion damages and traps by the virtual of the MacEtch. The R<sub>on,sp</sub> extracted from the slope of low V<sub>ds</sub> region is 1.5mΩ-cm<sup>2</sup> with V<sub>ov</sub> = 6 V, which is low compared to other published β-Ga<sub>2</sub>O<sub>3</sub> FETs (ref). Detailed output characteristics and breakdown measurement of β-Ga<sub>2</sub>O<sub>3</sub> FinFET will be presented.<br/>Acknowledgement: NSF ECCS 18-09946.<br/>[1] W.Li, et al., 2019 IEDM, 2019. [2] K.Chabak et al., APL, 2016 [3] Z.Hu et al., EDL, 2018

Keywords

Ga | nanostructure

Symposium Organizers

Robert Kaplar, Sandia National Laboratories
Srabanti Chowdhury, Stanford University
Yoshinao Kumagai, Tokyo University of Agriculture and Technology
Julien Pernot, University of Grenoble Alpes

Publishing Alliance

MRS publishes with Springer Nature